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unicore |
---------------------------------------------------------------------
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---- ----
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---- FFT Filter IP core ----
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---- ----
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---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
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---- Company: Unicore Systems http://unicore.co.ua ----
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---- ----
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---- Downloaded from: http://www.opencores.org ----
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---- ----
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---------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2006-2010 Unicore Systems LTD ----
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---- www.unicore.co.ua ----
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---- o.uzenkov@unicore.co.ua ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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---- ----
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---- THIS SOFTWARE IS PROVIDED "AS IS" ----
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---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
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---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
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---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
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---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
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---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
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---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
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---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
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---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
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---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
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---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
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---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
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---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
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---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
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---- ----
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---------------------------------------------------------------------
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-- File: RAMB4_S18_S18.vhd
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-- created by Design Wizard: 12/13/99 08:52:59
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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entity RAMB16_S18_S18 is
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port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
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DIB : in STD_LOGIC_VECTOR (15 downto 0);
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DIPA : in STD_LOGIC_VECTOR (1 downto 0);
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DIPB : in STD_LOGIC_VECTOR (1 downto 0);
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ENA : in STD_ULOGIC;
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ENB : in STD_ULOGIC;
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WEA : in STD_ULOGIC;
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WEB : in STD_ULOGIC;
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SSRA : in STD_ULOGIC;
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SSRB : in STD_ULOGIC;
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CLKA : in STD_ULOGIC;
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CLKB : in STD_ULOGIC;
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ADDRA : in STD_LOGIC_VECTOR (9 downto 0);
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ADDRB : in STD_LOGIC_VECTOR (9 downto 0);
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DOA : out STD_LOGIC_VECTOR (15 downto 0);
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DOB : out STD_LOGIC_VECTOR (15 downto 0);
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DOPA : out STD_LOGIC_VECTOR (1 downto 0);
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DOPB : out STD_LOGIC_VECTOR (1 downto 0)
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);
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end RAMB16_S18_S18;
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architecture BEH of RAMB16_S18_S18 is
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type mem is array (0 to 1023) of std_logic_vector (17 downto 0);
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signal adra,adrb:std_logic_vector (9 downto 0):=(others=>'0');
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signal data_a,data_b:std_logic_vector (17 downto 0);
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signal wea_1,web_1: STD_LOGIC;
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begin
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process(clka,ssra,clkb,ssrb,adra,adrb,wea,web,dia,dib)
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variable ram: mem:=(others=>"000000000000000000") ;
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variable ia,ib: integer;
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variable a,b:std_logic_vector (17 downto 0);
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begin
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ia:= conv_integer(To_X01(adra));
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a:= ram(ia);
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dopa<=a(17 downto 16);
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doa <= a(15 downto 0);
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if wea_1 = '1' then
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ram(ia) :=data_a;
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end if;
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ib:= conv_integer(To_X01(adrb));
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b:= ram(ib);
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dopb<=b(17 downto 16);
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dob <= b(15 downto 0);
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if web_1 = '1' then
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ram(ib) := data_b;
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end if;
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if ssra = '1' then
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dopa<="00";
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doa <= X"0000";
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adra <= "0000000000";
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wea_1 <= '0';
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elsif clka = '1' and clka'event then
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data_a <= dipa&dia;
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adra(9 downto 0) <= addra;
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wea_1 <= wea;
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end if;
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if ssrb = '1' then
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dopb<="00";
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dob <= X"0000";
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adrb <= "0000000000";
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web_1 <= '0';
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elsif clkb = '1' and clkb'event then
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data_b <= dipb&dib;
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adrb(9 downto 0) <= addrb;
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web_1 <= web;
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end if;
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end process;
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end BEH;
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