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------------------------------------------------------------------------------
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-- Title : fixed_extensions (VHDL fixed-point arithmetic --
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-- : extensions package). --
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-- Author : Nikolaos Kavvadias --
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-- Contact : nikolaos.kavvadias@gmail.com --
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-- : http://www.nkavvadias.com --
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-- Release Date : 25 July 2011 --
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-- Version : 0.0.5 --
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--------------------:---------------------------------------------------------
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-- Revision history : --
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-- v0.0.5 : 2011-07-25 --
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-- : Initial release. --
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------------------------------------------------------------------------------
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1. INTRODUCTION
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---------------
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"fixed_extensions_pkg" is a fixed-point arithmetic package written in VHDL
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according to the VHDL-2008 update of the standard. It uses VHDL-2008 back-
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compatible libraries (by David Bishop) that are included in this distribution
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for the sake of completeness.
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Currently, the "fixed_extensions_pkg" package implements the following:
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- ceil : round towards plus infinity.
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- fix : round towards zero.
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- floor : round towards minus infinity.
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- round : round to nearest; ties to greatest absolute value.
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- nearest : round to nearest; ties to plus infinity.
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- convergent: round to nearest; ties to closest even.
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- bitinsert : bit-field insertion to word
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- bitextract: bit-field extraction from word
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"fixed_extensions" is distributed along with a tool (gentestround) to generate
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customized VHDL test designs.
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2. FILE LISTING
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---------------
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The fixed_extensions distributions includes the following files:
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/fixed_extensions-
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/bench/vhdl
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testrounding_tb.vhd Standard testbench file.
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/doc
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AUTHORS List of "fixed_extensions" authors.
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BUGS Bug list.
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ChangeLog A log for code changes.
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COPYING.BSD The Modified BSD License.
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README This file.
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THANKS Acknowledgements.
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TODO A list of future enhancements.
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/gen/vhdl
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testroundings.vhd Auto-generated test file for sfixed arithmetic.
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testroundingu.vhd Auto-generated test file for ufixed arithmetic.
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/rtl/vhdl
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fixed_extensions_pkg_sim.vhd
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The VHDL package for simulation-oriented use.
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fixed_extensions_pkg_synth.vhd
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The VHDL package for synthesis-oriented use.
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/sim/rtl_sim/bin
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run.sh A bash script for testing the package.
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testroundings.do Modelsim macro script for testing sfixed arithmetic.
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testroundings.sh Bash script for running an sfixed simulation.
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testroundingu.do Modelsim macro script for testing ufixed arithmetic.
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testroundingu.sh Bash script for running an ufixed simulation.
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/sim/rtl_sim/src
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fixed_float_types_custom.vhd
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VHDL package with definitions for fixed-point arith.
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fixed_pkg_c.vhd VHDL package implementing fixed-point arithmetic.
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math_real.vhd VHDL package with some real arithmetic functions.
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/sw
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gentestround.c Test design generator written in ANSI C.
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Makefile Makefile for compiling the test design generator.
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3. FIXED_EXTENSIONS USAGE
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-------------------------
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The fixed_extensions package can be used as follows:
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$./run.sh
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4. PREREQUISITIES
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-----------------
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- Standard UNIX-based tools (tested on cygwin/x86)
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make, bash
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- [optional] Mentor Modelsim ("mti") (http://www.mentor.com)
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Provides a simulation environment to run the tests.
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5. CONTACT
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----------
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You may contact me for further questions/suggestions/corrections at:
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Nikolaos Kavvadias
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http://www.nkavvadias.com
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