URL https://opencores.org/ocsvn/fixed_point_arithmetic_parameterized/fixed_point_arithmetic_parameterized/trunk

Subversion Repositories fixed_point_arithmetic_parameterized

[/] [fixed_point_arithmetic_parameterized/] [trunk/] [testfixtures/] [qadd_tf.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	samis13	`timescale 1ns / 1ps
2
3			`////////////////////////////////////////////////////////////////////////////////`
4			`// Company:`
5			`// Engineer:`
6			`//`
7			`// Create Date: 09:36:47 08/24/2011`
8			`// Design Name: q15_add`
9			`// Module Name: C:/Documents and Settings/samskalicky/Desktop/PLE/q_15_add_tf.v`
10			`// Project Name: PLE`
11			`// Target Device:`
12			`// Tool versions:`
13			`// Description:`
14			`//`
15			`// Verilog Test Fixture created by ISE for module: q15_add`
16			`//`
17			`// Dependencies:`
18			`//`
19			`// Revision:`
20			`// Revision 0.01 - File Created`
21			`// Additional Comments:`
22			`//`
23			`////////////////////////////////////////////////////////////////////////////////`
24
25			`module qadd_tf;`
26
27			`// Inputs`
28			`reg [31:0] a;`
29			`reg [31:0] b;`
30
31			`// Outputs`
32			`wire [31:0] c;`
33
34			`// Instantiate the Unit Under Test (UUT)`
35			`qadd #(23,32) uut (a, b, c);`
36
37			`initial begin`
38			`// Initialize Inputs`
39			`a = 0;`
40			`b = 0;`
41
42			`#100;`
43
44			`a = 1;`
45			`b = 0;`
46
47			`#100;`
48
49			`a = 0;`
50			`b = 1;`
51
52			`#100;`
53
54			`a = 1;`
55			`b = 1;`
56
57			`#100;`
58
59			`a[31:23] = 64;`
60			`a[22:0] = 125;`
61			`b[31:23] = 0;`
62			`b[22:0] = 75;`
63
64			`#100;`
65
66			`a[30]=0;`
67			`a[30:23] = 64;`
68			`a[22:0] = 1048576;`
69			`b[31]=1;`
70			`b[30:23] = 0; //-1`
71			`b[22:0] = 6291456;`
72
73			`// Add stimulus here`
74			`#100;`
75			`end`
76
77			`endmodule`
78