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songching |
---- $Author: songching $
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---- $Date: 2004-04-07 15:38:47 $
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---- $Revision: 1.1 $
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----------------------------------------------------------------------
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---- $Log: not supported by cvs2svn $
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----------------------------------------------------------------------
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----
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---- Copyright (C) 2004 Song Ching Koh, Free Software Foundation, Inc. and OPENCORES.ORG
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----
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---- This program is free software; you can redistribute it and/or modify
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---- it under the terms of the GNU General Public License as published by
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---- the Free Software Foundation; either version 2 of the License, or
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---- (at your option) any later version.
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----
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---- This program is distributed in the hope that it will be useful,
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---- but WITHOUT ANY WARRANTY; without even the implied warranty of
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---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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---- GNU General Public License for more details.
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----
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---- You should have received a copy of the GNU General Public License
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---- along with this program; if not, write to the Free Software
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---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity MUX1 is
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Port ( Input : in std_logic_vector(63 downto 0);
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Sel : in std_logic_vector(2 downto 0);
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Output : out std_logic_vector(7 downto 0));
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end MUX1;
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architecture mux1_structure of MUX1 is
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begin
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mux: process(Input, Sel)
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begin
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case SEL is
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when "000" => Output <= Input(7 downto 0);
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when "001" => Output <= Input(15 downto 8);
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when "010" => Output <= Input(23 downto 16);
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when "011" => Output <= Input(31 downto 24);
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when "100" => Output <= Input(39 downto 32);
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when "101" => Output <= Input(47 downto 40);
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when "110" => Output <= Input(55 downto 48);
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when others => Output <= Input(63 downto 56);
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end case;
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end process mux;
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end mux1_structure;
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