| 1 |
4 |
songching |
---- $Author: songching $
|
| 2 |
|
|
---- $Date: 2004-04-07 15:38:47 $
|
| 3 |
|
|
---- $Revision: 1.1 $
|
| 4 |
|
|
----------------------------------------------------------------------
|
| 5 |
|
|
---- $Log: not supported by cvs2svn $
|
| 6 |
|
|
----------------------------------------------------------------------
|
| 7 |
|
|
----
|
| 8 |
|
|
---- Copyright (C) 2004 Song Ching Koh, Free Software Foundation, Inc. and OPENCORES.ORG
|
| 9 |
|
|
----
|
| 10 |
|
|
---- This program is free software; you can redistribute it and/or modify
|
| 11 |
|
|
---- it under the terms of the GNU General Public License as published by
|
| 12 |
|
|
---- the Free Software Foundation; either version 2 of the License, or
|
| 13 |
|
|
---- (at your option) any later version.
|
| 14 |
|
|
----
|
| 15 |
|
|
---- This program is distributed in the hope that it will be useful,
|
| 16 |
|
|
---- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| 17 |
|
|
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
| 18 |
|
|
---- GNU General Public License for more details.
|
| 19 |
|
|
----
|
| 20 |
|
|
---- You should have received a copy of the GNU General Public License
|
| 21 |
|
|
---- along with this program; if not, write to the Free Software
|
| 22 |
|
|
---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
| 23 |
|
|
|
| 24 |
|
|
library IEEE;
|
| 25 |
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
| 26 |
|
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
| 27 |
|
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
| 28 |
|
|
|
| 29 |
|
|
-- Uncomment the following lines to use the declarations that are
|
| 30 |
|
|
-- provided for instantiating Xilinx primitive components.
|
| 31 |
|
|
--library UNISIM;
|
| 32 |
|
|
--use UNISIM.VComponents.all;
|
| 33 |
|
|
|
| 34 |
|
|
entity max8to8 is
|
| 35 |
|
|
Port ( A : in std_logic_vector(63 downto 0);
|
| 36 |
|
|
B : in std_logic_vector(63 downto 0);
|
| 37 |
|
|
C : out std_logic_vector(63 downto 0));
|
| 38 |
|
|
end max8to8;
|
| 39 |
|
|
|
| 40 |
|
|
architecture max8to8_structure of max8to8 is
|
| 41 |
|
|
COMPONENT maximum
|
| 42 |
|
|
PORT(
|
| 43 |
|
|
A : IN std_logic_vector(7 downto 0);
|
| 44 |
|
|
B : IN std_logic_vector(7 downto 0);
|
| 45 |
|
|
C : OUT std_logic_vector(7 downto 0)
|
| 46 |
|
|
);
|
| 47 |
|
|
END COMPONENT;
|
| 48 |
|
|
begin
|
| 49 |
|
|
Inst_maximum7to0: maximum PORT MAP(
|
| 50 |
|
|
A => A(7 downto 0),
|
| 51 |
|
|
B => B(7 downto 0),
|
| 52 |
|
|
C => C(7 downto 0)
|
| 53 |
|
|
);
|
| 54 |
|
|
Inst_maximum15to8: maximum PORT MAP(
|
| 55 |
|
|
A => A(15 downto 8),
|
| 56 |
|
|
B => B(15 downto 8),
|
| 57 |
|
|
C => C(15 downto 8)
|
| 58 |
|
|
);
|
| 59 |
|
|
Inst_maximum23to16: maximum PORT MAP(
|
| 60 |
|
|
A => A(23 downto 16),
|
| 61 |
|
|
B => B(23 downto 16),
|
| 62 |
|
|
C => C(23 downto 16)
|
| 63 |
|
|
);
|
| 64 |
|
|
Inst_maximum31to24: maximum PORT MAP(
|
| 65 |
|
|
A => A(31 downto 24),
|
| 66 |
|
|
B => B(31 downto 24),
|
| 67 |
|
|
C => C(31 downto 24)
|
| 68 |
|
|
);
|
| 69 |
|
|
Inst_maximum39to32: maximum PORT MAP(
|
| 70 |
|
|
A => A(39 downto 32),
|
| 71 |
|
|
B => B(39 downto 32),
|
| 72 |
|
|
C => C(39 downto 32)
|
| 73 |
|
|
);
|
| 74 |
|
|
Inst_maximum47to40: maximum PORT MAP(
|
| 75 |
|
|
A => A(47 downto 40),
|
| 76 |
|
|
B => B(47 downto 40),
|
| 77 |
|
|
C => C(47 downto 40)
|
| 78 |
|
|
);
|
| 79 |
|
|
Inst_maximum55to48: maximum PORT MAP(
|
| 80 |
|
|
A => A(55 downto 48),
|
| 81 |
|
|
B => B(55 downto 48),
|
| 82 |
|
|
C => C(55 downto 48)
|
| 83 |
|
|
);
|
| 84 |
|
|
Inst_maximum63to56: maximum PORT MAP(
|
| 85 |
|
|
A => A(63 downto 56),
|
| 86 |
|
|
B => B(63 downto 56),
|
| 87 |
|
|
C => C(63 downto 56)
|
| 88 |
|
|
);
|
| 89 |
|
|
end max8to8_structure;
|
