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[/] [flha/] [trunk/] [VHDL/] [Core/] [min1to8_translate.vhd] - Blame information for rev 6

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1 4 songching 
-- Xilinx Vhdl netlist produced by netgen application (version G.26)
2 
-- Command       : -intstyle ise -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim min1to8.ngd min1to8_translate.vhd
3 
-- Input file    : min1to8.ngd
4 
-- Output file   : min1to8_translate.vhd
5 
-- Design name   : min1to8
6 
-- # of Entities : 1
7 
-- Xilinx        : C:/Xilinx
8 
-- Device        : 2s300eft256-7
9 
 
10 
-- This vhdl netlist is a simulation model and uses simulation
11 
-- primitives which may not represent the true implementation of the
12 
-- device, however the netlist is functionally correct and should not
13 
-- be modified. This file cannot be synthesized and should only be used
14 
-- with supported simulation tools.
15 
 
16 
library IEEE;
17 
use IEEE.STD_LOGIC_1164.ALL;
18 
library SIMPRIM;
19 
use SIMPRIM.VCOMPONENTS.ALL;
20 
use SIMPRIM.VPACKAGE.ALL;
21 
 
22 
entity min1to8 is
23 
  port (
24 
    A : in STD_LOGIC_VECTOR ( 7 downto 0 );
25 
    B : in STD_LOGIC_VECTOR ( 63 downto 0 );
26 
    C : out STD_LOGIC_VECTOR ( 63 downto 0 )
27 
  );
28 
end min1to8;
29 
 
30 
architecture Structure of min1to8 is
31 
  signal B_17_IBUF : STD_LOGIC;
32 
  signal B_16_IBUF : STD_LOGIC;
33 
  signal B_18_IBUF : STD_LOGIC;
34 
  signal B_3_IBUF : STD_LOGIC;
35 
  signal B_11_IBUF : STD_LOGIC;
36 
  signal B_4_IBUF : STD_LOGIC;
37 
  signal B_12_IBUF : STD_LOGIC;
38 
  signal B_5_IBUF : STD_LOGIC;
39 
  signal B_10_IBUF : STD_LOGIC;
40 
  signal B_13_IBUF : STD_LOGIC;
41 
  signal B_0_IBUF : STD_LOGIC;
42 
  signal B_6_IBUF : STD_LOGIC;
43 
  signal B_9_IBUF : STD_LOGIC;
44 
  signal B_14_IBUF : STD_LOGIC;
45 
  signal B_1_IBUF : STD_LOGIC;
46 
  signal B_7_IBUF : STD_LOGIC;
47 
  signal B_8_IBUF : STD_LOGIC;
48 
  signal B_15_IBUF : STD_LOGIC;
49 
  signal B_2_IBUF : STD_LOGIC;
50 
  signal C_63_OBUF : STD_LOGIC;
51 
  signal C_62_OBUF : STD_LOGIC;
52 
  signal C_61_OBUF : STD_LOGIC;
53 
  signal C_60_OBUF : STD_LOGIC;
54 
  signal C_59_OBUF : STD_LOGIC;
55 
  signal C_58_OBUF : STD_LOGIC;
56 
  signal C_57_OBUF : STD_LOGIC;
57 
  signal C_56_OBUF : STD_LOGIC;
58 
  signal C_55_OBUF : STD_LOGIC;
59 
  signal C_54_OBUF : STD_LOGIC;
60 
  signal C_53_OBUF : STD_LOGIC;
61 
  signal C_52_OBUF : STD_LOGIC;
62 
  signal C_51_OBUF : STD_LOGIC;
63 
  signal C_50_OBUF : STD_LOGIC;
64 
  signal C_49_OBUF : STD_LOGIC;
65 
  signal C_48_OBUF : STD_LOGIC;
66 
  signal C_47_OBUF : STD_LOGIC;
67 
  signal C_46_OBUF : STD_LOGIC;
68 
  signal C_45_OBUF : STD_LOGIC;
69 
  signal C_44_OBUF : STD_LOGIC;
70 
  signal C_43_OBUF : STD_LOGIC;
71 
  signal C_42_OBUF : STD_LOGIC;
72 
  signal C_41_OBUF : STD_LOGIC;
73 
  signal C_40_OBUF : STD_LOGIC;
74 
  signal C_39_OBUF : STD_LOGIC;
75 
  signal C_38_OBUF : STD_LOGIC;
76 
  signal C_37_OBUF : STD_LOGIC;
77 
  signal C_36_OBUF : STD_LOGIC;
78 
  signal C_35_OBUF : STD_LOGIC;
79 
  signal C_34_OBUF : STD_LOGIC;
80 
  signal C_33_OBUF : STD_LOGIC;
81 
  signal C_32_OBUF : STD_LOGIC;
82 
  signal C_31_OBUF : STD_LOGIC;
83 
  signal C_30_OBUF : STD_LOGIC;
84 
  signal C_29_OBUF : STD_LOGIC;
85 
  signal C_28_OBUF : STD_LOGIC;
86 
  signal C_27_OBUF : STD_LOGIC;
87 
  signal C_26_OBUF : STD_LOGIC;
88 
  signal C_25_OBUF : STD_LOGIC;
89 
  signal C_24_OBUF : STD_LOGIC;
90 
  signal C_23_OBUF : STD_LOGIC;
91 
  signal C_22_OBUF : STD_LOGIC;
92 
  signal C_21_OBUF : STD_LOGIC;
93 
  signal C_20_OBUF : STD_LOGIC;
94 
  signal C_19_OBUF : STD_LOGIC;
95 
  signal C_18_OBUF : STD_LOGIC;
96 
  signal C_17_OBUF : STD_LOGIC;
97 
  signal C_16_OBUF : STD_LOGIC;
98 
  signal C_15_OBUF : STD_LOGIC;
99 
  signal C_14_OBUF : STD_LOGIC;
100 
  signal C_13_OBUF : STD_LOGIC;
101 
  signal C_12_OBUF : STD_LOGIC;
102 
  signal C_11_OBUF : STD_LOGIC;
103 
  signal C_10_OBUF : STD_LOGIC;
104 
  signal C_9_OBUF : STD_LOGIC;
105 
  signal C_8_OBUF : STD_LOGIC;
106 
  signal C_7_OBUF : STD_LOGIC;
107 
  signal C_6_OBUF : STD_LOGIC;
108 
  signal C_5_OBUF : STD_LOGIC;
109 
  signal C_4_OBUF : STD_LOGIC;
110 
  signal C_3_OBUF : STD_LOGIC;
111 
  signal C_2_OBUF : STD_LOGIC;
112 
  signal C_1_OBUF : STD_LOGIC;
113 
  signal C_0_OBUF : STD_LOGIC;
114 
  signal A_7_IBUF : STD_LOGIC;
115 
  signal A_6_IBUF : STD_LOGIC;
116 
  signal A_5_IBUF : STD_LOGIC;
117 
  signal A_4_IBUF : STD_LOGIC;
118 
  signal A_3_IBUF : STD_LOGIC;
119 
  signal A_2_IBUF : STD_LOGIC;
120 
  signal A_1_IBUF : STD_LOGIC;
121 
  signal A_0_IBUF : STD_LOGIC;
122 
  signal B_63_IBUF : STD_LOGIC;
123 
  signal B_62_IBUF : STD_LOGIC;
124 
  signal B_61_IBUF : STD_LOGIC;
125 
  signal B_60_IBUF : STD_LOGIC;
126 
  signal B_59_IBUF : STD_LOGIC;
127 
  signal B_58_IBUF : STD_LOGIC;
128 
  signal B_57_IBUF : STD_LOGIC;
129 
  signal B_56_IBUF : STD_LOGIC;
130 
  signal B_55_IBUF : STD_LOGIC;
131 
  signal B_54_IBUF : STD_LOGIC;
132 
  signal B_53_IBUF : STD_LOGIC;
133 
  signal B_52_IBUF : STD_LOGIC;
134 
  signal B_51_IBUF : STD_LOGIC;
135 
  signal B_50_IBUF : STD_LOGIC;
136 
  signal B_49_IBUF : STD_LOGIC;
137 
  signal B_48_IBUF : STD_LOGIC;
138 
  signal B_47_IBUF : STD_LOGIC;
139 
  signal B_46_IBUF : STD_LOGIC;
140 
  signal B_45_IBUF : STD_LOGIC;
141 
  signal B_44_IBUF : STD_LOGIC;
142 
  signal B_43_IBUF : STD_LOGIC;
143 
  signal B_42_IBUF : STD_LOGIC;
144 
  signal B_41_IBUF : STD_LOGIC;
145 
  signal B_40_IBUF : STD_LOGIC;
146 
  signal B_39_IBUF : STD_LOGIC;
147 
  signal B_38_IBUF : STD_LOGIC;
148 
  signal B_37_IBUF : STD_LOGIC;
149 
  signal B_36_IBUF : STD_LOGIC;
150 
  signal B_35_IBUF : STD_LOGIC;
151 
  signal B_34_IBUF : STD_LOGIC;
152 
  signal B_33_IBUF : STD_LOGIC;
153 
  signal B_32_IBUF : STD_LOGIC;
154 
  signal B_31_IBUF : STD_LOGIC;
155 
  signal B_30_IBUF : STD_LOGIC;
156 
  signal B_29_IBUF : STD_LOGIC;
157 
  signal B_28_IBUF : STD_LOGIC;
158 
  signal B_27_IBUF : STD_LOGIC;
159 
  signal B_26_IBUF : STD_LOGIC;
160 
  signal B_25_IBUF : STD_LOGIC;
161 
  signal B_24_IBUF : STD_LOGIC;
162 
  signal B_23_IBUF : STD_LOGIC;
163 
  signal B_22_IBUF : STD_LOGIC;
164 
  signal B_21_IBUF : STD_LOGIC;
165 
  signal B_20_IBUF : STD_LOGIC;
166 
  signal B_19_IBUF : STD_LOGIC;
167 
  signal Inst_minimum63to56_n0000 : STD_LOGIC;
168 
  signal Inst_minimum55to48_n0000 : STD_LOGIC;
169 
  signal Inst_minimum47to40_n0000 : STD_LOGIC;
170 
  signal Inst_minimum39to32_n0000 : STD_LOGIC;
171 
  signal Inst_minimum31to24_n0000 : STD_LOGIC;
172 
  signal Inst_minimum23to16_n0000 : STD_LOGIC;
173 
  signal Inst_minimum15to8_n0000 : STD_LOGIC;
174 
  signal Inst_minimum7to0_n0000 : STD_LOGIC;
175 
  signal N183 : STD_LOGIC;
176 
  signal Inst_minimum7to0_Mcompar_n0000_inst_lut2_7 : STD_LOGIC;
177 
  signal Inst_minimum7to0_Mcompar_n0000_inst_cy_6 : STD_LOGIC;
178 
  signal Inst_minimum7to0_Mcompar_n0000_inst_lut2_6 : STD_LOGIC;
179 
  signal Inst_minimum7to0_Mcompar_n0000_inst_cy_5 : STD_LOGIC;
180 
  signal Inst_minimum7to0_Mcompar_n0000_inst_lut2_5 : STD_LOGIC;
181 
  signal Inst_minimum7to0_Mcompar_n0000_inst_cy_4 : STD_LOGIC;
182 
  signal Inst_minimum7to0_Mcompar_n0000_inst_lut2_4 : STD_LOGIC;
183 
  signal Inst_minimum7to0_Mcompar_n0000_inst_cy_3 : STD_LOGIC;
184 
  signal Inst_minimum7to0_Mcompar_n0000_inst_lut2_3 : STD_LOGIC;
185 
  signal Inst_minimum7to0_Mcompar_n0000_inst_cy_2 : STD_LOGIC;
186 
  signal Inst_minimum7to0_Mcompar_n0000_inst_lut2_2 : STD_LOGIC;
187 
  signal Inst_minimum7to0_Mcompar_n0000_inst_cy_1 : STD_LOGIC;
188 
  signal Inst_minimum7to0_Mcompar_n0000_inst_lut2_1 : STD_LOGIC;
189 
  signal Inst_minimum7to0_Mcompar_n0000_inst_cy_0 : STD_LOGIC;
190 
  signal Inst_minimum7to0_Mcompar_n0000_inst_lut2_0 : STD_LOGIC;
191 
  signal Inst_minimum15to8_Mcompar_n0000_inst_cy_0 : STD_LOGIC;
192 
  signal Inst_minimum15to8_Mcompar_n0000_inst_lut2_0 : STD_LOGIC;
193 
  signal Inst_minimum15to8_Mcompar_n0000_inst_lut2_7 : STD_LOGIC;
194 
  signal Inst_minimum15to8_Mcompar_n0000_inst_cy_6 : STD_LOGIC;
195 
  signal Inst_minimum15to8_Mcompar_n0000_inst_lut2_6 : STD_LOGIC;
196 
  signal Inst_minimum15to8_Mcompar_n0000_inst_cy_5 : STD_LOGIC;
197 
  signal Inst_minimum15to8_Mcompar_n0000_inst_lut2_5 : STD_LOGIC;
198 
  signal Inst_minimum15to8_Mcompar_n0000_inst_cy_4 : STD_LOGIC;
199 
  signal Inst_minimum15to8_Mcompar_n0000_inst_lut2_4 : STD_LOGIC;
200 
  signal Inst_minimum15to8_Mcompar_n0000_inst_cy_3 : STD_LOGIC;
201 
  signal Inst_minimum15to8_Mcompar_n0000_inst_lut2_3 : STD_LOGIC;
202 
  signal Inst_minimum15to8_Mcompar_n0000_inst_cy_2 : STD_LOGIC;
203 
  signal Inst_minimum15to8_Mcompar_n0000_inst_lut2_2 : STD_LOGIC;
204 
  signal Inst_minimum15to8_Mcompar_n0000_inst_cy_1 : STD_LOGIC;
205 
  signal Inst_minimum15to8_Mcompar_n0000_inst_lut2_1 : STD_LOGIC;
206 
  signal Inst_minimum23to16_Mcompar_n0000_inst_cy_0 : STD_LOGIC;
207 
  signal Inst_minimum23to16_Mcompar_n0000_inst_lut2_0 : STD_LOGIC;
208 
  signal Inst_minimum23to16_Mcompar_n0000_inst_lut2_7 : STD_LOGIC;
209 
  signal Inst_minimum23to16_Mcompar_n0000_inst_cy_6 : STD_LOGIC;
210 
  signal Inst_minimum23to16_Mcompar_n0000_inst_lut2_6 : STD_LOGIC;
211 
  signal Inst_minimum23to16_Mcompar_n0000_inst_cy_5 : STD_LOGIC;
212 
  signal Inst_minimum23to16_Mcompar_n0000_inst_lut2_5 : STD_LOGIC;
213 
  signal Inst_minimum23to16_Mcompar_n0000_inst_cy_4 : STD_LOGIC;
214 
  signal Inst_minimum23to16_Mcompar_n0000_inst_lut2_4 : STD_LOGIC;
215 
  signal Inst_minimum23to16_Mcompar_n0000_inst_cy_3 : STD_LOGIC;
216 
  signal Inst_minimum23to16_Mcompar_n0000_inst_lut2_3 : STD_LOGIC;
217 
  signal Inst_minimum23to16_Mcompar_n0000_inst_cy_2 : STD_LOGIC;
218 
  signal Inst_minimum23to16_Mcompar_n0000_inst_lut2_2 : STD_LOGIC;
219 
  signal Inst_minimum23to16_Mcompar_n0000_inst_cy_1 : STD_LOGIC;
220 
  signal Inst_minimum23to16_Mcompar_n0000_inst_lut2_1 : STD_LOGIC;
221 
  signal Inst_minimum31to24_Mcompar_n0000_inst_cy_0 : STD_LOGIC;
222 
  signal Inst_minimum31to24_Mcompar_n0000_inst_lut2_0 : STD_LOGIC;
223 
  signal Inst_minimum31to24_Mcompar_n0000_inst_lut2_7 : STD_LOGIC;
224 
  signal Inst_minimum31to24_Mcompar_n0000_inst_cy_6 : STD_LOGIC;
225 
  signal Inst_minimum31to24_Mcompar_n0000_inst_lut2_6 : STD_LOGIC;
226 
  signal Inst_minimum31to24_Mcompar_n0000_inst_cy_5 : STD_LOGIC;
227 
  signal Inst_minimum31to24_Mcompar_n0000_inst_lut2_5 : STD_LOGIC;
228 
  signal Inst_minimum31to24_Mcompar_n0000_inst_cy_4 : STD_LOGIC;
229 
  signal Inst_minimum31to24_Mcompar_n0000_inst_lut2_4 : STD_LOGIC;
230 
  signal Inst_minimum31to24_Mcompar_n0000_inst_cy_3 : STD_LOGIC;
231 
  signal Inst_minimum31to24_Mcompar_n0000_inst_lut2_3 : STD_LOGIC;
232 
  signal Inst_minimum31to24_Mcompar_n0000_inst_cy_2 : STD_LOGIC;
233 
  signal Inst_minimum31to24_Mcompar_n0000_inst_lut2_2 : STD_LOGIC;
234 
  signal Inst_minimum31to24_Mcompar_n0000_inst_cy_1 : STD_LOGIC;
235 
  signal Inst_minimum31to24_Mcompar_n0000_inst_lut2_1 : STD_LOGIC;
236 
  signal Inst_minimum39to32_Mcompar_n0000_inst_cy_0 : STD_LOGIC;
237 
  signal Inst_minimum39to32_Mcompar_n0000_inst_lut2_0 : STD_LOGIC;
238 
  signal Inst_minimum39to32_Mcompar_n0000_inst_lut2_7 : STD_LOGIC;
239 
  signal Inst_minimum39to32_Mcompar_n0000_inst_cy_6 : STD_LOGIC;
240 
  signal Inst_minimum39to32_Mcompar_n0000_inst_lut2_6 : STD_LOGIC;
241 
  signal Inst_minimum39to32_Mcompar_n0000_inst_cy_5 : STD_LOGIC;
242 
  signal Inst_minimum39to32_Mcompar_n0000_inst_lut2_5 : STD_LOGIC;
243 
  signal Inst_minimum39to32_Mcompar_n0000_inst_cy_4 : STD_LOGIC;
244 
  signal Inst_minimum39to32_Mcompar_n0000_inst_lut2_4 : STD_LOGIC;
245 
  signal Inst_minimum39to32_Mcompar_n0000_inst_cy_3 : STD_LOGIC;
246 
  signal Inst_minimum39to32_Mcompar_n0000_inst_lut2_3 : STD_LOGIC;
247 
  signal Inst_minimum39to32_Mcompar_n0000_inst_cy_2 : STD_LOGIC;
248 
  signal Inst_minimum39to32_Mcompar_n0000_inst_lut2_2 : STD_LOGIC;
249 
  signal Inst_minimum39to32_Mcompar_n0000_inst_cy_1 : STD_LOGIC;
250 
  signal Inst_minimum39to32_Mcompar_n0000_inst_lut2_1 : STD_LOGIC;
251 
  signal Inst_minimum47to40_Mcompar_n0000_inst_cy_0 : STD_LOGIC;
252 
  signal Inst_minimum47to40_Mcompar_n0000_inst_lut2_0 : STD_LOGIC;
253 
  signal Inst_minimum47to40_Mcompar_n0000_inst_lut2_7 : STD_LOGIC;
254 
  signal Inst_minimum47to40_Mcompar_n0000_inst_cy_6 : STD_LOGIC;
255 
  signal Inst_minimum47to40_Mcompar_n0000_inst_lut2_6 : STD_LOGIC;
256 
  signal Inst_minimum47to40_Mcompar_n0000_inst_cy_5 : STD_LOGIC;
257 
  signal Inst_minimum47to40_Mcompar_n0000_inst_lut2_5 : STD_LOGIC;
258 
  signal Inst_minimum47to40_Mcompar_n0000_inst_cy_4 : STD_LOGIC;
259 
  signal Inst_minimum47to40_Mcompar_n0000_inst_lut2_4 : STD_LOGIC;
260 
  signal Inst_minimum47to40_Mcompar_n0000_inst_cy_3 : STD_LOGIC;
261 
  signal Inst_minimum47to40_Mcompar_n0000_inst_lut2_3 : STD_LOGIC;
262 
  signal Inst_minimum47to40_Mcompar_n0000_inst_cy_2 : STD_LOGIC;
263 
  signal Inst_minimum47to40_Mcompar_n0000_inst_lut2_2 : STD_LOGIC;
264 
  signal Inst_minimum47to40_Mcompar_n0000_inst_cy_1 : STD_LOGIC;
265 
  signal Inst_minimum47to40_Mcompar_n0000_inst_lut2_1 : STD_LOGIC;
266 
  signal Inst_minimum55to48_Mcompar_n0000_inst_cy_0 : STD_LOGIC;
267 
  signal Inst_minimum55to48_Mcompar_n0000_inst_lut2_0 : STD_LOGIC;
268 
  signal Inst_minimum55to48_Mcompar_n0000_inst_lut2_7 : STD_LOGIC;
269 
  signal Inst_minimum55to48_Mcompar_n0000_inst_cy_6 : STD_LOGIC;
270 
  signal Inst_minimum55to48_Mcompar_n0000_inst_lut2_6 : STD_LOGIC;
271 
  signal Inst_minimum55to48_Mcompar_n0000_inst_cy_5 : STD_LOGIC;
272 
  signal Inst_minimum55to48_Mcompar_n0000_inst_lut2_5 : STD_LOGIC;
273 
  signal Inst_minimum55to48_Mcompar_n0000_inst_cy_4 : STD_LOGIC;
274 
  signal Inst_minimum55to48_Mcompar_n0000_inst_lut2_4 : STD_LOGIC;
275 
  signal Inst_minimum55to48_Mcompar_n0000_inst_cy_3 : STD_LOGIC;
276 
  signal Inst_minimum55to48_Mcompar_n0000_inst_lut2_3 : STD_LOGIC;
277 
  signal Inst_minimum55to48_Mcompar_n0000_inst_cy_2 : STD_LOGIC;
278 
  signal Inst_minimum55to48_Mcompar_n0000_inst_lut2_2 : STD_LOGIC;
279 
  signal Inst_minimum55to48_Mcompar_n0000_inst_cy_1 : STD_LOGIC;
280 
  signal Inst_minimum55to48_Mcompar_n0000_inst_lut2_1 : STD_LOGIC;
281 
  signal Inst_minimum63to56_Mcompar_n0000_inst_cy_0 : STD_LOGIC;
282 
  signal Inst_minimum63to56_Mcompar_n0000_inst_lut2_0 : STD_LOGIC;
283 
  signal Inst_minimum63to56_Mcompar_n0000_inst_lut2_7 : STD_LOGIC;
284 
  signal Inst_minimum63to56_Mcompar_n0000_inst_cy_6 : STD_LOGIC;
285 
  signal Inst_minimum63to56_Mcompar_n0000_inst_lut2_6 : STD_LOGIC;
286 
  signal Inst_minimum63to56_Mcompar_n0000_inst_cy_5 : STD_LOGIC;
287 
  signal Inst_minimum63to56_Mcompar_n0000_inst_lut2_5 : STD_LOGIC;
288 
  signal Inst_minimum63to56_Mcompar_n0000_inst_cy_4 : STD_LOGIC;
289 
  signal Inst_minimum63to56_Mcompar_n0000_inst_lut2_4 : STD_LOGIC;
290 
  signal Inst_minimum63to56_Mcompar_n0000_inst_cy_3 : STD_LOGIC;
291 
  signal Inst_minimum63to56_Mcompar_n0000_inst_lut2_3 : STD_LOGIC;
292 
  signal Inst_minimum63to56_Mcompar_n0000_inst_cy_2 : STD_LOGIC;
293 
  signal Inst_minimum63to56_Mcompar_n0000_inst_lut2_2 : STD_LOGIC;
294 
  signal Inst_minimum63to56_Mcompar_n0000_inst_cy_1 : STD_LOGIC;
295 
  signal Inst_minimum63to56_Mcompar_n0000_inst_lut2_1 : STD_LOGIC;
296 
  signal C_0_OBUF_GTS_TRI : STD_LOGIC;
297 
  signal GTS : STD_LOGIC;
298 
  signal C_63_OBUF_GTS_TRI : STD_LOGIC;
299 
  signal C_62_OBUF_GTS_TRI : STD_LOGIC;
300 
  signal C_61_OBUF_GTS_TRI : STD_LOGIC;
301 
  signal C_60_OBUF_GTS_TRI : STD_LOGIC;
302 
  signal C_59_OBUF_GTS_TRI : STD_LOGIC;
303 
  signal C_58_OBUF_GTS_TRI : STD_LOGIC;
304 
  signal C_57_OBUF_GTS_TRI : STD_LOGIC;
305 
  signal C_56_OBUF_GTS_TRI : STD_LOGIC;
306 
  signal C_55_OBUF_GTS_TRI : STD_LOGIC;
307 
  signal C_54_OBUF_GTS_TRI : STD_LOGIC;
308 
  signal C_53_OBUF_GTS_TRI : STD_LOGIC;
309 
  signal C_52_OBUF_GTS_TRI : STD_LOGIC;
310 
  signal C_51_OBUF_GTS_TRI : STD_LOGIC;
311 
  signal C_50_OBUF_GTS_TRI : STD_LOGIC;
312 
  signal C_49_OBUF_GTS_TRI : STD_LOGIC;
313 
  signal C_48_OBUF_GTS_TRI : STD_LOGIC;
314 
  signal C_47_OBUF_GTS_TRI : STD_LOGIC;
315 
  signal C_46_OBUF_GTS_TRI : STD_LOGIC;
316 
  signal C_45_OBUF_GTS_TRI : STD_LOGIC;
317 
  signal C_44_OBUF_GTS_TRI : STD_LOGIC;
318 
  signal C_43_OBUF_GTS_TRI : STD_LOGIC;
319 
  signal C_42_OBUF_GTS_TRI : STD_LOGIC;
320 
  signal C_41_OBUF_GTS_TRI : STD_LOGIC;
321 
  signal C_40_OBUF_GTS_TRI : STD_LOGIC;
322 
  signal C_39_OBUF_GTS_TRI : STD_LOGIC;
323 
  signal C_38_OBUF_GTS_TRI : STD_LOGIC;
324 
  signal C_37_OBUF_GTS_TRI : STD_LOGIC;
325 
  signal C_36_OBUF_GTS_TRI : STD_LOGIC;
326 
  signal C_35_OBUF_GTS_TRI : STD_LOGIC;
327 
  signal C_34_OBUF_GTS_TRI : STD_LOGIC;
328 
  signal C_33_OBUF_GTS_TRI : STD_LOGIC;
329 
  signal C_32_OBUF_GTS_TRI : STD_LOGIC;
330 
  signal C_31_OBUF_GTS_TRI : STD_LOGIC;
331 
  signal C_30_OBUF_GTS_TRI : STD_LOGIC;
332 
  signal C_29_OBUF_GTS_TRI : STD_LOGIC;
333 
  signal C_28_OBUF_GTS_TRI : STD_LOGIC;
334 
  signal C_27_OBUF_GTS_TRI : STD_LOGIC;
335 
  signal C_26_OBUF_GTS_TRI : STD_LOGIC;
336 
  signal C_25_OBUF_GTS_TRI : STD_LOGIC;
337 
  signal C_24_OBUF_GTS_TRI : STD_LOGIC;
338 
  signal C_23_OBUF_GTS_TRI : STD_LOGIC;
339 
  signal C_22_OBUF_GTS_TRI : STD_LOGIC;
340 
  signal C_21_OBUF_GTS_TRI : STD_LOGIC;
341 
  signal C_20_OBUF_GTS_TRI : STD_LOGIC;
342 
  signal C_19_OBUF_GTS_TRI : STD_LOGIC;
343 
  signal C_18_OBUF_GTS_TRI : STD_LOGIC;
344 
  signal C_17_OBUF_GTS_TRI : STD_LOGIC;
345 
  signal C_16_OBUF_GTS_TRI : STD_LOGIC;
346 
  signal C_15_OBUF_GTS_TRI : STD_LOGIC;
347 
  signal C_14_OBUF_GTS_TRI : STD_LOGIC;
348 
  signal C_13_OBUF_GTS_TRI : STD_LOGIC;
349 
  signal C_12_OBUF_GTS_TRI : STD_LOGIC;
350 
  signal C_11_OBUF_GTS_TRI : STD_LOGIC;
351 
  signal C_10_OBUF_GTS_TRI : STD_LOGIC;
352 
  signal C_9_OBUF_GTS_TRI : STD_LOGIC;
353 
  signal C_8_OBUF_GTS_TRI : STD_LOGIC;
354 
  signal C_7_OBUF_GTS_TRI : STD_LOGIC;
355 
  signal C_6_OBUF_GTS_TRI : STD_LOGIC;
356 
  signal C_5_OBUF_GTS_TRI : STD_LOGIC;
357 
  signal C_4_OBUF_GTS_TRI : STD_LOGIC;
358 
  signal C_3_OBUF_GTS_TRI : STD_LOGIC;
359 
  signal C_2_OBUF_GTS_TRI : STD_LOGIC;
360 
  signal C_1_OBUF_GTS_TRI : STD_LOGIC;
361 
  signal NlwInverterSignal_C_0_OBUF_GTS_TRI_CTL : STD_LOGIC;
362 
  signal NlwInverterSignal_C_63_OBUF_GTS_TRI_CTL : STD_LOGIC;
363 
  signal NlwInverterSignal_C_62_OBUF_GTS_TRI_CTL : STD_LOGIC;
364 
  signal NlwInverterSignal_C_61_OBUF_GTS_TRI_CTL : STD_LOGIC;
365 
  signal NlwInverterSignal_C_60_OBUF_GTS_TRI_CTL : STD_LOGIC;
366 
  signal NlwInverterSignal_C_59_OBUF_GTS_TRI_CTL : STD_LOGIC;
367 
  signal NlwInverterSignal_C_58_OBUF_GTS_TRI_CTL : STD_LOGIC;
368 
  signal NlwInverterSignal_C_57_OBUF_GTS_TRI_CTL : STD_LOGIC;
369 
  signal NlwInverterSignal_C_56_OBUF_GTS_TRI_CTL : STD_LOGIC;
370 
  signal NlwInverterSignal_C_55_OBUF_GTS_TRI_CTL : STD_LOGIC;
371 
  signal NlwInverterSignal_C_54_OBUF_GTS_TRI_CTL : STD_LOGIC;
372 
  signal NlwInverterSignal_C_53_OBUF_GTS_TRI_CTL : STD_LOGIC;
373 
  signal NlwInverterSignal_C_52_OBUF_GTS_TRI_CTL : STD_LOGIC;
374 
  signal NlwInverterSignal_C_51_OBUF_GTS_TRI_CTL : STD_LOGIC;
375 
  signal NlwInverterSignal_C_50_OBUF_GTS_TRI_CTL : STD_LOGIC;
376 
  signal NlwInverterSignal_C_49_OBUF_GTS_TRI_CTL : STD_LOGIC;
377 
  signal NlwInverterSignal_C_48_OBUF_GTS_TRI_CTL : STD_LOGIC;
378 
  signal NlwInverterSignal_C_47_OBUF_GTS_TRI_CTL : STD_LOGIC;
379 
  signal NlwInverterSignal_C_46_OBUF_GTS_TRI_CTL : STD_LOGIC;
380 
  signal NlwInverterSignal_C_45_OBUF_GTS_TRI_CTL : STD_LOGIC;
381 
  signal NlwInverterSignal_C_44_OBUF_GTS_TRI_CTL : STD_LOGIC;
382 
  signal NlwInverterSignal_C_43_OBUF_GTS_TRI_CTL : STD_LOGIC;
383 
  signal NlwInverterSignal_C_42_OBUF_GTS_TRI_CTL : STD_LOGIC;
384 
  signal NlwInverterSignal_C_41_OBUF_GTS_TRI_CTL : STD_LOGIC;
385 
  signal NlwInverterSignal_C_40_OBUF_GTS_TRI_CTL : STD_LOGIC;
386 
  signal NlwInverterSignal_C_39_OBUF_GTS_TRI_CTL : STD_LOGIC;
387 
  signal NlwInverterSignal_C_38_OBUF_GTS_TRI_CTL : STD_LOGIC;
388 
  signal NlwInverterSignal_C_37_OBUF_GTS_TRI_CTL : STD_LOGIC;
389 
  signal NlwInverterSignal_C_36_OBUF_GTS_TRI_CTL : STD_LOGIC;
390 
  signal NlwInverterSignal_C_35_OBUF_GTS_TRI_CTL : STD_LOGIC;
391 
  signal NlwInverterSignal_C_34_OBUF_GTS_TRI_CTL : STD_LOGIC;
392 
  signal NlwInverterSignal_C_33_OBUF_GTS_TRI_CTL : STD_LOGIC;
393 
  signal NlwInverterSignal_C_32_OBUF_GTS_TRI_CTL : STD_LOGIC;
394 
  signal NlwInverterSignal_C_31_OBUF_GTS_TRI_CTL : STD_LOGIC;
395 
  signal NlwInverterSignal_C_30_OBUF_GTS_TRI_CTL : STD_LOGIC;
396 
  signal NlwInverterSignal_C_29_OBUF_GTS_TRI_CTL : STD_LOGIC;
397 
  signal NlwInverterSignal_C_28_OBUF_GTS_TRI_CTL : STD_LOGIC;
398 
  signal NlwInverterSignal_C_27_OBUF_GTS_TRI_CTL : STD_LOGIC;
399 
  signal NlwInverterSignal_C_26_OBUF_GTS_TRI_CTL : STD_LOGIC;
400 
  signal NlwInverterSignal_C_25_OBUF_GTS_TRI_CTL : STD_LOGIC;
401 
  signal NlwInverterSignal_C_24_OBUF_GTS_TRI_CTL : STD_LOGIC;
402 
  signal NlwInverterSignal_C_23_OBUF_GTS_TRI_CTL : STD_LOGIC;
403 
  signal NlwInverterSignal_C_22_OBUF_GTS_TRI_CTL : STD_LOGIC;
404 
  signal NlwInverterSignal_C_21_OBUF_GTS_TRI_CTL : STD_LOGIC;
405 
  signal NlwInverterSignal_C_20_OBUF_GTS_TRI_CTL : STD_LOGIC;
406 
  signal NlwInverterSignal_C_19_OBUF_GTS_TRI_CTL : STD_LOGIC;
407 
  signal NlwInverterSignal_C_18_OBUF_GTS_TRI_CTL : STD_LOGIC;
408 
  signal NlwInverterSignal_C_17_OBUF_GTS_TRI_CTL : STD_LOGIC;
409 
  signal NlwInverterSignal_C_16_OBUF_GTS_TRI_CTL : STD_LOGIC;
410 
  signal NlwInverterSignal_C_15_OBUF_GTS_TRI_CTL : STD_LOGIC;
411 
  signal NlwInverterSignal_C_14_OBUF_GTS_TRI_CTL : STD_LOGIC;
412 
  signal NlwInverterSignal_C_13_OBUF_GTS_TRI_CTL : STD_LOGIC;
413 
  signal NlwInverterSignal_C_12_OBUF_GTS_TRI_CTL : STD_LOGIC;
414 
  signal NlwInverterSignal_C_11_OBUF_GTS_TRI_CTL : STD_LOGIC;
415 
  signal NlwInverterSignal_C_10_OBUF_GTS_TRI_CTL : STD_LOGIC;
416 
  signal NlwInverterSignal_C_9_OBUF_GTS_TRI_CTL : STD_LOGIC;
417 
  signal NlwInverterSignal_C_8_OBUF_GTS_TRI_CTL : STD_LOGIC;
418 
  signal NlwInverterSignal_C_7_OBUF_GTS_TRI_CTL : STD_LOGIC;
419 
  signal NlwInverterSignal_C_6_OBUF_GTS_TRI_CTL : STD_LOGIC;
420 
  signal NlwInverterSignal_C_5_OBUF_GTS_TRI_CTL : STD_LOGIC;
421 
  signal NlwInverterSignal_C_4_OBUF_GTS_TRI_CTL : STD_LOGIC;
422 
  signal NlwInverterSignal_C_3_OBUF_GTS_TRI_CTL : STD_LOGIC;
423 
  signal NlwInverterSignal_C_2_OBUF_GTS_TRI_CTL : STD_LOGIC;
424 
  signal NlwInverterSignal_C_1_OBUF_GTS_TRI_CTL : STD_LOGIC;
425 
begin
426 
  Inst_minimum63to56_Mmux_C_Result_7_1 : X_LUT3
427 
    generic map(
428 
      INIT => X"E4"
429 
    )
430 
    port map (
431 
      ADR0 => Inst_minimum63to56_n0000,
432 
      ADR1 => B_63_IBUF,
433 
      ADR2 => A_7_IBUF,
434 
      O => C_63_OBUF
435 
    );
436 
  Inst_minimum55to48_Mmux_C_Result_7_1 : X_LUT3
437 
    generic map(
438 
      INIT => X"E4"
439 
    )
440 
    port map (
441 
      ADR0 => Inst_minimum55to48_n0000,
442 
      ADR1 => B_55_IBUF,
443 
      ADR2 => A_7_IBUF,
444 
      O => C_55_OBUF
445 
    );
446 
  Inst_minimum7to0_Mmux_C_Result_7_1 : X_LUT3
447 
    generic map(
448 
      INIT => X"E4"
449 
    )
450 
    port map (
451 
      ADR0 => Inst_minimum7to0_n0000,
452 
      ADR1 => B_7_IBUF,
453 
      ADR2 => A_7_IBUF,
454 
      O => C_7_OBUF
455 
    );
456 
  Inst_minimum15to8_Mmux_C_Result_7_1 : X_LUT3
457 
    generic map(
458 
      INIT => X"E4"
459 
    )
460 
    port map (
461 
      ADR0 => Inst_minimum15to8_n0000,
462 
      ADR1 => B_15_IBUF,
463 
      ADR2 => A_7_IBUF,
464 
      O => C_15_OBUF
465 
    );
466 
  Inst_minimum23to16_Mmux_C_Result_7_1 : X_LUT3
467 
    generic map(
468 
      INIT => X"E4"
469 
    )
470 
    port map (
471 
      ADR0 => Inst_minimum23to16_n0000,
472 
      ADR1 => B_23_IBUF,
473 
      ADR2 => A_7_IBUF,
474 
      O => C_23_OBUF
475 
    );
476 
  Inst_minimum31to24_Mmux_C_Result_7_1 : X_LUT3
477 
    generic map(
478 
      INIT => X"E4"
479 
    )
480 
    port map (
481 
      ADR0 => Inst_minimum31to24_n0000,
482 
      ADR1 => B_31_IBUF,
483 
      ADR2 => A_7_IBUF,
484 
      O => C_31_OBUF
485 
    );
486 
  Inst_minimum39to32_Mmux_C_Result_7_1 : X_LUT3
487 
    generic map(
488 
      INIT => X"E4"
489 
    )
490 
    port map (
491 
      ADR0 => Inst_minimum39to32_n0000,
492 
      ADR1 => B_39_IBUF,
493 
      ADR2 => A_7_IBUF,
494 
      O => C_39_OBUF
495 
    );
496 
  Inst_minimum47to40_Mmux_C_Result_7_1 : X_LUT3
497 
    generic map(
498 
      INIT => X"E4"
499 
    )
500 
    port map (
501 
      ADR0 => Inst_minimum47to40_n0000,
502 
      ADR1 => B_47_IBUF,
503 
      ADR2 => A_7_IBUF,
504 
      O => C_47_OBUF
505 
    );
506 
  Inst_minimum63to56_Mcompar_n0000_inst_cy_6_0 : X_MUX2
507 
    port map (
508 
      IB => Inst_minimum63to56_Mcompar_n0000_inst_cy_5,
509 
      IA => B_62_IBUF,
510 
      SEL => Inst_minimum63to56_Mcompar_n0000_inst_lut2_6,
511 
      O => Inst_minimum63to56_Mcompar_n0000_inst_cy_6
512 
    );
513 
  Inst_minimum55to48_Mcompar_n0000_inst_cy_6_1 : X_MUX2
514 
    port map (
515 
      IB => Inst_minimum55to48_Mcompar_n0000_inst_cy_5,
516 
      IA => B_54_IBUF,
517 
      SEL => Inst_minimum55to48_Mcompar_n0000_inst_lut2_6,
518 
      O => Inst_minimum55to48_Mcompar_n0000_inst_cy_6
519 
    );
520 
  Inst_minimum47to40_Mcompar_n0000_inst_cy_6_2 : X_MUX2
521 
    port map (
522 
      IB => Inst_minimum47to40_Mcompar_n0000_inst_cy_5,
523 
      IA => B_46_IBUF,
524 
      SEL => Inst_minimum47to40_Mcompar_n0000_inst_lut2_6,
525 
      O => Inst_minimum47to40_Mcompar_n0000_inst_cy_6
526 
    );
527 
  Inst_minimum39to32_Mcompar_n0000_inst_cy_6_3 : X_MUX2
528 
    port map (
529 
      IB => Inst_minimum39to32_Mcompar_n0000_inst_cy_5,
530 
      IA => B_38_IBUF,
531 
      SEL => Inst_minimum39to32_Mcompar_n0000_inst_lut2_6,
532 
      O => Inst_minimum39to32_Mcompar_n0000_inst_cy_6
533 
    );
534 
  Inst_minimum31to24_Mcompar_n0000_inst_cy_6_4 : X_MUX2
535 
    port map (
536 
      IB => Inst_minimum31to24_Mcompar_n0000_inst_cy_5,
537 
      IA => B_30_IBUF,
538 
      SEL => Inst_minimum31to24_Mcompar_n0000_inst_lut2_6,
539 
      O => Inst_minimum31to24_Mcompar_n0000_inst_cy_6
540 
    );
541 
  Inst_minimum23to16_Mcompar_n0000_inst_cy_6_5 : X_MUX2
542 
    port map (
543 
      IB => Inst_minimum23to16_Mcompar_n0000_inst_cy_5,
544 
      IA => B_22_IBUF,
545 
      SEL => Inst_minimum23to16_Mcompar_n0000_inst_lut2_6,
546 
      O => Inst_minimum23to16_Mcompar_n0000_inst_cy_6
547 
    );
548 
  Inst_minimum15to8_Mcompar_n0000_inst_cy_6_6 : X_MUX2
549 
    port map (
550 
      IB => Inst_minimum15to8_Mcompar_n0000_inst_cy_5,
551 
      IA => B_14_IBUF,
552 
      SEL => Inst_minimum15to8_Mcompar_n0000_inst_lut2_6,
553 
      O => Inst_minimum15to8_Mcompar_n0000_inst_cy_6
554 
    );
555 
  Inst_minimum7to0_Mcompar_n0000_inst_cy_7 : X_MUX2
556 
    port map (
557 
      IB => Inst_minimum7to0_Mcompar_n0000_inst_cy_6,
558 
      IA => B_7_IBUF,
559 
      SEL => Inst_minimum7to0_Mcompar_n0000_inst_lut2_7,
560 
      O => Inst_minimum7to0_n0000
561 
    );
562 
  XST_GND : X_ZERO
563 
    port map (
564 
      O => N183
565 
    );
566 
  C_0_OBUF_7 : X_BUF
567 
    port map (
568 
      I => C_0_OBUF,
569 
      O => C_0_OBUF_GTS_TRI
570 
    );
571 
  Inst_minimum7to0_Mcompar_n0000_inst_lut2_01 : X_LUT2
572 
    generic map(
573 
      INIT => X"9"
574 
    )
575 
    port map (
576 
      ADR0 => B_0_IBUF,
577 
      ADR1 => A_0_IBUF,
578 
      O => Inst_minimum7to0_Mcompar_n0000_inst_lut2_0
579 
    );
580 
  Inst_minimum7to0_Mcompar_n0000_inst_cy_0_8 : X_MUX2
581 
    port map (
582 
      IB => N183,
583 
      IA => B_0_IBUF,
584 
      SEL => Inst_minimum7to0_Mcompar_n0000_inst_lut2_0,
585 
      O => Inst_minimum7to0_Mcompar_n0000_inst_cy_0
586 
    );
587 
  Inst_minimum7to0_Mcompar_n0000_inst_lut2_11 : X_LUT2
588 
    generic map(
589 
      INIT => X"9"
590 
    )
591 
    port map (
592 
      ADR0 => B_1_IBUF,
593 
      ADR1 => A_1_IBUF,
594 
      O => Inst_minimum7to0_Mcompar_n0000_inst_lut2_1
595 
    );
596 
  Inst_minimum7to0_Mcompar_n0000_inst_cy_1_9 : X_MUX2
597 
    port map (
598 
      IB => Inst_minimum7to0_Mcompar_n0000_inst_cy_0,
599 
      IA => B_1_IBUF,
600 
      SEL => Inst_minimum7to0_Mcompar_n0000_inst_lut2_1,
601 
      O => Inst_minimum7to0_Mcompar_n0000_inst_cy_1
602 
    );
603 
  Inst_minimum7to0_Mcompar_n0000_inst_lut2_21 : X_LUT2
604 
    generic map(
605 
      INIT => X"9"
606 
    )
607 
    port map (
608 
      ADR0 => B_2_IBUF,
609 
      ADR1 => A_2_IBUF,
610 
      O => Inst_minimum7to0_Mcompar_n0000_inst_lut2_2
611 
    );
612 
  Inst_minimum7to0_Mcompar_n0000_inst_cy_2_10 : X_MUX2
613 
    port map (
614 
      IB => Inst_minimum7to0_Mcompar_n0000_inst_cy_1,
615 
      IA => B_2_IBUF,
616 
      SEL => Inst_minimum7to0_Mcompar_n0000_inst_lut2_2,
617 
      O => Inst_minimum7to0_Mcompar_n0000_inst_cy_2
618 
    );
619 
  Inst_minimum7to0_Mcompar_n0000_inst_lut2_31 : X_LUT2
620 
    generic map(
621 
      INIT => X"9"
622 
    )
623 
    port map (
624 
      ADR0 => B_3_IBUF,
625 
      ADR1 => A_3_IBUF,
626 
      O => Inst_minimum7to0_Mcompar_n0000_inst_lut2_3
627 
    );
628 
  Inst_minimum7to0_Mcompar_n0000_inst_cy_3_11 : X_MUX2
629 
    port map (
630 
      IB => Inst_minimum7to0_Mcompar_n0000_inst_cy_2,
631 
      IA => B_3_IBUF,
632 
      SEL => Inst_minimum7to0_Mcompar_n0000_inst_lut2_3,
633 
      O => Inst_minimum7to0_Mcompar_n0000_inst_cy_3
634 
    );
635 
  Inst_minimum7to0_Mcompar_n0000_inst_lut2_41 : X_LUT2
636 
    generic map(
637 
      INIT => X"9"
638 
    )
639 
    port map (
640 
      ADR0 => B_4_IBUF,
641 
      ADR1 => A_4_IBUF,
642 
      O => Inst_minimum7to0_Mcompar_n0000_inst_lut2_4
643 
    );
644 
  Inst_minimum7to0_Mcompar_n0000_inst_cy_4_12 : X_MUX2
645 
    port map (
646 
      IB => Inst_minimum7to0_Mcompar_n0000_inst_cy_3,
647 
      IA => B_4_IBUF,
648 
      SEL => Inst_minimum7to0_Mcompar_n0000_inst_lut2_4,
649 
      O => Inst_minimum7to0_Mcompar_n0000_inst_cy_4
650 
    );
651 
  Inst_minimum7to0_Mcompar_n0000_inst_lut2_51 : X_LUT2
652 
    generic map(
653 
      INIT => X"9"
654 
    )
655 
    port map (
656 
      ADR0 => B_5_IBUF,
657 
      ADR1 => A_5_IBUF,
658 
      O => Inst_minimum7to0_Mcompar_n0000_inst_lut2_5
659 
    );
660 
  Inst_minimum7to0_Mcompar_n0000_inst_cy_5_13 : X_MUX2
661 
    port map (
662 
      IB => Inst_minimum7to0_Mcompar_n0000_inst_cy_4,
663 
      IA => B_5_IBUF,
664 
      SEL => Inst_minimum7to0_Mcompar_n0000_inst_lut2_5,
665 
      O => Inst_minimum7to0_Mcompar_n0000_inst_cy_5
666 
    );
667 
  Inst_minimum7to0_Mcompar_n0000_inst_lut2_61 : X_LUT2
668 
    generic map(
669 
      INIT => X"9"
670 
    )
671 
    port map (
672 
      ADR0 => B_6_IBUF,
673 
      ADR1 => A_6_IBUF,
674 
      O => Inst_minimum7to0_Mcompar_n0000_inst_lut2_6
675 
    );
676 
  Inst_minimum7to0_Mcompar_n0000_inst_cy_6_14 : X_MUX2
677 
    port map (
678 
      IB => Inst_minimum7to0_Mcompar_n0000_inst_cy_5,
679 
      IA => B_6_IBUF,
680 
      SEL => Inst_minimum7to0_Mcompar_n0000_inst_lut2_6,
681 
      O => Inst_minimum7to0_Mcompar_n0000_inst_cy_6
682 
    );
683 
  Inst_minimum7to0_Mcompar_n0000_inst_lut2_71 : X_LUT2
684 
    generic map(
685 
      INIT => X"9"
686 
    )
687 
    port map (
688 
      ADR0 => B_7_IBUF,
689 
      ADR1 => A_7_IBUF,
690 
      O => Inst_minimum7to0_Mcompar_n0000_inst_lut2_7
691 
    );
692 
  Inst_minimum15to8_Mcompar_n0000_inst_lut2_71 : X_LUT2
693 
    generic map(
694 
      INIT => X"9"
695 
    )
696 
    port map (
697 
      ADR0 => B_15_IBUF,
698 
      ADR1 => A_7_IBUF,
699 
      O => Inst_minimum15to8_Mcompar_n0000_inst_lut2_7
700 
    );
701 
  Inst_minimum15to8_Mcompar_n0000_inst_cy_7 : X_MUX2
702 
    port map (
703 
      IB => Inst_minimum15to8_Mcompar_n0000_inst_cy_6,
704 
      IA => B_15_IBUF,
705 
      SEL => Inst_minimum15to8_Mcompar_n0000_inst_lut2_7,
706 
      O => Inst_minimum15to8_n0000
707 
    );
708 
  Inst_minimum15to8_Mcompar_n0000_inst_lut2_01 : X_LUT2
709 
    generic map(
710 
      INIT => X"9"
711 
    )
712 
    port map (
713 
      ADR0 => B_8_IBUF,
714 
      ADR1 => A_0_IBUF,
715 
      O => Inst_minimum15to8_Mcompar_n0000_inst_lut2_0
716 
    );
717 
  Inst_minimum15to8_Mcompar_n0000_inst_cy_0_15 : X_MUX2
718 
    port map (
719 
      IB => N183,
720 
      IA => B_8_IBUF,
721 
      SEL => Inst_minimum15to8_Mcompar_n0000_inst_lut2_0,
722 
      O => Inst_minimum15to8_Mcompar_n0000_inst_cy_0
723 
    );
724 
  Inst_minimum15to8_Mcompar_n0000_inst_lut2_11 : X_LUT2
725 
    generic map(
726 
      INIT => X"9"
727 
    )
728 
    port map (
729 
      ADR0 => B_9_IBUF,
730 
      ADR1 => A_1_IBUF,
731 
      O => Inst_minimum15to8_Mcompar_n0000_inst_lut2_1
732 
    );
733 
  Inst_minimum15to8_Mcompar_n0000_inst_cy_1_16 : X_MUX2
734 
    port map (
735 
      IB => Inst_minimum15to8_Mcompar_n0000_inst_cy_0,
736 
      IA => B_9_IBUF,
737 
      SEL => Inst_minimum15to8_Mcompar_n0000_inst_lut2_1,
738 
      O => Inst_minimum15to8_Mcompar_n0000_inst_cy_1
739 
    );
740 
  Inst_minimum15to8_Mcompar_n0000_inst_lut2_21 : X_LUT2
741 
    generic map(
742 
      INIT => X"9"
743 
    )
744 
    port map (
745 
      ADR0 => B_10_IBUF,
746 
      ADR1 => A_2_IBUF,
747 
      O => Inst_minimum15to8_Mcompar_n0000_inst_lut2_2
748 
    );
749 
  Inst_minimum15to8_Mcompar_n0000_inst_cy_2_17 : X_MUX2
750 
    port map (
751 
      IB => Inst_minimum15to8_Mcompar_n0000_inst_cy_1,
752 
      IA => B_10_IBUF,
753 
      SEL => Inst_minimum15to8_Mcompar_n0000_inst_lut2_2,
754 
      O => Inst_minimum15to8_Mcompar_n0000_inst_cy_2
755 
    );
756 
  Inst_minimum15to8_Mcompar_n0000_inst_lut2_31 : X_LUT2
757 
    generic map(
758 
      INIT => X"9"
759 
    )
760 
    port map (
761 
      ADR0 => B_11_IBUF,
762 
      ADR1 => A_3_IBUF,
763 
      O => Inst_minimum15to8_Mcompar_n0000_inst_lut2_3
764 
    );
765 
  Inst_minimum15to8_Mcompar_n0000_inst_cy_3_18 : X_MUX2
766 
    port map (
767 
      IB => Inst_minimum15to8_Mcompar_n0000_inst_cy_2,
768 
      IA => B_11_IBUF,
769 
      SEL => Inst_minimum15to8_Mcompar_n0000_inst_lut2_3,
770 
      O => Inst_minimum15to8_Mcompar_n0000_inst_cy_3
771 
    );
772 
  Inst_minimum15to8_Mcompar_n0000_inst_lut2_41 : X_LUT2
773 
    generic map(
774 
      INIT => X"9"
775 
    )
776 
    port map (
777 
      ADR0 => B_12_IBUF,
778 
      ADR1 => A_4_IBUF,
779 
      O => Inst_minimum15to8_Mcompar_n0000_inst_lut2_4
780 
    );
781 
  Inst_minimum15to8_Mcompar_n0000_inst_cy_4_19 : X_MUX2
782 
    port map (
783 
      IB => Inst_minimum15to8_Mcompar_n0000_inst_cy_3,
784 
      IA => B_12_IBUF,
785 
      SEL => Inst_minimum15to8_Mcompar_n0000_inst_lut2_4,
786 
      O => Inst_minimum15to8_Mcompar_n0000_inst_cy_4
787 
    );
788 
  Inst_minimum15to8_Mcompar_n0000_inst_lut2_51 : X_LUT2
789 
    generic map(
790 
      INIT => X"9"
791 
    )
792 
    port map (
793 
      ADR0 => B_13_IBUF,
794 
      ADR1 => A_5_IBUF,
795 
      O => Inst_minimum15to8_Mcompar_n0000_inst_lut2_5
796 
    );
797 
  Inst_minimum15to8_Mcompar_n0000_inst_cy_5_20 : X_MUX2
798 
    port map (
799 
      IB => Inst_minimum15to8_Mcompar_n0000_inst_cy_4,
800 
      IA => B_13_IBUF,
801 
      SEL => Inst_minimum15to8_Mcompar_n0000_inst_lut2_5,
802 
      O => Inst_minimum15to8_Mcompar_n0000_inst_cy_5
803 
    );
804 
  Inst_minimum15to8_Mcompar_n0000_inst_lut2_61 : X_LUT2
805 
    generic map(
806 
      INIT => X"9"
807 
    )
808 
    port map (
809 
      ADR0 => B_14_IBUF,
810 
      ADR1 => A_6_IBUF,
811 
      O => Inst_minimum15to8_Mcompar_n0000_inst_lut2_6
812 
    );
813 
  Inst_minimum23to16_Mcompar_n0000_inst_lut2_71 : X_LUT2
814 
    generic map(
815 
      INIT => X"9"
816 
    )
817 
    port map (
818 
      ADR0 => B_23_IBUF,
819 
      ADR1 => A_7_IBUF,
820 
      O => Inst_minimum23to16_Mcompar_n0000_inst_lut2_7
821 
    );
822 
  Inst_minimum23to16_Mcompar_n0000_inst_cy_7 : X_MUX2
823 
    port map (
824 
      IB => Inst_minimum23to16_Mcompar_n0000_inst_cy_6,
825 
      IA => B_23_IBUF,
826 
      SEL => Inst_minimum23to16_Mcompar_n0000_inst_lut2_7,
827 
      O => Inst_minimum23to16_n0000
828 
    );
829 
  Inst_minimum23to16_Mcompar_n0000_inst_lut2_01 : X_LUT2
830 
    generic map(
831 
      INIT => X"9"
832 
    )
833 
    port map (
834 
      ADR0 => B_16_IBUF,
835 
      ADR1 => A_0_IBUF,
836 
      O => Inst_minimum23to16_Mcompar_n0000_inst_lut2_0
837 
    );
838 
  Inst_minimum23to16_Mcompar_n0000_inst_cy_0_21 : X_MUX2
839 
    port map (
840 
      IB => N183,
841 
      IA => B_16_IBUF,
842 
      SEL => Inst_minimum23to16_Mcompar_n0000_inst_lut2_0,
843 
      O => Inst_minimum23to16_Mcompar_n0000_inst_cy_0
844 
    );
845 
  Inst_minimum23to16_Mcompar_n0000_inst_lut2_11 : X_LUT2
846 
    generic map(
847 
      INIT => X"9"
848 
    )
849 
    port map (
850 
      ADR0 => B_17_IBUF,
851 
      ADR1 => A_1_IBUF,
852 
      O => Inst_minimum23to16_Mcompar_n0000_inst_lut2_1
853 
    );
854 
  Inst_minimum23to16_Mcompar_n0000_inst_cy_1_22 : X_MUX2
855 
    port map (
856 
      IB => Inst_minimum23to16_Mcompar_n0000_inst_cy_0,
857 
      IA => B_17_IBUF,
858 
      SEL => Inst_minimum23to16_Mcompar_n0000_inst_lut2_1,
859 
      O => Inst_minimum23to16_Mcompar_n0000_inst_cy_1
860 
    );
861 
  Inst_minimum23to16_Mcompar_n0000_inst_lut2_21 : X_LUT2
862 
    generic map(
863 
      INIT => X"9"
864 
    )
865 
    port map (
866 
      ADR0 => B_18_IBUF,
867 
      ADR1 => A_2_IBUF,
868 
      O => Inst_minimum23to16_Mcompar_n0000_inst_lut2_2
869 
    );
870 
  Inst_minimum23to16_Mcompar_n0000_inst_cy_2_23 : X_MUX2
871 
    port map (
872 
      IB => Inst_minimum23to16_Mcompar_n0000_inst_cy_1,
873 
      IA => B_18_IBUF,
874 
      SEL => Inst_minimum23to16_Mcompar_n0000_inst_lut2_2,
875 
      O => Inst_minimum23to16_Mcompar_n0000_inst_cy_2
876 
    );
877 
  Inst_minimum23to16_Mcompar_n0000_inst_lut2_31 : X_LUT2
878 
    generic map(
879 
      INIT => X"9"
880 
    )
881 
    port map (
882 
      ADR0 => B_19_IBUF,
883 
      ADR1 => A_3_IBUF,
884 
      O => Inst_minimum23to16_Mcompar_n0000_inst_lut2_3
885 
    );
886 
  Inst_minimum23to16_Mcompar_n0000_inst_cy_3_24 : X_MUX2
887 
    port map (
888 
      IB => Inst_minimum23to16_Mcompar_n0000_inst_cy_2,
889 
      IA => B_19_IBUF,
890 
      SEL => Inst_minimum23to16_Mcompar_n0000_inst_lut2_3,
891 
      O => Inst_minimum23to16_Mcompar_n0000_inst_cy_3
892 
    );
893 
  Inst_minimum23to16_Mcompar_n0000_inst_lut2_41 : X_LUT2
894 
    generic map(
895 
      INIT => X"9"
896 
    )
897 
    port map (
898 
      ADR0 => B_20_IBUF,
899 
      ADR1 => A_4_IBUF,
900 
      O => Inst_minimum23to16_Mcompar_n0000_inst_lut2_4
901 
    );
902 
  Inst_minimum23to16_Mcompar_n0000_inst_cy_4_25 : X_MUX2
903 
    port map (
904 
      IB => Inst_minimum23to16_Mcompar_n0000_inst_cy_3,
905 
      IA => B_20_IBUF,
906 
      SEL => Inst_minimum23to16_Mcompar_n0000_inst_lut2_4,
907 
      O => Inst_minimum23to16_Mcompar_n0000_inst_cy_4
908 
    );
909 
  Inst_minimum23to16_Mcompar_n0000_inst_lut2_51 : X_LUT2
910 
    generic map(
911 
      INIT => X"9"
912 
    )
913 
    port map (
914 
      ADR0 => B_21_IBUF,
915 
      ADR1 => A_5_IBUF,
916 
      O => Inst_minimum23to16_Mcompar_n0000_inst_lut2_5
917 
    );
918 
  Inst_minimum23to16_Mcompar_n0000_inst_cy_5_26 : X_MUX2
919 
    port map (
920 
      IB => Inst_minimum23to16_Mcompar_n0000_inst_cy_4,
921 
      IA => B_21_IBUF,
922 
      SEL => Inst_minimum23to16_Mcompar_n0000_inst_lut2_5,
923 
      O => Inst_minimum23to16_Mcompar_n0000_inst_cy_5
924 
    );
925 
  Inst_minimum23to16_Mcompar_n0000_inst_lut2_61 : X_LUT2
926 
    generic map(
927 
      INIT => X"9"
928 
    )
929 
    port map (
930 
      ADR0 => B_22_IBUF,
931 
      ADR1 => A_6_IBUF,
932 
      O => Inst_minimum23to16_Mcompar_n0000_inst_lut2_6
933 
    );
934 
  Inst_minimum31to24_Mcompar_n0000_inst_lut2_71 : X_LUT2
935 
    generic map(
936 
      INIT => X"9"
937 
    )
938 
    port map (
939 
      ADR0 => B_31_IBUF,
940 
      ADR1 => A_7_IBUF,
941 
      O => Inst_minimum31to24_Mcompar_n0000_inst_lut2_7
942 
    );
943 
  Inst_minimum31to24_Mcompar_n0000_inst_cy_7 : X_MUX2
944 
    port map (
945 
      IB => Inst_minimum31to24_Mcompar_n0000_inst_cy_6,
946 
      IA => B_31_IBUF,
947 
      SEL => Inst_minimum31to24_Mcompar_n0000_inst_lut2_7,
948 
      O => Inst_minimum31to24_n0000
949 
    );
950 
  Inst_minimum31to24_Mcompar_n0000_inst_lut2_01 : X_LUT2
951 
    generic map(
952 
      INIT => X"9"
953 
    )
954 
    port map (
955 
      ADR0 => B_24_IBUF,
956 
      ADR1 => A_0_IBUF,
957 
      O => Inst_minimum31to24_Mcompar_n0000_inst_lut2_0
958 
    );
959 
  Inst_minimum31to24_Mcompar_n0000_inst_cy_0_27 : X_MUX2
960 
    port map (
961 
      IB => N183,
962 
      IA => B_24_IBUF,
963 
      SEL => Inst_minimum31to24_Mcompar_n0000_inst_lut2_0,
964 
      O => Inst_minimum31to24_Mcompar_n0000_inst_cy_0
965 
    );
966 
  Inst_minimum31to24_Mcompar_n0000_inst_lut2_11 : X_LUT2
967 
    generic map(
968 
      INIT => X"9"
969 
    )
970 
    port map (
971 
      ADR0 => B_25_IBUF,
972 
      ADR1 => A_1_IBUF,
973 
      O => Inst_minimum31to24_Mcompar_n0000_inst_lut2_1
974 
    );
975 
  Inst_minimum31to24_Mcompar_n0000_inst_cy_1_28 : X_MUX2
976 
    port map (
977 
      IB => Inst_minimum31to24_Mcompar_n0000_inst_cy_0,
978 
      IA => B_25_IBUF,
979 
      SEL => Inst_minimum31to24_Mcompar_n0000_inst_lut2_1,
980 
      O => Inst_minimum31to24_Mcompar_n0000_inst_cy_1
981 
    );
982 
  Inst_minimum31to24_Mcompar_n0000_inst_lut2_21 : X_LUT2
983 
    generic map(
984 
      INIT => X"9"
985 
    )
986 
    port map (
987 
      ADR0 => B_26_IBUF,
988 
      ADR1 => A_2_IBUF,
989 
      O => Inst_minimum31to24_Mcompar_n0000_inst_lut2_2
990 
    );
991 
  Inst_minimum31to24_Mcompar_n0000_inst_cy_2_29 : X_MUX2
992 
    port map (
993 
      IB => Inst_minimum31to24_Mcompar_n0000_inst_cy_1,
994 
      IA => B_26_IBUF,
995 
      SEL => Inst_minimum31to24_Mcompar_n0000_inst_lut2_2,
996 
      O => Inst_minimum31to24_Mcompar_n0000_inst_cy_2
997 
    );
998 
  Inst_minimum31to24_Mcompar_n0000_inst_lut2_31 : X_LUT2
999 
    generic map(
1000 
      INIT => X"9"
1001 
    )
1002 
    port map (
1003 
      ADR0 => B_27_IBUF,
1004 
      ADR1 => A_3_IBUF,
1005 
      O => Inst_minimum31to24_Mcompar_n0000_inst_lut2_3
1006 
    );
1007 
  Inst_minimum31to24_Mcompar_n0000_inst_cy_3_30 : X_MUX2
1008 
    port map (
1009 
      IB => Inst_minimum31to24_Mcompar_n0000_inst_cy_2,
1010 
      IA => B_27_IBUF,
1011 
      SEL => Inst_minimum31to24_Mcompar_n0000_inst_lut2_3,
1012 
      O => Inst_minimum31to24_Mcompar_n0000_inst_cy_3
1013 
    );
1014 
  Inst_minimum31to24_Mcompar_n0000_inst_lut2_41 : X_LUT2
1015 
    generic map(
1016 
      INIT => X"9"
1017 
    )
1018 
    port map (
1019 
      ADR0 => B_28_IBUF,
1020 
      ADR1 => A_4_IBUF,
1021 
      O => Inst_minimum31to24_Mcompar_n0000_inst_lut2_4
1022 
    );
1023 
  Inst_minimum31to24_Mcompar_n0000_inst_cy_4_31 : X_MUX2
1024 
    port map (
1025 
      IB => Inst_minimum31to24_Mcompar_n0000_inst_cy_3,
1026 
      IA => B_28_IBUF,
1027 
      SEL => Inst_minimum31to24_Mcompar_n0000_inst_lut2_4,
1028 
      O => Inst_minimum31to24_Mcompar_n0000_inst_cy_4
1029 
    );
1030 
  Inst_minimum31to24_Mcompar_n0000_inst_lut2_51 : X_LUT2
1031 
    generic map(
1032 
      INIT => X"9"
1033 
    )
1034 
    port map (
1035 
      ADR0 => B_29_IBUF,
1036 
      ADR1 => A_5_IBUF,
1037 
      O => Inst_minimum31to24_Mcompar_n0000_inst_lut2_5
1038 
    );
1039 
  Inst_minimum31to24_Mcompar_n0000_inst_cy_5_32 : X_MUX2
1040 
    port map (
1041 
      IB => Inst_minimum31to24_Mcompar_n0000_inst_cy_4,
1042 
      IA => B_29_IBUF,
1043 
      SEL => Inst_minimum31to24_Mcompar_n0000_inst_lut2_5,
1044 
      O => Inst_minimum31to24_Mcompar_n0000_inst_cy_5
1045 
    );
1046 
  Inst_minimum31to24_Mcompar_n0000_inst_lut2_61 : X_LUT2
1047 
    generic map(
1048 
      INIT => X"9"
1049 
    )
1050 
    port map (
1051 
      ADR0 => B_30_IBUF,
1052 
      ADR1 => A_6_IBUF,
1053 
      O => Inst_minimum31to24_Mcompar_n0000_inst_lut2_6
1054 
    );
1055 
  Inst_minimum39to32_Mcompar_n0000_inst_lut2_71 : X_LUT2
1056 
    generic map(
1057 
      INIT => X"9"
1058 
    )
1059 
    port map (
1060 
      ADR0 => B_39_IBUF,
1061 
      ADR1 => A_7_IBUF,
1062 
      O => Inst_minimum39to32_Mcompar_n0000_inst_lut2_7
1063 
    );
1064 
  Inst_minimum39to32_Mcompar_n0000_inst_cy_7 : X_MUX2
1065 
    port map (
1066 
      IB => Inst_minimum39to32_Mcompar_n0000_inst_cy_6,
1067 
      IA => B_39_IBUF,
1068 
      SEL => Inst_minimum39to32_Mcompar_n0000_inst_lut2_7,
1069 
      O => Inst_minimum39to32_n0000
1070 
    );
1071 
  Inst_minimum39to32_Mcompar_n0000_inst_lut2_01 : X_LUT2
1072 
    generic map(
1073 
      INIT => X"9"
1074 
    )
1075 
    port map (
1076 
      ADR0 => B_32_IBUF,
1077 
      ADR1 => A_0_IBUF,
1078 
      O => Inst_minimum39to32_Mcompar_n0000_inst_lut2_0
1079 
    );
1080 
  Inst_minimum39to32_Mcompar_n0000_inst_cy_0_33 : X_MUX2
1081 
    port map (
1082 
      IB => N183,
1083 
      IA => B_32_IBUF,
1084 
      SEL => Inst_minimum39to32_Mcompar_n0000_inst_lut2_0,
1085 
      O => Inst_minimum39to32_Mcompar_n0000_inst_cy_0
1086 
    );
1087 
  Inst_minimum39to32_Mcompar_n0000_inst_lut2_11 : X_LUT2
1088 
    generic map(
1089 
      INIT => X"9"
1090 
    )
1091 
    port map (
1092 
      ADR0 => B_33_IBUF,
1093 
      ADR1 => A_1_IBUF,
1094 
      O => Inst_minimum39to32_Mcompar_n0000_inst_lut2_1
1095 
    );
1096 
  Inst_minimum39to32_Mcompar_n0000_inst_cy_1_34 : X_MUX2
1097 
    port map (
1098 
      IB => Inst_minimum39to32_Mcompar_n0000_inst_cy_0,
1099 
      IA => B_33_IBUF,
1100 
      SEL => Inst_minimum39to32_Mcompar_n0000_inst_lut2_1,
1101 
      O => Inst_minimum39to32_Mcompar_n0000_inst_cy_1
1102 
    );
1103 
  Inst_minimum39to32_Mcompar_n0000_inst_lut2_21 : X_LUT2
1104 
    generic map(
1105 
      INIT => X"9"
1106 
    )
1107 
    port map (
1108 
      ADR0 => B_34_IBUF,
1109 
      ADR1 => A_2_IBUF,
1110 
      O => Inst_minimum39to32_Mcompar_n0000_inst_lut2_2
1111 
    );
1112 
  Inst_minimum39to32_Mcompar_n0000_inst_cy_2_35 : X_MUX2
1113 
    port map (
1114 
      IB => Inst_minimum39to32_Mcompar_n0000_inst_cy_1,
1115 
      IA => B_34_IBUF,
1116 
      SEL => Inst_minimum39to32_Mcompar_n0000_inst_lut2_2,
1117 
      O => Inst_minimum39to32_Mcompar_n0000_inst_cy_2
1118 
    );
1119 
  Inst_minimum39to32_Mcompar_n0000_inst_lut2_31 : X_LUT2
1120 
    generic map(
1121 
      INIT => X"9"
1122 
    )
1123 
    port map (
1124 
      ADR0 => B_35_IBUF,
1125 
      ADR1 => A_3_IBUF,
1126 
      O => Inst_minimum39to32_Mcompar_n0000_inst_lut2_3
1127 
    );
1128 
  Inst_minimum39to32_Mcompar_n0000_inst_cy_3_36 : X_MUX2
1129 
    port map (
1130 
      IB => Inst_minimum39to32_Mcompar_n0000_inst_cy_2,
1131 
      IA => B_35_IBUF,
1132 
      SEL => Inst_minimum39to32_Mcompar_n0000_inst_lut2_3,
1133 
      O => Inst_minimum39to32_Mcompar_n0000_inst_cy_3
1134 
    );
1135 
  Inst_minimum39to32_Mcompar_n0000_inst_lut2_41 : X_LUT2
1136 
    generic map(
1137 
      INIT => X"9"
1138 
    )
1139 
    port map (
1140 
      ADR0 => B_36_IBUF,
1141 
      ADR1 => A_4_IBUF,
1142 
      O => Inst_minimum39to32_Mcompar_n0000_inst_lut2_4
1143 
    );
1144 
  Inst_minimum39to32_Mcompar_n0000_inst_cy_4_37 : X_MUX2
1145 
    port map (
1146 
      IB => Inst_minimum39to32_Mcompar_n0000_inst_cy_3,
1147 
      IA => B_36_IBUF,
1148 
      SEL => Inst_minimum39to32_Mcompar_n0000_inst_lut2_4,
1149 
      O => Inst_minimum39to32_Mcompar_n0000_inst_cy_4
1150 
    );
1151 
  Inst_minimum39to32_Mcompar_n0000_inst_lut2_51 : X_LUT2
1152 
    generic map(
1153 
      INIT => X"9"
1154 
    )
1155 
    port map (
1156 
      ADR0 => B_37_IBUF,
1157 
      ADR1 => A_5_IBUF,
1158 
      O => Inst_minimum39to32_Mcompar_n0000_inst_lut2_5
1159 
    );
1160 
  Inst_minimum39to32_Mcompar_n0000_inst_cy_5_38 : X_MUX2
1161 
    port map (
1162 
      IB => Inst_minimum39to32_Mcompar_n0000_inst_cy_4,
1163 
      IA => B_37_IBUF,
1164 
      SEL => Inst_minimum39to32_Mcompar_n0000_inst_lut2_5,
1165 
      O => Inst_minimum39to32_Mcompar_n0000_inst_cy_5
1166 
    );
1167 
  Inst_minimum39to32_Mcompar_n0000_inst_lut2_61 : X_LUT2
1168 
    generic map(
1169 
      INIT => X"9"
1170 
    )
1171 
    port map (
1172 
      ADR0 => B_38_IBUF,
1173 
      ADR1 => A_6_IBUF,
1174 
      O => Inst_minimum39to32_Mcompar_n0000_inst_lut2_6
1175 
    );
1176 
  Inst_minimum47to40_Mcompar_n0000_inst_lut2_71 : X_LUT2
1177 
    generic map(
1178 
      INIT => X"9"
1179 
    )
1180 
    port map (
1181 
      ADR0 => B_47_IBUF,
1182 
      ADR1 => A_7_IBUF,
1183 
      O => Inst_minimum47to40_Mcompar_n0000_inst_lut2_7
1184 
    );
1185 
  Inst_minimum47to40_Mcompar_n0000_inst_cy_7 : X_MUX2
1186 
    port map (
1187 
      IB => Inst_minimum47to40_Mcompar_n0000_inst_cy_6,
1188 
      IA => B_47_IBUF,
1189 
      SEL => Inst_minimum47to40_Mcompar_n0000_inst_lut2_7,
1190 
      O => Inst_minimum47to40_n0000
1191 
    );
1192 
  Inst_minimum47to40_Mcompar_n0000_inst_lut2_01 : X_LUT2
1193 
    generic map(
1194 
      INIT => X"9"
1195 
    )
1196 
    port map (
1197 
      ADR0 => B_40_IBUF,
1198 
      ADR1 => A_0_IBUF,
1199 
      O => Inst_minimum47to40_Mcompar_n0000_inst_lut2_0
1200 
    );
1201 
  Inst_minimum47to40_Mcompar_n0000_inst_cy_0_39 : X_MUX2
1202 
    port map (
1203 
      IB => N183,
1204 
      IA => B_40_IBUF,
1205 
      SEL => Inst_minimum47to40_Mcompar_n0000_inst_lut2_0,
1206 
      O => Inst_minimum47to40_Mcompar_n0000_inst_cy_0
1207 
    );
1208 
  Inst_minimum47to40_Mcompar_n0000_inst_lut2_11 : X_LUT2
1209 
    generic map(
1210 
      INIT => X"9"
1211 
    )
1212 
    port map (
1213 
      ADR0 => B_41_IBUF,
1214 
      ADR1 => A_1_IBUF,
1215 
      O => Inst_minimum47to40_Mcompar_n0000_inst_lut2_1
1216 
    );
1217 
  Inst_minimum47to40_Mcompar_n0000_inst_cy_1_40 : X_MUX2
1218 
    port map (
1219 
      IB => Inst_minimum47to40_Mcompar_n0000_inst_cy_0,
1220 
      IA => B_41_IBUF,
1221 
      SEL => Inst_minimum47to40_Mcompar_n0000_inst_lut2_1,
1222 
      O => Inst_minimum47to40_Mcompar_n0000_inst_cy_1
1223 
    );
1224 
  Inst_minimum47to40_Mcompar_n0000_inst_lut2_21 : X_LUT2
1225 
    generic map(
1226 
      INIT => X"9"
1227 
    )
1228 
    port map (
1229 
      ADR0 => B_42_IBUF,
1230 
      ADR1 => A_2_IBUF,
1231 
      O => Inst_minimum47to40_Mcompar_n0000_inst_lut2_2
1232 
    );
1233 
  Inst_minimum47to40_Mcompar_n0000_inst_cy_2_41 : X_MUX2
1234 
    port map (
1235 
      IB => Inst_minimum47to40_Mcompar_n0000_inst_cy_1,
1236 
      IA => B_42_IBUF,
1237 
      SEL => Inst_minimum47to40_Mcompar_n0000_inst_lut2_2,
1238 
      O => Inst_minimum47to40_Mcompar_n0000_inst_cy_2
1239 
    );
1240 
  Inst_minimum47to40_Mcompar_n0000_inst_lut2_31 : X_LUT2
1241 
    generic map(
1242 
      INIT => X"9"
1243 
    )
1244 
    port map (
1245 
      ADR0 => B_43_IBUF,
1246 
      ADR1 => A_3_IBUF,
1247 
      O => Inst_minimum47to40_Mcompar_n0000_inst_lut2_3
1248 
    );
1249 
  Inst_minimum47to40_Mcompar_n0000_inst_cy_3_42 : X_MUX2
1250 
    port map (
1251 
      IB => Inst_minimum47to40_Mcompar_n0000_inst_cy_2,
1252 
      IA => B_43_IBUF,
1253 
      SEL => Inst_minimum47to40_Mcompar_n0000_inst_lut2_3,
1254 
      O => Inst_minimum47to40_Mcompar_n0000_inst_cy_3
1255 
    );
1256 
  Inst_minimum47to40_Mcompar_n0000_inst_lut2_41 : X_LUT2
1257 
    generic map(
1258 
      INIT => X"9"
1259 
    )
1260 
    port map (
1261 
      ADR0 => B_44_IBUF,
1262 
      ADR1 => A_4_IBUF,
1263 
      O => Inst_minimum47to40_Mcompar_n0000_inst_lut2_4
1264 
    );
1265 
  Inst_minimum47to40_Mcompar_n0000_inst_cy_4_43 : X_MUX2
1266 
    port map (
1267 
      IB => Inst_minimum47to40_Mcompar_n0000_inst_cy_3,
1268 
      IA => B_44_IBUF,
1269 
      SEL => Inst_minimum47to40_Mcompar_n0000_inst_lut2_4,
1270 
      O => Inst_minimum47to40_Mcompar_n0000_inst_cy_4
1271 
    );
1272 
  Inst_minimum47to40_Mcompar_n0000_inst_lut2_51 : X_LUT2
1273 
    generic map(
1274 
      INIT => X"9"
1275 
    )
1276 
    port map (
1277 
      ADR0 => B_45_IBUF,
1278 
      ADR1 => A_5_IBUF,
1279 
      O => Inst_minimum47to40_Mcompar_n0000_inst_lut2_5
1280 
    );
1281 
  Inst_minimum47to40_Mcompar_n0000_inst_cy_5_44 : X_MUX2
1282 
    port map (
1283 
      IB => Inst_minimum47to40_Mcompar_n0000_inst_cy_4,
1284 
      IA => B_45_IBUF,
1285 
      SEL => Inst_minimum47to40_Mcompar_n0000_inst_lut2_5,
1286 
      O => Inst_minimum47to40_Mcompar_n0000_inst_cy_5
1287 
    );
1288 
  Inst_minimum47to40_Mcompar_n0000_inst_lut2_61 : X_LUT2
1289 
    generic map(
1290 
      INIT => X"9"
1291 
    )
1292 
    port map (
1293 
      ADR0 => B_46_IBUF,
1294 
      ADR1 => A_6_IBUF,
1295 
      O => Inst_minimum47to40_Mcompar_n0000_inst_lut2_6
1296 
    );
1297 
  Inst_minimum55to48_Mcompar_n0000_inst_lut2_71 : X_LUT2
1298 
    generic map(
1299 
      INIT => X"9"
1300 
    )
1301 
    port map (
1302 
      ADR0 => B_55_IBUF,
1303 
      ADR1 => A_7_IBUF,
1304 
      O => Inst_minimum55to48_Mcompar_n0000_inst_lut2_7
1305 
    );
1306 
  Inst_minimum55to48_Mcompar_n0000_inst_cy_7 : X_MUX2
1307 
    port map (
1308 
      IB => Inst_minimum55to48_Mcompar_n0000_inst_cy_6,
1309 
      IA => B_55_IBUF,
1310 
      SEL => Inst_minimum55to48_Mcompar_n0000_inst_lut2_7,
1311 
      O => Inst_minimum55to48_n0000
1312 
    );
1313 
  Inst_minimum55to48_Mcompar_n0000_inst_lut2_01 : X_LUT2
1314 
    generic map(
1315 
      INIT => X"9"
1316 
    )
1317 
    port map (
1318 
      ADR0 => B_48_IBUF,
1319 
      ADR1 => A_0_IBUF,
1320 
      O => Inst_minimum55to48_Mcompar_n0000_inst_lut2_0
1321 
    );
1322 
  Inst_minimum55to48_Mcompar_n0000_inst_cy_0_45 : X_MUX2
1323 
    port map (
1324 
      IB => N183,
1325 
      IA => B_48_IBUF,
1326 
      SEL => Inst_minimum55to48_Mcompar_n0000_inst_lut2_0,
1327 
      O => Inst_minimum55to48_Mcompar_n0000_inst_cy_0
1328 
    );
1329 
  Inst_minimum55to48_Mcompar_n0000_inst_lut2_11 : X_LUT2
1330 
    generic map(
1331 
      INIT => X"9"
1332 
    )
1333 
    port map (
1334 
      ADR0 => B_49_IBUF,
1335 
      ADR1 => A_1_IBUF,
1336 
      O => Inst_minimum55to48_Mcompar_n0000_inst_lut2_1
1337 
    );
1338 
  Inst_minimum55to48_Mcompar_n0000_inst_cy_1_46 : X_MUX2
1339 
    port map (
1340 
      IB => Inst_minimum55to48_Mcompar_n0000_inst_cy_0,
1341 
      IA => B_49_IBUF,
1342 
      SEL => Inst_minimum55to48_Mcompar_n0000_inst_lut2_1,
1343 
      O => Inst_minimum55to48_Mcompar_n0000_inst_cy_1
1344 
    );
1345 
  Inst_minimum55to48_Mcompar_n0000_inst_lut2_21 : X_LUT2
1346 
    generic map(
1347 
      INIT => X"9"
1348 
    )
1349 
    port map (
1350 
      ADR0 => B_50_IBUF,
1351 
      ADR1 => A_2_IBUF,
1352 
      O => Inst_minimum55to48_Mcompar_n0000_inst_lut2_2
1353 
    );
1354 
  Inst_minimum55to48_Mcompar_n0000_inst_cy_2_47 : X_MUX2
1355 
    port map (
1356 
      IB => Inst_minimum55to48_Mcompar_n0000_inst_cy_1,
1357 
      IA => B_50_IBUF,
1358 
      SEL => Inst_minimum55to48_Mcompar_n0000_inst_lut2_2,
1359 
      O => Inst_minimum55to48_Mcompar_n0000_inst_cy_2
1360 
    );
1361 
  Inst_minimum55to48_Mcompar_n0000_inst_lut2_31 : X_LUT2
1362 
    generic map(
1363 
      INIT => X"9"
1364 
    )
1365 
    port map (
1366 
      ADR0 => B_51_IBUF,
1367 
      ADR1 => A_3_IBUF,
1368 
      O => Inst_minimum55to48_Mcompar_n0000_inst_lut2_3
1369 
    );
1370 
  Inst_minimum55to48_Mcompar_n0000_inst_cy_3_48 : X_MUX2
1371 
    port map (
1372 
      IB => Inst_minimum55to48_Mcompar_n0000_inst_cy_2,
1373 
      IA => B_51_IBUF,
1374 
      SEL => Inst_minimum55to48_Mcompar_n0000_inst_lut2_3,
1375 
      O => Inst_minimum55to48_Mcompar_n0000_inst_cy_3
1376 
    );
1377 
  Inst_minimum55to48_Mcompar_n0000_inst_lut2_41 : X_LUT2
1378 
    generic map(
1379 
      INIT => X"9"
1380 
    )
1381 
    port map (
1382 
      ADR0 => B_52_IBUF,
1383 
      ADR1 => A_4_IBUF,
1384 
      O => Inst_minimum55to48_Mcompar_n0000_inst_lut2_4
1385 
    );
1386 
  Inst_minimum55to48_Mcompar_n0000_inst_cy_4_49 : X_MUX2
1387 
    port map (
1388 
      IB => Inst_minimum55to48_Mcompar_n0000_inst_cy_3,
1389 
      IA => B_52_IBUF,
1390 
      SEL => Inst_minimum55to48_Mcompar_n0000_inst_lut2_4,
1391 
      O => Inst_minimum55to48_Mcompar_n0000_inst_cy_4
1392 
    );
1393 
  Inst_minimum55to48_Mcompar_n0000_inst_lut2_51 : X_LUT2
1394 
    generic map(
1395 
      INIT => X"9"
1396 
    )
1397 
    port map (
1398 
      ADR0 => B_53_IBUF,
1399 
      ADR1 => A_5_IBUF,
1400 
      O => Inst_minimum55to48_Mcompar_n0000_inst_lut2_5
1401 
    );
1402 
  Inst_minimum55to48_Mcompar_n0000_inst_cy_5_50 : X_MUX2
1403 
    port map (
1404 
      IB => Inst_minimum55to48_Mcompar_n0000_inst_cy_4,
1405 
      IA => B_53_IBUF,
1406 
      SEL => Inst_minimum55to48_Mcompar_n0000_inst_lut2_5,
1407 
      O => Inst_minimum55to48_Mcompar_n0000_inst_cy_5
1408 
    );
1409 
  Inst_minimum55to48_Mcompar_n0000_inst_lut2_61 : X_LUT2
1410 
    generic map(
1411 
      INIT => X"9"
1412 
    )
1413 
    port map (
1414 
      ADR0 => B_54_IBUF,
1415 
      ADR1 => A_6_IBUF,
1416 
      O => Inst_minimum55to48_Mcompar_n0000_inst_lut2_6
1417 
    );
1418 
  Inst_minimum63to56_Mcompar_n0000_inst_lut2_71 : X_LUT2
1419 
    generic map(
1420 
      INIT => X"9"
1421 
    )
1422 
    port map (
1423 
      ADR0 => B_63_IBUF,
1424 
      ADR1 => A_7_IBUF,
1425 
      O => Inst_minimum63to56_Mcompar_n0000_inst_lut2_7
1426 
    );
1427 
  Inst_minimum63to56_Mcompar_n0000_inst_cy_7 : X_MUX2
1428 
    port map (
1429 
      IB => Inst_minimum63to56_Mcompar_n0000_inst_cy_6,
1430 
      IA => B_63_IBUF,
1431 
      SEL => Inst_minimum63to56_Mcompar_n0000_inst_lut2_7,
1432 
      O => Inst_minimum63to56_n0000
1433 
    );
1434 
  Inst_minimum63to56_Mcompar_n0000_inst_lut2_01 : X_LUT2
1435 
    generic map(
1436 
      INIT => X"9"
1437 
    )
1438 
    port map (
1439 
      ADR0 => B_56_IBUF,
1440 
      ADR1 => A_0_IBUF,
1441 
      O => Inst_minimum63to56_Mcompar_n0000_inst_lut2_0
1442 
    );
1443 
  Inst_minimum63to56_Mcompar_n0000_inst_cy_0_51 : X_MUX2
1444 
    port map (
1445 
      IB => N183,
1446 
      IA => B_56_IBUF,
1447 
      SEL => Inst_minimum63to56_Mcompar_n0000_inst_lut2_0,
1448 
      O => Inst_minimum63to56_Mcompar_n0000_inst_cy_0
1449 
    );
1450 
  Inst_minimum63to56_Mcompar_n0000_inst_lut2_11 : X_LUT2
1451 
    generic map(
1452 
      INIT => X"9"
1453 
    )
1454 
    port map (
1455 
      ADR0 => B_57_IBUF,
1456 
      ADR1 => A_1_IBUF,
1457 
      O => Inst_minimum63to56_Mcompar_n0000_inst_lut2_1
1458 
    );
1459 
  Inst_minimum63to56_Mcompar_n0000_inst_cy_1_52 : X_MUX2
1460 
    port map (
1461 
      IB => Inst_minimum63to56_Mcompar_n0000_inst_cy_0,
1462 
      IA => B_57_IBUF,
1463 
      SEL => Inst_minimum63to56_Mcompar_n0000_inst_lut2_1,
1464 
      O => Inst_minimum63to56_Mcompar_n0000_inst_cy_1
1465 
    );
1466 
  Inst_minimum63to56_Mcompar_n0000_inst_lut2_21 : X_LUT2
1467 
    generic map(
1468 
      INIT => X"9"
1469 
    )
1470 
    port map (
1471 
      ADR0 => B_58_IBUF,
1472 
      ADR1 => A_2_IBUF,
1473 
      O => Inst_minimum63to56_Mcompar_n0000_inst_lut2_2
1474 
    );
1475 
  Inst_minimum63to56_Mcompar_n0000_inst_cy_2_53 : X_MUX2
1476 
    port map (
1477 
      IB => Inst_minimum63to56_Mcompar_n0000_inst_cy_1,
1478 
      IA => B_58_IBUF,
1479 
      SEL => Inst_minimum63to56_Mcompar_n0000_inst_lut2_2,
1480 
      O => Inst_minimum63to56_Mcompar_n0000_inst_cy_2
1481 
    );
1482 
  Inst_minimum63to56_Mcompar_n0000_inst_lut2_31 : X_LUT2
1483 
    generic map(
1484 
      INIT => X"9"
1485 
    )
1486 
    port map (
1487 
      ADR0 => B_59_IBUF,
1488 
      ADR1 => A_3_IBUF,
1489 
      O => Inst_minimum63to56_Mcompar_n0000_inst_lut2_3
1490 
    );
1491 
  Inst_minimum63to56_Mcompar_n0000_inst_cy_3_54 : X_MUX2
1492 
    port map (
1493 
      IB => Inst_minimum63to56_Mcompar_n0000_inst_cy_2,
1494 
      IA => B_59_IBUF,
1495 
      SEL => Inst_minimum63to56_Mcompar_n0000_inst_lut2_3,
1496 
      O => Inst_minimum63to56_Mcompar_n0000_inst_cy_3
1497 
    );
1498 
  Inst_minimum63to56_Mcompar_n0000_inst_lut2_41 : X_LUT2
1499 
    generic map(
1500 
      INIT => X"9"
1501 
    )
1502 
    port map (
1503 
      ADR0 => B_60_IBUF,
1504 
      ADR1 => A_4_IBUF,
1505 
      O => Inst_minimum63to56_Mcompar_n0000_inst_lut2_4
1506 
    );
1507 
  Inst_minimum63to56_Mcompar_n0000_inst_cy_4_55 : X_MUX2
1508 
    port map (
1509 
      IB => Inst_minimum63to56_Mcompar_n0000_inst_cy_3,
1510 
      IA => B_60_IBUF,
1511 
      SEL => Inst_minimum63to56_Mcompar_n0000_inst_lut2_4,
1512 
      O => Inst_minimum63to56_Mcompar_n0000_inst_cy_4
1513 
    );
1514 
  Inst_minimum63to56_Mcompar_n0000_inst_lut2_51 : X_LUT2
1515 
    generic map(
1516 
      INIT => X"9"
1517 
    )
1518 
    port map (
1519 
      ADR0 => B_61_IBUF,
1520 
      ADR1 => A_5_IBUF,
1521 
      O => Inst_minimum63to56_Mcompar_n0000_inst_lut2_5
1522 
    );
1523 
  Inst_minimum63to56_Mcompar_n0000_inst_cy_5_56 : X_MUX2
1524 
    port map (
1525 
      IB => Inst_minimum63to56_Mcompar_n0000_inst_cy_4,
1526 
      IA => B_61_IBUF,
1527 
      SEL => Inst_minimum63to56_Mcompar_n0000_inst_lut2_5,
1528 
      O => Inst_minimum63to56_Mcompar_n0000_inst_cy_5
1529 
    );
1530 
  Inst_minimum63to56_Mcompar_n0000_inst_lut2_61 : X_LUT2
1531 
    generic map(
1532 
      INIT => X"9"
1533 
    )
1534 
    port map (
1535 
      ADR0 => B_62_IBUF,
1536 
      ADR1 => A_6_IBUF,
1537 
      O => Inst_minimum63to56_Mcompar_n0000_inst_lut2_6
1538 
    );
1539 
  Inst_minimum7to0_Mmux_C_Result_0_1 : X_LUT3
1540 
    generic map(
1541 
      INIT => X"E4"
1542 
    )
1543 
    port map (
1544 
      ADR0 => Inst_minimum7to0_n0000,
1545 
      ADR1 => B_0_IBUF,
1546 
      ADR2 => A_0_IBUF,
1547 
      O => C_0_OBUF
1548 
    );
1549 
  Inst_minimum7to0_Mmux_C_Result_1_1 : X_LUT3
1550 
    generic map(
1551 
      INIT => X"E4"
1552 
    )
1553 
    port map (
1554 
      ADR0 => Inst_minimum7to0_n0000,
1555 
      ADR1 => B_1_IBUF,
1556 
      ADR2 => A_1_IBUF,
1557 
      O => C_1_OBUF
1558 
    );
1559 
  Inst_minimum7to0_Mmux_C_Result_2_1 : X_LUT3
1560 
    generic map(
1561 
      INIT => X"E4"
1562 
    )
1563 
    port map (
1564 
      ADR0 => Inst_minimum7to0_n0000,
1565 
      ADR1 => B_2_IBUF,
1566 
      ADR2 => A_2_IBUF,
1567 
      O => C_2_OBUF
1568 
    );
1569 
  Inst_minimum7to0_Mmux_C_Result_3_1 : X_LUT3
1570 
    generic map(
1571 
      INIT => X"E4"
1572 
    )
1573 
    port map (
1574 
      ADR0 => Inst_minimum7to0_n0000,
1575 
      ADR1 => B_3_IBUF,
1576 
      ADR2 => A_3_IBUF,
1577 
      O => C_3_OBUF
1578 
    );
1579 
  Inst_minimum7to0_Mmux_C_Result_4_1 : X_LUT3
1580 
    generic map(
1581 
      INIT => X"E4"
1582 
    )
1583 
    port map (
1584 
      ADR0 => Inst_minimum7to0_n0000,
1585 
      ADR1 => B_4_IBUF,
1586 
      ADR2 => A_4_IBUF,
1587 
      O => C_4_OBUF
1588 
    );
1589 
  Inst_minimum7to0_Mmux_C_Result_5_1 : X_LUT3
1590 
    generic map(
1591 
      INIT => X"E4"
1592 
    )
1593 
    port map (
1594 
      ADR0 => Inst_minimum7to0_n0000,
1595 
      ADR1 => B_5_IBUF,
1596 
      ADR2 => A_5_IBUF,
1597 
      O => C_5_OBUF
1598 
    );
1599 
  Inst_minimum7to0_Mmux_C_Result_6_1 : X_LUT3
1600 
    generic map(
1601 
      INIT => X"E4"
1602 
    )
1603 
    port map (
1604 
      ADR0 => Inst_minimum7to0_n0000,
1605 
      ADR1 => B_6_IBUF,
1606 
      ADR2 => A_6_IBUF,
1607 
      O => C_6_OBUF
1608 
    );
1609 
  Inst_minimum15to8_Mmux_C_Result_0_1 : X_LUT3
1610 
    generic map(
1611 
      INIT => X"E4"
1612 
    )
1613 
    port map (
1614 
      ADR0 => Inst_minimum15to8_n0000,
1615 
      ADR1 => B_8_IBUF,
1616 
      ADR2 => A_0_IBUF,
1617 
      O => C_8_OBUF
1618 
    );
1619 
  Inst_minimum15to8_Mmux_C_Result_1_1 : X_LUT3
1620 
    generic map(
1621 
      INIT => X"E4"
1622 
    )
1623 
    port map (
1624 
      ADR0 => Inst_minimum15to8_n0000,
1625 
      ADR1 => B_9_IBUF,
1626 
      ADR2 => A_1_IBUF,
1627 
      O => C_9_OBUF
1628 
    );
1629 
  Inst_minimum15to8_Mmux_C_Result_2_1 : X_LUT3
1630 
    generic map(
1631 
      INIT => X"E4"
1632 
    )
1633 
    port map (
1634 
      ADR0 => Inst_minimum15to8_n0000,
1635 
      ADR1 => B_10_IBUF,
1636 
      ADR2 => A_2_IBUF,
1637 
      O => C_10_OBUF
1638 
    );
1639 
  Inst_minimum15to8_Mmux_C_Result_3_1 : X_LUT3
1640 
    generic map(
1641 
      INIT => X"E4"
1642 
    )
1643 
    port map (
1644 
      ADR0 => Inst_minimum15to8_n0000,
1645 
      ADR1 => B_11_IBUF,
1646 
      ADR2 => A_3_IBUF,
1647 
      O => C_11_OBUF
1648 
    );
1649 
  Inst_minimum15to8_Mmux_C_Result_4_1 : X_LUT3
1650 
    generic map(
1651 
      INIT => X"E4"
1652 
    )
1653 
    port map (
1654 
      ADR0 => Inst_minimum15to8_n0000,
1655 
      ADR1 => B_12_IBUF,
1656 
      ADR2 => A_4_IBUF,
1657 
      O => C_12_OBUF
1658 
    );
1659 
  Inst_minimum15to8_Mmux_C_Result_5_1 : X_LUT3
1660 
    generic map(
1661 
      INIT => X"E4"
1662 
    )
1663 
    port map (
1664 
      ADR0 => Inst_minimum15to8_n0000,
1665 
      ADR1 => B_13_IBUF,
1666 
      ADR2 => A_5_IBUF,
1667 
      O => C_13_OBUF
1668 
    );
1669 
  Inst_minimum15to8_Mmux_C_Result_6_1 : X_LUT3
1670 
    generic map(
1671 
      INIT => X"E4"
1672 
    )
1673 
    port map (
1674 
      ADR0 => Inst_minimum15to8_n0000,
1675 
      ADR1 => B_14_IBUF,
1676 
      ADR2 => A_6_IBUF,
1677 
      O => C_14_OBUF
1678 
    );
1679 
  Inst_minimum23to16_Mmux_C_Result_0_1 : X_LUT3
1680 
    generic map(
1681 
      INIT => X"E4"
1682 
    )
1683 
    port map (
1684 
      ADR0 => Inst_minimum23to16_n0000,
1685 
      ADR1 => B_16_IBUF,
1686 
      ADR2 => A_0_IBUF,
1687 
      O => C_16_OBUF
1688 
    );
1689 
  Inst_minimum23to16_Mmux_C_Result_1_1 : X_LUT3
1690 
    generic map(
1691 
      INIT => X"E4"
1692 
    )
1693 
    port map (
1694 
      ADR0 => Inst_minimum23to16_n0000,
1695 
      ADR1 => B_17_IBUF,
1696 
      ADR2 => A_1_IBUF,
1697 
      O => C_17_OBUF
1698 
    );
1699 
  Inst_minimum23to16_Mmux_C_Result_2_1 : X_LUT3
1700 
    generic map(
1701 
      INIT => X"E4"
1702 
    )
1703 
    port map (
1704 
      ADR0 => Inst_minimum23to16_n0000,
1705 
      ADR1 => B_18_IBUF,
1706 
      ADR2 => A_2_IBUF,
1707 
      O => C_18_OBUF
1708 
    );
1709 
  Inst_minimum23to16_Mmux_C_Result_3_1 : X_LUT3
1710 
    generic map(
1711 
      INIT => X"E4"
1712 
    )
1713 
    port map (
1714 
      ADR0 => Inst_minimum23to16_n0000,
1715 
      ADR1 => B_19_IBUF,
1716 
      ADR2 => A_3_IBUF,
1717 
      O => C_19_OBUF
1718 
    );
1719 
  Inst_minimum23to16_Mmux_C_Result_4_1 : X_LUT3
1720 
    generic map(
1721 
      INIT => X"E4"
1722 
    )
1723 
    port map (
1724 
      ADR0 => Inst_minimum23to16_n0000,
1725 
      ADR1 => B_20_IBUF,
1726 
      ADR2 => A_4_IBUF,
1727 
      O => C_20_OBUF
1728 
    );
1729 
  Inst_minimum23to16_Mmux_C_Result_5_1 : X_LUT3
1730 
    generic map(
1731 
      INIT => X"E4"
1732 
    )
1733 
    port map (
1734 
      ADR0 => Inst_minimum23to16_n0000,
1735 
      ADR1 => B_21_IBUF,
1736 
      ADR2 => A_5_IBUF,
1737 
      O => C_21_OBUF
1738 
    );
1739 
  Inst_minimum23to16_Mmux_C_Result_6_1 : X_LUT3
1740 
    generic map(
1741 
      INIT => X"E4"
1742 
    )
1743 
    port map (
1744 
      ADR0 => Inst_minimum23to16_n0000,
1745 
      ADR1 => B_22_IBUF,
1746 
      ADR2 => A_6_IBUF,
1747 
      O => C_22_OBUF
1748 
    );
1749 
  Inst_minimum31to24_Mmux_C_Result_0_1 : X_LUT3
1750 
    generic map(
1751 
      INIT => X"E4"
1752 
    )
1753 
    port map (
1754 
      ADR0 => Inst_minimum31to24_n0000,
1755 
      ADR1 => B_24_IBUF,
1756 
      ADR2 => A_0_IBUF,
1757 
      O => C_24_OBUF
1758 
    );
1759 
  Inst_minimum31to24_Mmux_C_Result_1_1 : X_LUT3
1760 
    generic map(
1761 
      INIT => X"E4"
1762 
    )
1763 
    port map (
1764 
      ADR0 => Inst_minimum31to24_n0000,
1765 
      ADR1 => B_25_IBUF,
1766 
      ADR2 => A_1_IBUF,
1767 
      O => C_25_OBUF
1768 
    );
1769 
  Inst_minimum31to24_Mmux_C_Result_2_1 : X_LUT3
1770 
    generic map(
1771 
      INIT => X"E4"
1772 
    )
1773 
    port map (
1774 
      ADR0 => Inst_minimum31to24_n0000,
1775 
      ADR1 => B_26_IBUF,
1776 
      ADR2 => A_2_IBUF,
1777 
      O => C_26_OBUF
1778 
    );
1779 
  Inst_minimum31to24_Mmux_C_Result_3_1 : X_LUT3
1780 
    generic map(
1781 
      INIT => X"E4"
1782 
    )
1783 
    port map (
1784 
      ADR0 => Inst_minimum31to24_n0000,
1785 
      ADR1 => B_27_IBUF,
1786 
      ADR2 => A_3_IBUF,
1787 
      O => C_27_OBUF
1788 
    );
1789 
  Inst_minimum31to24_Mmux_C_Result_4_1 : X_LUT3
1790 
    generic map(
1791 
      INIT => X"E4"
1792 
    )
1793 
    port map (
1794 
      ADR0 => Inst_minimum31to24_n0000,
1795 
      ADR1 => B_28_IBUF,
1796 
      ADR2 => A_4_IBUF,
1797 
      O => C_28_OBUF
1798 
    );
1799 
  Inst_minimum31to24_Mmux_C_Result_5_1 : X_LUT3
1800 
    generic map(
1801 
      INIT => X"E4"
1802 
    )
1803 
    port map (
1804 
      ADR0 => Inst_minimum31to24_n0000,
1805 
      ADR1 => B_29_IBUF,
1806 
      ADR2 => A_5_IBUF,
1807 
      O => C_29_OBUF
1808 
    );
1809 
  Inst_minimum31to24_Mmux_C_Result_6_1 : X_LUT3
1810 
    generic map(
1811 
      INIT => X"E4"
1812 
    )
1813 
    port map (
1814 
      ADR0 => Inst_minimum31to24_n0000,
1815 
      ADR1 => B_30_IBUF,
1816 
      ADR2 => A_6_IBUF,
1817 
      O => C_30_OBUF
1818 
    );
1819 
  Inst_minimum39to32_Mmux_C_Result_0_1 : X_LUT3
1820 
    generic map(
1821 
      INIT => X"E4"
1822 
    )
1823 
    port map (
1824 
      ADR0 => Inst_minimum39to32_n0000,
1825 
      ADR1 => B_32_IBUF,
1826 
      ADR2 => A_0_IBUF,
1827 
      O => C_32_OBUF
1828 
    );
1829 
  Inst_minimum39to32_Mmux_C_Result_1_1 : X_LUT3
1830 
    generic map(
1831 
      INIT => X"E4"
1832 
    )
1833 
    port map (
1834 
      ADR0 => Inst_minimum39to32_n0000,
1835 
      ADR1 => B_33_IBUF,
1836 
      ADR2 => A_1_IBUF,
1837 
      O => C_33_OBUF
1838 
    );
1839 
  Inst_minimum39to32_Mmux_C_Result_2_1 : X_LUT3
1840 
    generic map(
1841 
      INIT => X"E4"
1842 
    )
1843 
    port map (
1844 
      ADR0 => Inst_minimum39to32_n0000,
1845 
      ADR1 => B_34_IBUF,
1846 
      ADR2 => A_2_IBUF,
1847 
      O => C_34_OBUF
1848 
    );
1849 
  Inst_minimum39to32_Mmux_C_Result_3_1 : X_LUT3
1850 
    generic map(
1851 
      INIT => X"E4"
1852 
    )
1853 
    port map (
1854 
      ADR0 => Inst_minimum39to32_n0000,
1855 
      ADR1 => B_35_IBUF,
1856 
      ADR2 => A_3_IBUF,
1857 
      O => C_35_OBUF
1858 
    );
1859 
  Inst_minimum39to32_Mmux_C_Result_4_1 : X_LUT3
1860 
    generic map(
1861 
      INIT => X"E4"
1862 
    )
1863 
    port map (
1864 
      ADR0 => Inst_minimum39to32_n0000,
1865 
      ADR1 => B_36_IBUF,
1866 
      ADR2 => A_4_IBUF,
1867 
      O => C_36_OBUF
1868 
    );
1869 
  Inst_minimum39to32_Mmux_C_Result_5_1 : X_LUT3
1870 
    generic map(
1871 
      INIT => X"E4"
1872 
    )
1873 
    port map (
1874 
      ADR0 => Inst_minimum39to32_n0000,
1875 
      ADR1 => B_37_IBUF,
1876 
      ADR2 => A_5_IBUF,
1877 
      O => C_37_OBUF
1878 
    );
1879 
  Inst_minimum39to32_Mmux_C_Result_6_1 : X_LUT3
1880 
    generic map(
1881 
      INIT => X"E4"
1882 
    )
1883 
    port map (
1884 
      ADR0 => Inst_minimum39to32_n0000,
1885 
      ADR1 => B_38_IBUF,
1886 
      ADR2 => A_6_IBUF,
1887 
      O => C_38_OBUF
1888 
    );
1889 
  Inst_minimum47to40_Mmux_C_Result_0_1 : X_LUT3
1890 
    generic map(
1891 
      INIT => X"E4"
1892 
    )
1893 
    port map (
1894 
      ADR0 => Inst_minimum47to40_n0000,
1895 
      ADR1 => B_40_IBUF,
1896 
      ADR2 => A_0_IBUF,
1897 
      O => C_40_OBUF
1898 
    );
1899 
  Inst_minimum47to40_Mmux_C_Result_1_1 : X_LUT3
1900 
    generic map(
1901 
      INIT => X"E4"
1902 
    )
1903 
    port map (
1904 
      ADR0 => Inst_minimum47to40_n0000,
1905 
      ADR1 => B_41_IBUF,
1906 
      ADR2 => A_1_IBUF,
1907 
      O => C_41_OBUF
1908 
    );
1909 
  Inst_minimum47to40_Mmux_C_Result_2_1 : X_LUT3
1910 
    generic map(
1911 
      INIT => X"E4"
1912 
    )
1913 
    port map (
1914 
      ADR0 => Inst_minimum47to40_n0000,
1915 
      ADR1 => B_42_IBUF,
1916 
      ADR2 => A_2_IBUF,
1917 
      O => C_42_OBUF
1918 
    );
1919 
  Inst_minimum47to40_Mmux_C_Result_3_1 : X_LUT3
1920 
    generic map(
1921 
      INIT => X"E4"
1922 
    )
1923 
    port map (
1924 
      ADR0 => Inst_minimum47to40_n0000,
1925 
      ADR1 => B_43_IBUF,
1926 
      ADR2 => A_3_IBUF,
1927 
      O => C_43_OBUF
1928 
    );
1929 
  Inst_minimum47to40_Mmux_C_Result_4_1 : X_LUT3
1930 
    generic map(
1931 
      INIT => X"E4"
1932 
    )
1933 
    port map (
1934 
      ADR0 => Inst_minimum47to40_n0000,
1935 
      ADR1 => B_44_IBUF,
1936 
      ADR2 => A_4_IBUF,
1937 
      O => C_44_OBUF
1938 
    );
1939 
  Inst_minimum47to40_Mmux_C_Result_5_1 : X_LUT3
1940 
    generic map(
1941 
      INIT => X"E4"
1942 
    )
1943 
    port map (
1944 
      ADR0 => Inst_minimum47to40_n0000,
1945 
      ADR1 => B_45_IBUF,
1946 
      ADR2 => A_5_IBUF,
1947 
      O => C_45_OBUF
1948 
    );
1949 
  Inst_minimum47to40_Mmux_C_Result_6_1 : X_LUT3
1950 
    generic map(
1951 
      INIT => X"E4"
1952 
    )
1953 
    port map (
1954 
      ADR0 => Inst_minimum47to40_n0000,
1955 
      ADR1 => B_46_IBUF,
1956 
      ADR2 => A_6_IBUF,
1957 
      O => C_46_OBUF
1958 
    );
1959 
  Inst_minimum55to48_Mmux_C_Result_0_1 : X_LUT3
1960 
    generic map(
1961 
      INIT => X"E4"
1962 
    )
1963 
    port map (
1964 
      ADR0 => Inst_minimum55to48_n0000,
1965 
      ADR1 => B_48_IBUF,
1966 
      ADR2 => A_0_IBUF,
1967 
      O => C_48_OBUF
1968 
    );
1969 
  Inst_minimum55to48_Mmux_C_Result_1_1 : X_LUT3
1970 
    generic map(
1971 
      INIT => X"E4"
1972 
    )
1973 
    port map (
1974 
      ADR0 => Inst_minimum55to48_n0000,
1975 
      ADR1 => B_49_IBUF,
1976 
      ADR2 => A_1_IBUF,
1977 
      O => C_49_OBUF
1978 
    );
1979 
  Inst_minimum55to48_Mmux_C_Result_2_1 : X_LUT3
1980 
    generic map(
1981 
      INIT => X"E4"
1982 
    )
1983 
    port map (
1984 
      ADR0 => Inst_minimum55to48_n0000,
1985 
      ADR1 => B_50_IBUF,
1986 
      ADR2 => A_2_IBUF,
1987 
      O => C_50_OBUF
1988 
    );
1989 
  Inst_minimum55to48_Mmux_C_Result_3_1 : X_LUT3
1990 
    generic map(
1991 
      INIT => X"E4"
1992 
    )
1993 
    port map (
1994 
      ADR0 => Inst_minimum55to48_n0000,
1995 
      ADR1 => B_51_IBUF,
1996 
      ADR2 => A_3_IBUF,
1997 
      O => C_51_OBUF
1998 
    );
1999 
  Inst_minimum55to48_Mmux_C_Result_4_1 : X_LUT3
2000 
    generic map(
2001 
      INIT => X"E4"
2002 
    )
2003 
    port map (
2004 
      ADR0 => Inst_minimum55to48_n0000,
2005 
      ADR1 => B_52_IBUF,
2006 
      ADR2 => A_4_IBUF,
2007 
      O => C_52_OBUF
2008 
    );
2009 
  Inst_minimum55to48_Mmux_C_Result_5_1 : X_LUT3
2010 
    generic map(
2011 
      INIT => X"E4"
2012 
    )
2013 
    port map (
2014 
      ADR0 => Inst_minimum55to48_n0000,
2015 
      ADR1 => B_53_IBUF,
2016 
      ADR2 => A_5_IBUF,
2017 
      O => C_53_OBUF
2018 
    );
2019 
  Inst_minimum55to48_Mmux_C_Result_6_1 : X_LUT3
2020 
    generic map(
2021 
      INIT => X"E4"
2022 
    )
2023 
    port map (
2024 
      ADR0 => Inst_minimum55to48_n0000,
2025 
      ADR1 => B_54_IBUF,
2026 
      ADR2 => A_6_IBUF,
2027 
      O => C_54_OBUF
2028 
    );
2029 
  Inst_minimum63to56_Mmux_C_Result_0_1 : X_LUT3
2030 
    generic map(
2031 
      INIT => X"E4"
2032 
    )
2033 
    port map (
2034 
      ADR0 => Inst_minimum63to56_n0000,
2035 
      ADR1 => B_56_IBUF,
2036 
      ADR2 => A_0_IBUF,
2037 
      O => C_56_OBUF
2038 
    );
2039 
  Inst_minimum63to56_Mmux_C_Result_1_1 : X_LUT3
2040 
    generic map(
2041 
      INIT => X"E4"
2042 
    )
2043 
    port map (
2044 
      ADR0 => Inst_minimum63to56_n0000,
2045 
      ADR1 => B_57_IBUF,
2046 
      ADR2 => A_1_IBUF,
2047 
      O => C_57_OBUF
2048 
    );
2049 
  Inst_minimum63to56_Mmux_C_Result_2_1 : X_LUT3
2050 
    generic map(
2051 
      INIT => X"E4"
2052 
    )
2053 
    port map (
2054 
      ADR0 => Inst_minimum63to56_n0000,
2055 
      ADR1 => B_58_IBUF,
2056 
      ADR2 => A_2_IBUF,
2057 
      O => C_58_OBUF
2058 
    );
2059 
  Inst_minimum63to56_Mmux_C_Result_3_1 : X_LUT3
2060 
    generic map(
2061 
      INIT => X"E4"
2062 
    )
2063 
    port map (
2064 
      ADR0 => Inst_minimum63to56_n0000,
2065 
      ADR1 => B_59_IBUF,
2066 
      ADR2 => A_3_IBUF,
2067 
      O => C_59_OBUF
2068 
    );
2069 
  Inst_minimum63to56_Mmux_C_Result_4_1 : X_LUT3
2070 
    generic map(
2071 
      INIT => X"E4"
2072 
    )
2073 
    port map (
2074 
      ADR0 => Inst_minimum63to56_n0000,
2075 
      ADR1 => B_60_IBUF,
2076 
      ADR2 => A_4_IBUF,
2077 
      O => C_60_OBUF
2078 
    );
2079 
  Inst_minimum63to56_Mmux_C_Result_5_1 : X_LUT3
2080 
    generic map(
2081 
      INIT => X"E4"
2082 
    )
2083 
    port map (
2084 
      ADR0 => Inst_minimum63to56_n0000,
2085 
      ADR1 => B_61_IBUF,
2086 
      ADR2 => A_5_IBUF,
2087 
      O => C_61_OBUF
2088 
    );
2089 
  Inst_minimum63to56_Mmux_C_Result_6_1 : X_LUT3
2090 
    generic map(
2091 
      INIT => X"E4"
2092 
    )
2093 
    port map (
2094 
      ADR0 => Inst_minimum63to56_n0000,
2095 
      ADR1 => B_62_IBUF,
2096 
      ADR2 => A_6_IBUF,
2097 
      O => C_62_OBUF
2098 
    );
2099 
  A_7_IBUF_57 : X_BUF
2100 
    port map (
2101 
      I => A(7),
2102 
      O => A_7_IBUF
2103 
    );
2104 
  A_6_IBUF_58 : X_BUF
2105 
    port map (
2106 
      I => A(6),
2107 
      O => A_6_IBUF
2108 
    );
2109 
  A_5_IBUF_59 : X_BUF
2110 
    port map (
2111 
      I => A(5),
2112 
      O => A_5_IBUF
2113 
    );
2114 
  A_4_IBUF_60 : X_BUF
2115 
    port map (
2116 
      I => A(4),
2117 
      O => A_4_IBUF
2118 
    );
2119 
  A_3_IBUF_61 : X_BUF
2120 
    port map (
2121 
      I => A(3),
2122 
      O => A_3_IBUF
2123 
    );
2124 
  A_2_IBUF_62 : X_BUF
2125 
    port map (
2126 
      I => A(2),
2127 
      O => A_2_IBUF
2128 
    );
2129 
  A_1_IBUF_63 : X_BUF
2130 
    port map (
2131 
      I => A(1),
2132 
      O => A_1_IBUF
2133 
    );
2134 
  A_0_IBUF_64 : X_BUF
2135 
    port map (
2136 
      I => A(0),
2137 
      O => A_0_IBUF
2138 
    );
2139 
  B_63_IBUF_65 : X_BUF
2140 
    port map (
2141 
      I => B(63),
2142 
      O => B_63_IBUF
2143 
    );
2144 
  B_62_IBUF_66 : X_BUF
2145 
    port map (
2146 
      I => B(62),
2147 
      O => B_62_IBUF
2148 
    );
2149 
  B_61_IBUF_67 : X_BUF
2150 
    port map (
2151 
      I => B(61),
2152 
      O => B_61_IBUF
2153 
    );
2154 
  B_60_IBUF_68 : X_BUF
2155 
    port map (
2156 
      I => B(60),
2157 
      O => B_60_IBUF
2158 
    );
2159 
  B_59_IBUF_69 : X_BUF
2160 
    port map (
2161 
      I => B(59),
2162 
      O => B_59_IBUF
2163 
    );
2164 
  B_58_IBUF_70 : X_BUF
2165 
    port map (
2166 
      I => B(58),
2167 
      O => B_58_IBUF
2168 
    );
2169 
  B_57_IBUF_71 : X_BUF
2170 
    port map (
2171 
      I => B(57),
2172 
      O => B_57_IBUF
2173 
    );
2174 
  B_56_IBUF_72 : X_BUF
2175 
    port map (
2176 
      I => B(56),
2177 
      O => B_56_IBUF
2178 
    );
2179 
  B_55_IBUF_73 : X_BUF
2180 
    port map (
2181 
      I => B(55),
2182 
      O => B_55_IBUF
2183 
    );
2184 
  B_54_IBUF_74 : X_BUF
2185 
    port map (
2186 
      I => B(54),
2187 
      O => B_54_IBUF
2188 
    );
2189 
  B_53_IBUF_75 : X_BUF
2190 
    port map (
2191 
      I => B(53),
2192 
      O => B_53_IBUF
2193 
    );
2194 
  B_52_IBUF_76 : X_BUF
2195 
    port map (
2196 
      I => B(52),
2197 
      O => B_52_IBUF
2198 
    );
2199 
  B_51_IBUF_77 : X_BUF
2200 
    port map (
2201 
      I => B(51),
2202 
      O => B_51_IBUF
2203 
    );
2204 
  B_50_IBUF_78 : X_BUF
2205 
    port map (
2206 
      I => B(50),
2207 
      O => B_50_IBUF
2208 
    );
2209 
  B_49_IBUF_79 : X_BUF
2210 
    port map (
2211 
      I => B(49),
2212 
      O => B_49_IBUF
2213 
    );
2214 
  B_48_IBUF_80 : X_BUF
2215 
    port map (
2216 
      I => B(48),
2217 
      O => B_48_IBUF
2218 
    );
2219 
  B_47_IBUF_81 : X_BUF
2220 
    port map (
2221 
      I => B(47),
2222 
      O => B_47_IBUF
2223 
    );
2224 
  B_46_IBUF_82 : X_BUF
2225 
    port map (
2226 
      I => B(46),
2227 
      O => B_46_IBUF
2228 
    );
2229 
  B_45_IBUF_83 : X_BUF
2230 
    port map (
2231 
      I => B(45),
2232 
      O => B_45_IBUF
2233 
    );
2234 
  B_44_IBUF_84 : X_BUF
2235 
    port map (
2236 
      I => B(44),
2237 
      O => B_44_IBUF
2238 
    );
2239 
  B_43_IBUF_85 : X_BUF
2240 
    port map (
2241 
      I => B(43),
2242 
      O => B_43_IBUF
2243 
    );
2244 
  B_42_IBUF_86 : X_BUF
2245 
    port map (
2246 
      I => B(42),
2247 
      O => B_42_IBUF
2248 
    );
2249 
  B_41_IBUF_87 : X_BUF
2250 
    port map (
2251 
      I => B(41),
2252 
      O => B_41_IBUF
2253 
    );
2254 
  B_40_IBUF_88 : X_BUF
2255 
    port map (
2256 
      I => B(40),
2257 
      O => B_40_IBUF
2258 
    );
2259 
  B_39_IBUF_89 : X_BUF
2260 
    port map (
2261 
      I => B(39),
2262 
      O => B_39_IBUF
2263 
    );
2264 
  B_38_IBUF_90 : X_BUF
2265 
    port map (
2266 
      I => B(38),
2267 
      O => B_38_IBUF
2268 
    );
2269 
  B_37_IBUF_91 : X_BUF
2270 
    port map (
2271 
      I => B(37),
2272 
      O => B_37_IBUF
2273 
    );
2274 
  B_36_IBUF_92 : X_BUF
2275 
    port map (
2276 
      I => B(36),
2277 
      O => B_36_IBUF
2278 
    );
2279 
  B_35_IBUF_93 : X_BUF
2280 
    port map (
2281 
      I => B(35),
2282 
      O => B_35_IBUF
2283 
    );
2284 
  B_34_IBUF_94 : X_BUF
2285 
    port map (
2286 
      I => B(34),
2287 
      O => B_34_IBUF
2288 
    );
2289 
  B_33_IBUF_95 : X_BUF
2290 
    port map (
2291 
      I => B(33),
2292 
      O => B_33_IBUF
2293 
    );
2294 
  B_32_IBUF_96 : X_BUF
2295 
    port map (
2296 
      I => B(32),
2297 
      O => B_32_IBUF
2298 
    );
2299 
  B_31_IBUF_97 : X_BUF
2300 
    port map (
2301 
      I => B(31),
2302 
      O => B_31_IBUF
2303 
    );
2304 
  B_30_IBUF_98 : X_BUF
2305 
    port map (
2306 
      I => B(30),
2307 
      O => B_30_IBUF
2308 
    );
2309 
  B_29_IBUF_99 : X_BUF
2310 
    port map (
2311 
      I => B(29),
2312 
      O => B_29_IBUF
2313 
    );
2314 
  B_28_IBUF_100 : X_BUF
2315 
    port map (
2316 
      I => B(28),
2317 
      O => B_28_IBUF
2318 
    );
2319 
  B_27_IBUF_101 : X_BUF
2320 
    port map (
2321 
      I => B(27),
2322 
      O => B_27_IBUF
2323 
    );
2324 
  B_26_IBUF_102 : X_BUF
2325 
    port map (
2326 
      I => B(26),
2327 
      O => B_26_IBUF
2328 
    );
2329 
  B_25_IBUF_103 : X_BUF
2330 
    port map (
2331 
      I => B(25),
2332 
      O => B_25_IBUF
2333 
    );
2334 
  B_24_IBUF_104 : X_BUF
2335 
    port map (
2336 
      I => B(24),
2337 
      O => B_24_IBUF
2338 
    );
2339 
  B_23_IBUF_105 : X_BUF
2340 
    port map (
2341 
      I => B(23),
2342 
      O => B_23_IBUF
2343 
    );
2344 
  B_22_IBUF_106 : X_BUF
2345 
    port map (
2346 
      I => B(22),
2347 
      O => B_22_IBUF
2348 
    );
2349 
  B_21_IBUF_107 : X_BUF
2350 
    port map (
2351 
      I => B(21),
2352 
      O => B_21_IBUF
2353 
    );
2354 
  B_20_IBUF_108 : X_BUF
2355 
    port map (
2356 
      I => B(20),
2357 
      O => B_20_IBUF
2358 
    );
2359 
  B_19_IBUF_109 : X_BUF
2360 
    port map (
2361 
      I => B(19),
2362 
      O => B_19_IBUF
2363 
    );
2364 
  B_18_IBUF_110 : X_BUF
2365 
    port map (
2366 
      I => B(18),
2367 
      O => B_18_IBUF
2368 
    );
2369 
  B_17_IBUF_111 : X_BUF
2370 
    port map (
2371 
      I => B(17),
2372 
      O => B_17_IBUF
2373 
    );
2374 
  B_16_IBUF_112 : X_BUF
2375 
    port map (
2376 
      I => B(16),
2377 
      O => B_16_IBUF
2378 
    );
2379 
  B_15_IBUF_113 : X_BUF
2380 
    port map (
2381 
      I => B(15),
2382 
      O => B_15_IBUF
2383 
    );
2384 
  B_14_IBUF_114 : X_BUF
2385 
    port map (
2386 
      I => B(14),
2387 
      O => B_14_IBUF
2388 
    );
2389 
  B_13_IBUF_115 : X_BUF
2390 
    port map (
2391 
      I => B(13),
2392 
      O => B_13_IBUF
2393 
    );
2394 
  B_12_IBUF_116 : X_BUF
2395 
    port map (
2396 
      I => B(12),
2397 
      O => B_12_IBUF
2398 
    );
2399 
  B_11_IBUF_117 : X_BUF
2400 
    port map (
2401 
      I => B(11),
2402 
      O => B_11_IBUF
2403 
    );
2404 
  B_10_IBUF_118 : X_BUF
2405 
    port map (
2406 
      I => B(10),
2407 
      O => B_10_IBUF
2408 
    );
2409 
  B_9_IBUF_119 : X_BUF
2410 
    port map (
2411 
      I => B(9),
2412 
      O => B_9_IBUF
2413 
    );
2414 
  B_8_IBUF_120 : X_BUF
2415 
    port map (
2416 
      I => B(8),
2417 
      O => B_8_IBUF
2418 
    );
2419 
  B_7_IBUF_121 : X_BUF
2420 
    port map (
2421 
      I => B(7),
2422 
      O => B_7_IBUF
2423 
    );
2424 
  B_6_IBUF_122 : X_BUF
2425 
    port map (
2426 
      I => B(6),
2427 
      O => B_6_IBUF
2428 
    );
2429 
  B_5_IBUF_123 : X_BUF
2430 
    port map (
2431 
      I => B(5),
2432 
      O => B_5_IBUF
2433 
    );
2434 
  B_4_IBUF_124 : X_BUF
2435 
    port map (
2436 
      I => B(4),
2437 
      O => B_4_IBUF
2438 
    );
2439 
  B_3_IBUF_125 : X_BUF
2440 
    port map (
2441 
      I => B(3),
2442 
      O => B_3_IBUF
2443 
    );
2444 
  B_2_IBUF_126 : X_BUF
2445 
    port map (
2446 
      I => B(2),
2447 
      O => B_2_IBUF
2448 
    );
2449 
  B_1_IBUF_127 : X_BUF
2450 
    port map (
2451 
      I => B(1),
2452 
      O => B_1_IBUF
2453 
    );
2454 
  B_0_IBUF_128 : X_BUF
2455 
    port map (
2456 
      I => B(0),
2457 
      O => B_0_IBUF
2458 
    );
2459 
  C_63_OBUF_129 : X_BUF
2460 
    port map (
2461 
      I => C_63_OBUF,
2462 
      O => C_63_OBUF_GTS_TRI
2463 
    );
2464 
  C_62_OBUF_130 : X_BUF
2465 
    port map (
2466 
      I => C_62_OBUF,
2467 
      O => C_62_OBUF_GTS_TRI
2468 
    );
2469 
  C_61_OBUF_131 : X_BUF
2470 
    port map (
2471 
      I => C_61_OBUF,
2472 
      O => C_61_OBUF_GTS_TRI
2473 
    );
2474 
  C_60_OBUF_132 : X_BUF
2475 
    port map (
2476 
      I => C_60_OBUF,
2477 
      O => C_60_OBUF_GTS_TRI
2478 
    );
2479 
  C_59_OBUF_133 : X_BUF
2480 
    port map (
2481 
      I => C_59_OBUF,
2482 
      O => C_59_OBUF_GTS_TRI
2483 
    );
2484 
  C_58_OBUF_134 : X_BUF
2485 
    port map (
2486 
      I => C_58_OBUF,
2487 
      O => C_58_OBUF_GTS_TRI
2488 
    );
2489 
  C_57_OBUF_135 : X_BUF
2490 
    port map (
2491 
      I => C_57_OBUF,
2492 
      O => C_57_OBUF_GTS_TRI
2493 
    );
2494 
  C_56_OBUF_136 : X_BUF
2495 
    port map (
2496 
      I => C_56_OBUF,
2497 
      O => C_56_OBUF_GTS_TRI
2498 
    );
2499 
  C_55_OBUF_137 : X_BUF
2500 
    port map (
2501 
      I => C_55_OBUF,
2502 
      O => C_55_OBUF_GTS_TRI
2503 
    );
2504 
  C_54_OBUF_138 : X_BUF
2505 
    port map (
2506 
      I => C_54_OBUF,
2507 
      O => C_54_OBUF_GTS_TRI
2508 
    );
2509 
  C_53_OBUF_139 : X_BUF
2510 
    port map (
2511 
      I => C_53_OBUF,
2512 
      O => C_53_OBUF_GTS_TRI
2513 
    );
2514 
  C_52_OBUF_140 : X_BUF
2515 
    port map (
2516 
      I => C_52_OBUF,
2517 
      O => C_52_OBUF_GTS_TRI
2518 
    );
2519 
  C_51_OBUF_141 : X_BUF
2520 
    port map (
2521 
      I => C_51_OBUF,
2522 
      O => C_51_OBUF_GTS_TRI
2523 
    );
2524 
  C_50_OBUF_142 : X_BUF
2525 
    port map (
2526 
      I => C_50_OBUF,
2527 
      O => C_50_OBUF_GTS_TRI
2528 
    );
2529 
  C_49_OBUF_143 : X_BUF
2530 
    port map (
2531 
      I => C_49_OBUF,
2532 
      O => C_49_OBUF_GTS_TRI
2533 
    );
2534 
  C_48_OBUF_144 : X_BUF
2535 
    port map (
2536 
      I => C_48_OBUF,
2537 
      O => C_48_OBUF_GTS_TRI
2538 
    );
2539 
  C_47_OBUF_145 : X_BUF
2540 
    port map (
2541 
      I => C_47_OBUF,
2542 
      O => C_47_OBUF_GTS_TRI
2543 
    );
2544 
  C_46_OBUF_146 : X_BUF
2545 
    port map (
2546 
      I => C_46_OBUF,
2547 
      O => C_46_OBUF_GTS_TRI
2548 
    );
2549 
  C_45_OBUF_147 : X_BUF
2550 
    port map (
2551 
      I => C_45_OBUF,
2552 
      O => C_45_OBUF_GTS_TRI
2553 
    );
2554 
  C_44_OBUF_148 : X_BUF
2555 
    port map (
2556 
      I => C_44_OBUF,
2557 
      O => C_44_OBUF_GTS_TRI
2558 
    );
2559 
  C_43_OBUF_149 : X_BUF
2560 
    port map (
2561 
      I => C_43_OBUF,
2562 
      O => C_43_OBUF_GTS_TRI
2563 
    );
2564 
  C_42_OBUF_150 : X_BUF
2565 
    port map (
2566 
      I => C_42_OBUF,
2567 
      O => C_42_OBUF_GTS_TRI
2568 
    );
2569 
  C_41_OBUF_151 : X_BUF
2570 
    port map (
2571 
      I => C_41_OBUF,
2572 
      O => C_41_OBUF_GTS_TRI
2573 
    );
2574 
  C_40_OBUF_152 : X_BUF
2575 
    port map (
2576 
      I => C_40_OBUF,
2577 
      O => C_40_OBUF_GTS_TRI
2578 
    );
2579 
  C_39_OBUF_153 : X_BUF
2580 
    port map (
2581 
      I => C_39_OBUF,
2582 
      O => C_39_OBUF_GTS_TRI
2583 
    );
2584 
  C_38_OBUF_154 : X_BUF
2585 
    port map (
2586 
      I => C_38_OBUF,
2587 
      O => C_38_OBUF_GTS_TRI
2588 
    );
2589 
  C_37_OBUF_155 : X_BUF
2590 
    port map (
2591 
      I => C_37_OBUF,
2592 
      O => C_37_OBUF_GTS_TRI
2593 
    );
2594 
  C_36_OBUF_156 : X_BUF
2595 
    port map (
2596 
      I => C_36_OBUF,
2597 
      O => C_36_OBUF_GTS_TRI
2598 
    );
2599 
  C_35_OBUF_157 : X_BUF
2600 
    port map (
2601 
      I => C_35_OBUF,
2602 
      O => C_35_OBUF_GTS_TRI
2603 
    );
2604 
  C_34_OBUF_158 : X_BUF
2605 
    port map (
2606 
      I => C_34_OBUF,
2607 
      O => C_34_OBUF_GTS_TRI
2608 
    );
2609 
  C_33_OBUF_159 : X_BUF
2610 
    port map (
2611 
      I => C_33_OBUF,
2612 
      O => C_33_OBUF_GTS_TRI
2613 
    );
2614 
  C_32_OBUF_160 : X_BUF
2615 
    port map (
2616 
      I => C_32_OBUF,
2617 
      O => C_32_OBUF_GTS_TRI
2618 
    );
2619 
  C_31_OBUF_161 : X_BUF
2620 
    port map (
2621 
      I => C_31_OBUF,
2622 
      O => C_31_OBUF_GTS_TRI
2623 
    );
2624 
  C_30_OBUF_162 : X_BUF
2625 
    port map (
2626 
      I => C_30_OBUF,
2627 
      O => C_30_OBUF_GTS_TRI
2628 
    );
2629 
  C_29_OBUF_163 : X_BUF
2630 
    port map (
2631 
      I => C_29_OBUF,
2632 
      O => C_29_OBUF_GTS_TRI
2633 
    );
2634 
  C_28_OBUF_164 : X_BUF
2635 
    port map (
2636 
      I => C_28_OBUF,
2637 
      O => C_28_OBUF_GTS_TRI
2638 
    );
2639 
  C_27_OBUF_165 : X_BUF
2640 
    port map (
2641 
      I => C_27_OBUF,
2642 
      O => C_27_OBUF_GTS_TRI
2643 
    );
2644 
  C_26_OBUF_166 : X_BUF
2645 
    port map (
2646 
      I => C_26_OBUF,
2647 
      O => C_26_OBUF_GTS_TRI
2648 
    );
2649 
  C_25_OBUF_167 : X_BUF
2650 
    port map (
2651 
      I => C_25_OBUF,
2652 
      O => C_25_OBUF_GTS_TRI
2653 
    );
2654 
  C_24_OBUF_168 : X_BUF
2655 
    port map (
2656 
      I => C_24_OBUF,
2657 
      O => C_24_OBUF_GTS_TRI
2658 
    );
2659 
  C_23_OBUF_169 : X_BUF
2660 
    port map (
2661 
      I => C_23_OBUF,
2662 
      O => C_23_OBUF_GTS_TRI
2663 
    );
2664 
  C_22_OBUF_170 : X_BUF
2665 
    port map (
2666 
      I => C_22_OBUF,
2667 
      O => C_22_OBUF_GTS_TRI
2668 
    );
2669 
  C_21_OBUF_171 : X_BUF
2670 
    port map (
2671 
      I => C_21_OBUF,
2672 
      O => C_21_OBUF_GTS_TRI
2673 
    );
2674 
  C_20_OBUF_172 : X_BUF
2675 
    port map (
2676 
      I => C_20_OBUF,
2677 
      O => C_20_OBUF_GTS_TRI
2678 
    );
2679 
  C_19_OBUF_173 : X_BUF
2680 
    port map (
2681 
      I => C_19_OBUF,
2682 
      O => C_19_OBUF_GTS_TRI
2683 
    );
2684 
  C_18_OBUF_174 : X_BUF
2685 
    port map (
2686 
      I => C_18_OBUF,
2687 
      O => C_18_OBUF_GTS_TRI
2688 
    );
2689 
  C_17_OBUF_175 : X_BUF
2690 
    port map (
2691 
      I => C_17_OBUF,
2692 
      O => C_17_OBUF_GTS_TRI
2693 
    );
2694 
  C_16_OBUF_176 : X_BUF
2695 
    port map (
2696 
      I => C_16_OBUF,
2697 
      O => C_16_OBUF_GTS_TRI
2698 
    );
2699 
  C_15_OBUF_177 : X_BUF
2700 
    port map (
2701 
      I => C_15_OBUF,
2702 
      O => C_15_OBUF_GTS_TRI
2703 
    );
2704 
  C_14_OBUF_178 : X_BUF
2705 
    port map (
2706 
      I => C_14_OBUF,
2707 
      O => C_14_OBUF_GTS_TRI
2708 
    );
2709 
  C_13_OBUF_179 : X_BUF
2710 
    port map (
2711 
      I => C_13_OBUF,
2712 
      O => C_13_OBUF_GTS_TRI
2713 
    );
2714 
  C_12_OBUF_180 : X_BUF
2715 
    port map (
2716 
      I => C_12_OBUF,
2717 
      O => C_12_OBUF_GTS_TRI
2718 
    );
2719 
  C_11_OBUF_181 : X_BUF
2720 
    port map (
2721 
      I => C_11_OBUF,
2722 
      O => C_11_OBUF_GTS_TRI
2723 
    );
2724 
  C_10_OBUF_182 : X_BUF
2725 
    port map (
2726 
      I => C_10_OBUF,
2727 
      O => C_10_OBUF_GTS_TRI
2728 
    );
2729 
  C_9_OBUF_183 : X_BUF
2730 
    port map (
2731 
      I => C_9_OBUF,
2732 
      O => C_9_OBUF_GTS_TRI
2733 
    );
2734 
  C_8_OBUF_184 : X_BUF
2735 
    port map (
2736 
      I => C_8_OBUF,
2737 
      O => C_8_OBUF_GTS_TRI
2738 
    );
2739 
  C_7_OBUF_185 : X_BUF
2740 
    port map (
2741 
      I => C_7_OBUF,
2742 
      O => C_7_OBUF_GTS_TRI
2743 
    );
2744 
  C_6_OBUF_186 : X_BUF
2745 
    port map (
2746 
      I => C_6_OBUF,
2747 
      O => C_6_OBUF_GTS_TRI
2748 
    );
2749 
  C_5_OBUF_187 : X_BUF
2750 
    port map (
2751 
      I => C_5_OBUF,
2752 
      O => C_5_OBUF_GTS_TRI
2753 
    );
2754 
  C_4_OBUF_188 : X_BUF
2755 
    port map (
2756 
      I => C_4_OBUF,
2757 
      O => C_4_OBUF_GTS_TRI
2758 
    );
2759 
  C_3_OBUF_189 : X_BUF
2760 
    port map (
2761 
      I => C_3_OBUF,
2762 
      O => C_3_OBUF_GTS_TRI
2763 
    );
2764 
  C_2_OBUF_190 : X_BUF
2765 
    port map (
2766 
      I => C_2_OBUF,
2767 
      O => C_2_OBUF_GTS_TRI
2768 
    );
2769 
  C_1_OBUF_191 : X_BUF
2770 
    port map (
2771 
      I => C_1_OBUF,
2772 
      O => C_1_OBUF_GTS_TRI
2773 
    );
2774 
  C_0_OBUF_GTS_TRI_192 : X_TRI
2775 
    port map (
2776 
      I => C_0_OBUF_GTS_TRI,
2777 
      CTL => NlwInverterSignal_C_0_OBUF_GTS_TRI_CTL,
2778 
      O => C(0)
2779 
    );
2780 
  C_63_OBUF_GTS_TRI_193 : X_TRI
2781 
    port map (
2782 
      I => C_63_OBUF_GTS_TRI,
2783 
      CTL => NlwInverterSignal_C_63_OBUF_GTS_TRI_CTL,
2784 
      O => C(63)
2785 
    );
2786 
  C_62_OBUF_GTS_TRI_194 : X_TRI
2787 
    port map (
2788 
      I => C_62_OBUF_GTS_TRI,
2789 
      CTL => NlwInverterSignal_C_62_OBUF_GTS_TRI_CTL,
2790 
      O => C(62)
2791 
    );
2792 
  C_61_OBUF_GTS_TRI_195 : X_TRI
2793 
    port map (
2794 
      I => C_61_OBUF_GTS_TRI,
2795 
      CTL => NlwInverterSignal_C_61_OBUF_GTS_TRI_CTL,
2796 
      O => C(61)
2797 
    );
2798 
  C_60_OBUF_GTS_TRI_196 : X_TRI
2799 
    port map (
2800 
      I => C_60_OBUF_GTS_TRI,
2801 
      CTL => NlwInverterSignal_C_60_OBUF_GTS_TRI_CTL,
2802 
      O => C(60)
2803 
    );
2804 
  C_59_OBUF_GTS_TRI_197 : X_TRI
2805 
    port map (
2806 
      I => C_59_OBUF_GTS_TRI,
2807 
      CTL => NlwInverterSignal_C_59_OBUF_GTS_TRI_CTL,
2808 
      O => C(59)
2809 
    );
2810 
  C_58_OBUF_GTS_TRI_198 : X_TRI
2811 
    port map (
2812 
      I => C_58_OBUF_GTS_TRI,
2813 
      CTL => NlwInverterSignal_C_58_OBUF_GTS_TRI_CTL,
2814 
      O => C(58)
2815 
    );
2816 
  C_57_OBUF_GTS_TRI_199 : X_TRI
2817 
    port map (
2818 
      I => C_57_OBUF_GTS_TRI,
2819 
      CTL => NlwInverterSignal_C_57_OBUF_GTS_TRI_CTL,
2820 
      O => C(57)
2821 
    );
2822 
  C_56_OBUF_GTS_TRI_200 : X_TRI
2823 
    port map (
2824 
      I => C_56_OBUF_GTS_TRI,
2825 
      CTL => NlwInverterSignal_C_56_OBUF_GTS_TRI_CTL,
2826 
      O => C(56)
2827 
    );
2828 
  C_55_OBUF_GTS_TRI_201 : X_TRI
2829 
    port map (
2830 
      I => C_55_OBUF_GTS_TRI,
2831 
      CTL => NlwInverterSignal_C_55_OBUF_GTS_TRI_CTL,
2832 
      O => C(55)
2833 
    );
2834 
  C_54_OBUF_GTS_TRI_202 : X_TRI
2835 
    port map (
2836 
      I => C_54_OBUF_GTS_TRI,
2837 
      CTL => NlwInverterSignal_C_54_OBUF_GTS_TRI_CTL,
2838 
      O => C(54)
2839 
    );
2840 
  C_53_OBUF_GTS_TRI_203 : X_TRI
2841 
    port map (
2842 
      I => C_53_OBUF_GTS_TRI,
2843 
      CTL => NlwInverterSignal_C_53_OBUF_GTS_TRI_CTL,
2844 
      O => C(53)
2845 
    );
2846 
  C_52_OBUF_GTS_TRI_204 : X_TRI
2847 
    port map (
2848 
      I => C_52_OBUF_GTS_TRI,
2849 
      CTL => NlwInverterSignal_C_52_OBUF_GTS_TRI_CTL,
2850 
      O => C(52)
2851 
    );
2852 
  C_51_OBUF_GTS_TRI_205 : X_TRI
2853 
    port map (
2854 
      I => C_51_OBUF_GTS_TRI,
2855 
      CTL => NlwInverterSignal_C_51_OBUF_GTS_TRI_CTL,
2856 
      O => C(51)
2857 
    );
2858 
  C_50_OBUF_GTS_TRI_206 : X_TRI
2859 
    port map (
2860 
      I => C_50_OBUF_GTS_TRI,
2861 
      CTL => NlwInverterSignal_C_50_OBUF_GTS_TRI_CTL,
2862 
      O => C(50)
2863 
    );
2864 
  C_49_OBUF_GTS_TRI_207 : X_TRI
2865 
    port map (
2866 
      I => C_49_OBUF_GTS_TRI,
2867 
      CTL => NlwInverterSignal_C_49_OBUF_GTS_TRI_CTL,
2868 
      O => C(49)
2869 
    );
2870 
  C_48_OBUF_GTS_TRI_208 : X_TRI
2871 
    port map (
2872 
      I => C_48_OBUF_GTS_TRI,
2873 
      CTL => NlwInverterSignal_C_48_OBUF_GTS_TRI_CTL,
2874 
      O => C(48)
2875 
    );
2876 
  C_47_OBUF_GTS_TRI_209 : X_TRI
2877 
    port map (
2878 
      I => C_47_OBUF_GTS_TRI,
2879 
      CTL => NlwInverterSignal_C_47_OBUF_GTS_TRI_CTL,
2880 
      O => C(47)
2881 
    );
2882 
  C_46_OBUF_GTS_TRI_210 : X_TRI
2883 
    port map (
2884 
      I => C_46_OBUF_GTS_TRI,
2885 
      CTL => NlwInverterSignal_C_46_OBUF_GTS_TRI_CTL,
2886 
      O => C(46)
2887 
    );
2888 
  C_45_OBUF_GTS_TRI_211 : X_TRI
2889 
    port map (
2890 
      I => C_45_OBUF_GTS_TRI,
2891 
      CTL => NlwInverterSignal_C_45_OBUF_GTS_TRI_CTL,
2892 
      O => C(45)
2893 
    );
2894 
  C_44_OBUF_GTS_TRI_212 : X_TRI
2895 
    port map (
2896 
      I => C_44_OBUF_GTS_TRI,
2897 
      CTL => NlwInverterSignal_C_44_OBUF_GTS_TRI_CTL,
2898 
      O => C(44)
2899 
    );
2900 
  C_43_OBUF_GTS_TRI_213 : X_TRI
2901 
    port map (
2902 
      I => C_43_OBUF_GTS_TRI,
2903 
      CTL => NlwInverterSignal_C_43_OBUF_GTS_TRI_CTL,
2904 
      O => C(43)
2905 
    );
2906 
  C_42_OBUF_GTS_TRI_214 : X_TRI
2907 
    port map (
2908 
      I => C_42_OBUF_GTS_TRI,
2909 
      CTL => NlwInverterSignal_C_42_OBUF_GTS_TRI_CTL,
2910 
      O => C(42)
2911 
    );
2912 
  C_41_OBUF_GTS_TRI_215 : X_TRI
2913 
    port map (
2914 
      I => C_41_OBUF_GTS_TRI,
2915 
      CTL => NlwInverterSignal_C_41_OBUF_GTS_TRI_CTL,
2916 
      O => C(41)
2917 
    );
2918 
  C_40_OBUF_GTS_TRI_216 : X_TRI
2919 
    port map (
2920 
      I => C_40_OBUF_GTS_TRI,
2921 
      CTL => NlwInverterSignal_C_40_OBUF_GTS_TRI_CTL,
2922 
      O => C(40)
2923 
    );
2924 
  C_39_OBUF_GTS_TRI_217 : X_TRI
2925 
    port map (
2926 
      I => C_39_OBUF_GTS_TRI,
2927 
      CTL => NlwInverterSignal_C_39_OBUF_GTS_TRI_CTL,
2928 
      O => C(39)
2929 
    );
2930 
  C_38_OBUF_GTS_TRI_218 : X_TRI
2931 
    port map (
2932 
      I => C_38_OBUF_GTS_TRI,
2933 
      CTL => NlwInverterSignal_C_38_OBUF_GTS_TRI_CTL,
2934 
      O => C(38)
2935 
    );
2936 
  C_37_OBUF_GTS_TRI_219 : X_TRI
2937 
    port map (
2938 
      I => C_37_OBUF_GTS_TRI,
2939 
      CTL => NlwInverterSignal_C_37_OBUF_GTS_TRI_CTL,
2940 
      O => C(37)
2941 
    );
2942 
  C_36_OBUF_GTS_TRI_220 : X_TRI
2943 
    port map (
2944 
      I => C_36_OBUF_GTS_TRI,
2945 
      CTL => NlwInverterSignal_C_36_OBUF_GTS_TRI_CTL,
2946 
      O => C(36)
2947 
    );
2948 
  C_35_OBUF_GTS_TRI_221 : X_TRI
2949 
    port map (
2950 
      I => C_35_OBUF_GTS_TRI,
2951 
      CTL => NlwInverterSignal_C_35_OBUF_GTS_TRI_CTL,
2952 
      O => C(35)
2953 
    );
2954 
  C_34_OBUF_GTS_TRI_222 : X_TRI
2955 
    port map (
2956 
      I => C_34_OBUF_GTS_TRI,
2957 
      CTL => NlwInverterSignal_C_34_OBUF_GTS_TRI_CTL,
2958 
      O => C(34)
2959 
    );
2960 
  C_33_OBUF_GTS_TRI_223 : X_TRI
2961 
    port map (
2962 
      I => C_33_OBUF_GTS_TRI,
2963 
      CTL => NlwInverterSignal_C_33_OBUF_GTS_TRI_CTL,
2964 
      O => C(33)
2965 
    );
2966 
  C_32_OBUF_GTS_TRI_224 : X_TRI
2967 
    port map (
2968 
      I => C_32_OBUF_GTS_TRI,
2969 
      CTL => NlwInverterSignal_C_32_OBUF_GTS_TRI_CTL,
2970 
      O => C(32)
2971 
    );
2972 
  C_31_OBUF_GTS_TRI_225 : X_TRI
2973 
    port map (
2974 
      I => C_31_OBUF_GTS_TRI,
2975 
      CTL => NlwInverterSignal_C_31_OBUF_GTS_TRI_CTL,
2976 
      O => C(31)
2977 
    );
2978 
  C_30_OBUF_GTS_TRI_226 : X_TRI
2979 
    port map (
2980 
      I => C_30_OBUF_GTS_TRI,
2981 
      CTL => NlwInverterSignal_C_30_OBUF_GTS_TRI_CTL,
2982 
      O => C(30)
2983 
    );
2984 
  C_29_OBUF_GTS_TRI_227 : X_TRI
2985 
    port map (
2986 
      I => C_29_OBUF_GTS_TRI,
2987 
      CTL => NlwInverterSignal_C_29_OBUF_GTS_TRI_CTL,
2988 
      O => C(29)
2989 
    );
2990 
  C_28_OBUF_GTS_TRI_228 : X_TRI
2991 
    port map (
2992 
      I => C_28_OBUF_GTS_TRI,
2993 
      CTL => NlwInverterSignal_C_28_OBUF_GTS_TRI_CTL,
2994 
      O => C(28)
2995 
    );
2996 
  C_27_OBUF_GTS_TRI_229 : X_TRI
2997 
    port map (
2998 
      I => C_27_OBUF_GTS_TRI,
2999 
      CTL => NlwInverterSignal_C_27_OBUF_GTS_TRI_CTL,
3000 
      O => C(27)
3001 
    );
3002 
  C_26_OBUF_GTS_TRI_230 : X_TRI
3003 
    port map (
3004 
      I => C_26_OBUF_GTS_TRI,
3005 
      CTL => NlwInverterSignal_C_26_OBUF_GTS_TRI_CTL,
3006 
      O => C(26)
3007 
    );
3008 
  C_25_OBUF_GTS_TRI_231 : X_TRI
3009 
    port map (
3010 
      I => C_25_OBUF_GTS_TRI,
3011 
      CTL => NlwInverterSignal_C_25_OBUF_GTS_TRI_CTL,
3012 
      O => C(25)
3013 
    );
3014 
  C_24_OBUF_GTS_TRI_232 : X_TRI
3015 
    port map (
3016 
      I => C_24_OBUF_GTS_TRI,
3017 
      CTL => NlwInverterSignal_C_24_OBUF_GTS_TRI_CTL,
3018 
      O => C(24)
3019 
    );
3020 
  C_23_OBUF_GTS_TRI_233 : X_TRI
3021 
    port map (
3022 
      I => C_23_OBUF_GTS_TRI,
3023 
      CTL => NlwInverterSignal_C_23_OBUF_GTS_TRI_CTL,
3024 
      O => C(23)
3025 
    );
3026 
  C_22_OBUF_GTS_TRI_234 : X_TRI
3027 
    port map (
3028 
      I => C_22_OBUF_GTS_TRI,
3029 
      CTL => NlwInverterSignal_C_22_OBUF_GTS_TRI_CTL,
3030 
      O => C(22)
3031 
    );
3032 
  C_21_OBUF_GTS_TRI_235 : X_TRI
3033 
    port map (
3034 
      I => C_21_OBUF_GTS_TRI,
3035 
      CTL => NlwInverterSignal_C_21_OBUF_GTS_TRI_CTL,
3036 
      O => C(21)
3037 
    );
3038 
  C_20_OBUF_GTS_TRI_236 : X_TRI
3039 
    port map (
3040 
      I => C_20_OBUF_GTS_TRI,
3041 
      CTL => NlwInverterSignal_C_20_OBUF_GTS_TRI_CTL,
3042 
      O => C(20)
3043 
    );
3044 
  C_19_OBUF_GTS_TRI_237 : X_TRI
3045 
    port map (
3046 
      I => C_19_OBUF_GTS_TRI,
3047 
      CTL => NlwInverterSignal_C_19_OBUF_GTS_TRI_CTL,
3048 
      O => C(19)
3049 
    );
3050 
  C_18_OBUF_GTS_TRI_238 : X_TRI
3051 
    port map (
3052 
      I => C_18_OBUF_GTS_TRI,
3053 
      CTL => NlwInverterSignal_C_18_OBUF_GTS_TRI_CTL,
3054 
      O => C(18)
3055 
    );
3056 
  C_17_OBUF_GTS_TRI_239 : X_TRI
3057 
    port map (
3058 
      I => C_17_OBUF_GTS_TRI,
3059 
      CTL => NlwInverterSignal_C_17_OBUF_GTS_TRI_CTL,
3060 
      O => C(17)
3061 
    );
3062 
  C_16_OBUF_GTS_TRI_240 : X_TRI
3063 
    port map (
3064 
      I => C_16_OBUF_GTS_TRI,
3065 
      CTL => NlwInverterSignal_C_16_OBUF_GTS_TRI_CTL,
3066 
      O => C(16)
3067 
    );
3068 
  C_15_OBUF_GTS_TRI_241 : X_TRI
3069 
    port map (
3070 
      I => C_15_OBUF_GTS_TRI,
3071 
      CTL => NlwInverterSignal_C_15_OBUF_GTS_TRI_CTL,
3072 
      O => C(15)
3073 
    );
3074 
  C_14_OBUF_GTS_TRI_242 : X_TRI
3075 
    port map (
3076 
      I => C_14_OBUF_GTS_TRI,
3077 
      CTL => NlwInverterSignal_C_14_OBUF_GTS_TRI_CTL,
3078 
      O => C(14)
3079 
    );
3080 
  C_13_OBUF_GTS_TRI_243 : X_TRI
3081 
    port map (
3082 
      I => C_13_OBUF_GTS_TRI,
3083 
      CTL => NlwInverterSignal_C_13_OBUF_GTS_TRI_CTL,
3084 
      O => C(13)
3085 
    );
3086 
  C_12_OBUF_GTS_TRI_244 : X_TRI
3087 
    port map (
3088 
      I => C_12_OBUF_GTS_TRI,
3089 
      CTL => NlwInverterSignal_C_12_OBUF_GTS_TRI_CTL,
3090 
      O => C(12)
3091 
    );
3092 
  C_11_OBUF_GTS_TRI_245 : X_TRI
3093 
    port map (
3094 
      I => C_11_OBUF_GTS_TRI,
3095 
      CTL => NlwInverterSignal_C_11_OBUF_GTS_TRI_CTL,
3096 
      O => C(11)
3097 
    );
3098 
  C_10_OBUF_GTS_TRI_246 : X_TRI
3099 
    port map (
3100 
      I => C_10_OBUF_GTS_TRI,
3101 
      CTL => NlwInverterSignal_C_10_OBUF_GTS_TRI_CTL,
3102 
      O => C(10)
3103 
    );
3104 
  C_9_OBUF_GTS_TRI_247 : X_TRI
3105 
    port map (
3106 
      I => C_9_OBUF_GTS_TRI,
3107 
      CTL => NlwInverterSignal_C_9_OBUF_GTS_TRI_CTL,
3108 
      O => C(9)
3109 
    );
3110 
  C_8_OBUF_GTS_TRI_248 : X_TRI
3111 
    port map (
3112 
      I => C_8_OBUF_GTS_TRI,
3113 
      CTL => NlwInverterSignal_C_8_OBUF_GTS_TRI_CTL,
3114 
      O => C(8)
3115 
    );
3116 
  C_7_OBUF_GTS_TRI_249 : X_TRI
3117 
    port map (
3118 
      I => C_7_OBUF_GTS_TRI,
3119 
      CTL => NlwInverterSignal_C_7_OBUF_GTS_TRI_CTL,
3120 
      O => C(7)
3121 
    );
3122 
  C_6_OBUF_GTS_TRI_250 : X_TRI
3123 
    port map (
3124 
      I => C_6_OBUF_GTS_TRI,
3125 
      CTL => NlwInverterSignal_C_6_OBUF_GTS_TRI_CTL,
3126 
      O => C(6)
3127 
    );
3128 
  C_5_OBUF_GTS_TRI_251 : X_TRI
3129 
    port map (
3130 
      I => C_5_OBUF_GTS_TRI,
3131 
      CTL => NlwInverterSignal_C_5_OBUF_GTS_TRI_CTL,
3132 
      O => C(5)
3133 
    );
3134 
  C_4_OBUF_GTS_TRI_252 : X_TRI
3135 
    port map (
3136 
      I => C_4_OBUF_GTS_TRI,
3137 
      CTL => NlwInverterSignal_C_4_OBUF_GTS_TRI_CTL,
3138 
      O => C(4)
3139 
    );
3140 
  C_3_OBUF_GTS_TRI_253 : X_TRI
3141 
    port map (
3142 
      I => C_3_OBUF_GTS_TRI,
3143 
      CTL => NlwInverterSignal_C_3_OBUF_GTS_TRI_CTL,
3144 
      O => C(3)
3145 
    );
3146 
  C_2_OBUF_GTS_TRI_254 : X_TRI
3147 
    port map (
3148 
      I => C_2_OBUF_GTS_TRI,
3149 
      CTL => NlwInverterSignal_C_2_OBUF_GTS_TRI_CTL,
3150 
      O => C(2)
3151 
    );
3152 
  C_1_OBUF_GTS_TRI_255 : X_TRI
3153 
    port map (
3154 
      I => C_1_OBUF_GTS_TRI,
3155 
      CTL => NlwInverterSignal_C_1_OBUF_GTS_TRI_CTL,
3156 
      O => C(1)
3157 
    );
3158 
  NlwInverterBlock_C_0_OBUF_GTS_TRI_CTL : X_INV
3159 
    port map (
3160 
      I => GTS,
3161 
      O => NlwInverterSignal_C_0_OBUF_GTS_TRI_CTL
3162 
    );
3163 
  NlwInverterBlock_C_63_OBUF_GTS_TRI_CTL : X_INV
3164 
    port map (
3165 
      I => GTS,
3166 
      O => NlwInverterSignal_C_63_OBUF_GTS_TRI_CTL
3167 
    );
3168 
  NlwInverterBlock_C_62_OBUF_GTS_TRI_CTL : X_INV
3169 
    port map (
3170 
      I => GTS,
3171 
      O => NlwInverterSignal_C_62_OBUF_GTS_TRI_CTL
3172 
    );
3173 
  NlwInverterBlock_C_61_OBUF_GTS_TRI_CTL : X_INV
3174 
    port map (
3175 
      I => GTS,
3176 
      O => NlwInverterSignal_C_61_OBUF_GTS_TRI_CTL
3177 
    );
3178 
  NlwInverterBlock_C_60_OBUF_GTS_TRI_CTL : X_INV
3179 
    port map (
3180 
      I => GTS,
3181 
      O => NlwInverterSignal_C_60_OBUF_GTS_TRI_CTL
3182 
    );
3183 
  NlwInverterBlock_C_59_OBUF_GTS_TRI_CTL : X_INV
3184 
    port map (
3185 
      I => GTS,
3186 
      O => NlwInverterSignal_C_59_OBUF_GTS_TRI_CTL
3187 
    );
3188 
  NlwInverterBlock_C_58_OBUF_GTS_TRI_CTL : X_INV
3189 
    port map (
3190 
      I => GTS,
3191 
      O => NlwInverterSignal_C_58_OBUF_GTS_TRI_CTL
3192 
    );
3193 
  NlwInverterBlock_C_57_OBUF_GTS_TRI_CTL : X_INV
3194 
    port map (
3195 
      I => GTS,
3196 
      O => NlwInverterSignal_C_57_OBUF_GTS_TRI_CTL
3197 
    );
3198 
  NlwInverterBlock_C_56_OBUF_GTS_TRI_CTL : X_INV
3199 
    port map (
3200 
      I => GTS,
3201 
      O => NlwInverterSignal_C_56_OBUF_GTS_TRI_CTL
3202 
    );
3203 
  NlwInverterBlock_C_55_OBUF_GTS_TRI_CTL : X_INV
3204 
    port map (
3205 
      I => GTS,
3206 
      O => NlwInverterSignal_C_55_OBUF_GTS_TRI_CTL
3207 
    );
3208 
  NlwInverterBlock_C_54_OBUF_GTS_TRI_CTL : X_INV
3209 
    port map (
3210 
      I => GTS,
3211 
      O => NlwInverterSignal_C_54_OBUF_GTS_TRI_CTL
3212 
    );
3213 
  NlwInverterBlock_C_53_OBUF_GTS_TRI_CTL : X_INV
3214 
    port map (
3215 
      I => GTS,
3216 
      O => NlwInverterSignal_C_53_OBUF_GTS_TRI_CTL
3217 
    );
3218 
  NlwInverterBlock_C_52_OBUF_GTS_TRI_CTL : X_INV
3219 
    port map (
3220 
      I => GTS,
3221 
      O => NlwInverterSignal_C_52_OBUF_GTS_TRI_CTL
3222 
    );
3223 
  NlwInverterBlock_C_51_OBUF_GTS_TRI_CTL : X_INV
3224 
    port map (
3225 
      I => GTS,
3226 
      O => NlwInverterSignal_C_51_OBUF_GTS_TRI_CTL
3227 
    );
3228 
  NlwInverterBlock_C_50_OBUF_GTS_TRI_CTL : X_INV
3229 
    port map (
3230 
      I => GTS,
3231 
      O => NlwInverterSignal_C_50_OBUF_GTS_TRI_CTL
3232 
    );
3233 
  NlwInverterBlock_C_49_OBUF_GTS_TRI_CTL : X_INV
3234 
    port map (
3235 
      I => GTS,
3236 
      O => NlwInverterSignal_C_49_OBUF_GTS_TRI_CTL
3237 
    );
3238 
  NlwInverterBlock_C_48_OBUF_GTS_TRI_CTL : X_INV
3239 
    port map (
3240 
      I => GTS,
3241 
      O => NlwInverterSignal_C_48_OBUF_GTS_TRI_CTL
3242 
    );
3243 
  NlwInverterBlock_C_47_OBUF_GTS_TRI_CTL : X_INV
3244 
    port map (
3245 
      I => GTS,
3246 
      O => NlwInverterSignal_C_47_OBUF_GTS_TRI_CTL
3247 
    );
3248 
  NlwInverterBlock_C_46_OBUF_GTS_TRI_CTL : X_INV
3249 
    port map (
3250 
      I => GTS,
3251 
      O => NlwInverterSignal_C_46_OBUF_GTS_TRI_CTL
3252 
    );
3253 
  NlwInverterBlock_C_45_OBUF_GTS_TRI_CTL : X_INV
3254 
    port map (
3255 
      I => GTS,
3256 
      O => NlwInverterSignal_C_45_OBUF_GTS_TRI_CTL
3257 
    );
3258 
  NlwInverterBlock_C_44_OBUF_GTS_TRI_CTL : X_INV
3259 
    port map (
3260 
      I => GTS,
3261 
      O => NlwInverterSignal_C_44_OBUF_GTS_TRI_CTL
3262 
    );
3263 
  NlwInverterBlock_C_43_OBUF_GTS_TRI_CTL : X_INV
3264 
    port map (
3265 
      I => GTS,
3266 
      O => NlwInverterSignal_C_43_OBUF_GTS_TRI_CTL
3267 
    );
3268 
  NlwInverterBlock_C_42_OBUF_GTS_TRI_CTL : X_INV
3269 
    port map (
3270 
      I => GTS,
3271 
      O => NlwInverterSignal_C_42_OBUF_GTS_TRI_CTL
3272 
    );
3273 
  NlwInverterBlock_C_41_OBUF_GTS_TRI_CTL : X_INV
3274 
    port map (
3275 
      I => GTS,
3276 
      O => NlwInverterSignal_C_41_OBUF_GTS_TRI_CTL
3277 
    );
3278 
  NlwInverterBlock_C_40_OBUF_GTS_TRI_CTL : X_INV
3279 
    port map (
3280 
      I => GTS,
3281 
      O => NlwInverterSignal_C_40_OBUF_GTS_TRI_CTL
3282 
    );
3283 
  NlwInverterBlock_C_39_OBUF_GTS_TRI_CTL : X_INV
3284 
    port map (
3285 
      I => GTS,
3286 
      O => NlwInverterSignal_C_39_OBUF_GTS_TRI_CTL
3287 
    );
3288 
  NlwInverterBlock_C_38_OBUF_GTS_TRI_CTL : X_INV
3289 
    port map (
3290 
      I => GTS,
3291 
      O => NlwInverterSignal_C_38_OBUF_GTS_TRI_CTL
3292 
    );
3293 
  NlwInverterBlock_C_37_OBUF_GTS_TRI_CTL : X_INV
3294 
    port map (
3295 
      I => GTS,
3296 
      O => NlwInverterSignal_C_37_OBUF_GTS_TRI_CTL
3297 
    );
3298 
  NlwInverterBlock_C_36_OBUF_GTS_TRI_CTL : X_INV
3299 
    port map (
3300 
      I => GTS,
3301 
      O => NlwInverterSignal_C_36_OBUF_GTS_TRI_CTL
3302 
    );
3303 
  NlwInverterBlock_C_35_OBUF_GTS_TRI_CTL : X_INV
3304 
    port map (
3305 
      I => GTS,
3306 
      O => NlwInverterSignal_C_35_OBUF_GTS_TRI_CTL
3307 
    );
3308 
  NlwInverterBlock_C_34_OBUF_GTS_TRI_CTL : X_INV
3309 
    port map (
3310 
      I => GTS,
3311 
      O => NlwInverterSignal_C_34_OBUF_GTS_TRI_CTL
3312 
    );
3313 
  NlwInverterBlock_C_33_OBUF_GTS_TRI_CTL : X_INV
3314 
    port map (
3315 
      I => GTS,
3316 
      O => NlwInverterSignal_C_33_OBUF_GTS_TRI_CTL
3317 
    );
3318 
  NlwInverterBlock_C_32_OBUF_GTS_TRI_CTL : X_INV
3319 
    port map (
3320 
      I => GTS,
3321 
      O => NlwInverterSignal_C_32_OBUF_GTS_TRI_CTL
3322 
    );
3323 
  NlwInverterBlock_C_31_OBUF_GTS_TRI_CTL : X_INV
3324 
    port map (
3325 
      I => GTS,
3326 
      O => NlwInverterSignal_C_31_OBUF_GTS_TRI_CTL
3327 
    );
3328 
  NlwInverterBlock_C_30_OBUF_GTS_TRI_CTL : X_INV
3329 
    port map (
3330 
      I => GTS,
3331 
      O => NlwInverterSignal_C_30_OBUF_GTS_TRI_CTL
3332 
    );
3333 
  NlwInverterBlock_C_29_OBUF_GTS_TRI_CTL : X_INV
3334 
    port map (
3335 
      I => GTS,
3336 
      O => NlwInverterSignal_C_29_OBUF_GTS_TRI_CTL
3337 
    );
3338 
  NlwInverterBlock_C_28_OBUF_GTS_TRI_CTL : X_INV
3339 
    port map (
3340 
      I => GTS,
3341 
      O => NlwInverterSignal_C_28_OBUF_GTS_TRI_CTL
3342 
    );
3343 
  NlwInverterBlock_C_27_OBUF_GTS_TRI_CTL : X_INV
3344 
    port map (
3345 
      I => GTS,
3346 
      O => NlwInverterSignal_C_27_OBUF_GTS_TRI_CTL
3347 
    );
3348 
  NlwInverterBlock_C_26_OBUF_GTS_TRI_CTL : X_INV
3349 
    port map (
3350 
      I => GTS,
3351 
      O => NlwInverterSignal_C_26_OBUF_GTS_TRI_CTL
3352 
    );
3353 
  NlwInverterBlock_C_25_OBUF_GTS_TRI_CTL : X_INV
3354 
    port map (
3355 
      I => GTS,
3356 
      O => NlwInverterSignal_C_25_OBUF_GTS_TRI_CTL
3357 
    );
3358 
  NlwInverterBlock_C_24_OBUF_GTS_TRI_CTL : X_INV
3359 
    port map (
3360 
      I => GTS,
3361 
      O => NlwInverterSignal_C_24_OBUF_GTS_TRI_CTL
3362 
    );
3363 
  NlwInverterBlock_C_23_OBUF_GTS_TRI_CTL : X_INV
3364 
    port map (
3365 
      I => GTS,
3366 
      O => NlwInverterSignal_C_23_OBUF_GTS_TRI_CTL
3367 
    );
3368 
  NlwInverterBlock_C_22_OBUF_GTS_TRI_CTL : X_INV
3369 
    port map (
3370 
      I => GTS,
3371 
      O => NlwInverterSignal_C_22_OBUF_GTS_TRI_CTL
3372 
    );
3373 
  NlwInverterBlock_C_21_OBUF_GTS_TRI_CTL : X_INV
3374 
    port map (
3375 
      I => GTS,
3376 
      O => NlwInverterSignal_C_21_OBUF_GTS_TRI_CTL
3377 
    );
3378 
  NlwInverterBlock_C_20_OBUF_GTS_TRI_CTL : X_INV
3379 
    port map (
3380 
      I => GTS,
3381 
      O => NlwInverterSignal_C_20_OBUF_GTS_TRI_CTL
3382 
    );
3383 
  NlwInverterBlock_C_19_OBUF_GTS_TRI_CTL : X_INV
3384 
    port map (
3385 
      I => GTS,
3386 
      O => NlwInverterSignal_C_19_OBUF_GTS_TRI_CTL
3387 
    );
3388 
  NlwInverterBlock_C_18_OBUF_GTS_TRI_CTL : X_INV
3389 
    port map (
3390 
      I => GTS,
3391 
      O => NlwInverterSignal_C_18_OBUF_GTS_TRI_CTL
3392 
    );
3393 
  NlwInverterBlock_C_17_OBUF_GTS_TRI_CTL : X_INV
3394 
    port map (
3395 
      I => GTS,
3396 
      O => NlwInverterSignal_C_17_OBUF_GTS_TRI_CTL
3397 
    );
3398 
  NlwInverterBlock_C_16_OBUF_GTS_TRI_CTL : X_INV
3399 
    port map (
3400 
      I => GTS,
3401 
      O => NlwInverterSignal_C_16_OBUF_GTS_TRI_CTL
3402 
    );
3403 
  NlwInverterBlock_C_15_OBUF_GTS_TRI_CTL : X_INV
3404 
    port map (
3405 
      I => GTS,
3406 
      O => NlwInverterSignal_C_15_OBUF_GTS_TRI_CTL
3407 
    );
3408 
  NlwInverterBlock_C_14_OBUF_GTS_TRI_CTL : X_INV
3409 
    port map (
3410 
      I => GTS,
3411 
      O => NlwInverterSignal_C_14_OBUF_GTS_TRI_CTL
3412 
    );
3413 
  NlwInverterBlock_C_13_OBUF_GTS_TRI_CTL : X_INV
3414 
    port map (
3415 
      I => GTS,
3416 
      O => NlwInverterSignal_C_13_OBUF_GTS_TRI_CTL
3417 
    );
3418 
  NlwInverterBlock_C_12_OBUF_GTS_TRI_CTL : X_INV
3419 
    port map (
3420 
      I => GTS,
3421 
      O => NlwInverterSignal_C_12_OBUF_GTS_TRI_CTL
3422 
    );
3423 
  NlwInverterBlock_C_11_OBUF_GTS_TRI_CTL : X_INV
3424 
    port map (
3425 
      I => GTS,
3426 
      O => NlwInverterSignal_C_11_OBUF_GTS_TRI_CTL
3427 
    );
3428 
  NlwInverterBlock_C_10_OBUF_GTS_TRI_CTL : X_INV
3429 
    port map (
3430 
      I => GTS,
3431 
      O => NlwInverterSignal_C_10_OBUF_GTS_TRI_CTL
3432 
    );
3433 
  NlwInverterBlock_C_9_OBUF_GTS_TRI_CTL : X_INV
3434 
    port map (
3435 
      I => GTS,
3436 
      O => NlwInverterSignal_C_9_OBUF_GTS_TRI_CTL
3437 
    );
3438 
  NlwInverterBlock_C_8_OBUF_GTS_TRI_CTL : X_INV
3439 
    port map (
3440 
      I => GTS,
3441 
      O => NlwInverterSignal_C_8_OBUF_GTS_TRI_CTL
3442 
    );
3443 
  NlwInverterBlock_C_7_OBUF_GTS_TRI_CTL : X_INV
3444 
    port map (
3445 
      I => GTS,
3446 
      O => NlwInverterSignal_C_7_OBUF_GTS_TRI_CTL
3447 
    );
3448 
  NlwInverterBlock_C_6_OBUF_GTS_TRI_CTL : X_INV
3449 
    port map (
3450 
      I => GTS,
3451 
      O => NlwInverterSignal_C_6_OBUF_GTS_TRI_CTL
3452 
    );
3453 
  NlwInverterBlock_C_5_OBUF_GTS_TRI_CTL : X_INV
3454 
    port map (
3455 
      I => GTS,
3456 
      O => NlwInverterSignal_C_5_OBUF_GTS_TRI_CTL
3457 
    );
3458 
  NlwInverterBlock_C_4_OBUF_GTS_TRI_CTL : X_INV
3459 
    port map (
3460 
      I => GTS,
3461 
      O => NlwInverterSignal_C_4_OBUF_GTS_TRI_CTL
3462 
    );
3463 
  NlwInverterBlock_C_3_OBUF_GTS_TRI_CTL : X_INV
3464 
    port map (
3465 
      I => GTS,
3466 
      O => NlwInverterSignal_C_3_OBUF_GTS_TRI_CTL
3467 
    );
3468 
  NlwInverterBlock_C_2_OBUF_GTS_TRI_CTL : X_INV
3469 
    port map (
3470 
      I => GTS,
3471 
      O => NlwInverterSignal_C_2_OBUF_GTS_TRI_CTL
3472 
    );
3473 
  NlwInverterBlock_C_1_OBUF_GTS_TRI_CTL : X_INV
3474 
    port map (
3475 
      I => GTS,
3476 
      O => NlwInverterSignal_C_1_OBUF_GTS_TRI_CTL
3477 
    );
3478 
  NlwBlockTOC : X_TOC
3479 
    port map (O => GTS);
3480 
 
3481 
end Structure;
3482 
 

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