Subversion Repositories fluid_core_2

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2014-2015 Azmath Moosa                         ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 3 of the License, or (at your option) any     ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps

module tb_Reg_hist;

        // Inputs

        reg Clk;

        reg [0:2] nxt_reg_A;

        reg [0:2] nxt_reg_B;

        reg [0:2] nxt_dest;

        // Outputs

        wire [0:1] reg_src_A;

        wire [0:1] reg_src_B;

        // Instantiate the Unit Under Test (UUT)

        Reg_Hist uut (

                .Clk(Clk),

                .nxt_reg_A(nxt_reg_A),

                .nxt_reg_B(nxt_reg_B),

                .nxt_dest(nxt_dest),

                .reg_src_A(reg_src_A),

                .reg_src_B(reg_src_B)

        );

              initial begin

                // Initialize Inputs

                Clk = 1;

                nxt_reg_A = 0;

                nxt_reg_B = 0;

                nxt_dest = 0;

                // Wait 100 ns for global reset to finish

                #100;

                // Add stimulus here

        end

   always begin

        #50 Clk = ~Clk;

        end

        always begin

        #100 nxt_dest = 0;

        #100 nxt_dest = 1;

        #100 nxt_dest = 2;

                  nxt_reg_A = 1;

                  nxt_reg_B = 0;

        #100 nxt_dest = 3;

                  nxt_reg_A = 1;

                  nxt_reg_B = 2;

        end

endmodule