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[/] [fluid_core_2/] [trunk/] [bench/] [tb_Test_Bed.v] - Blame information for rev 3
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azmathmoos |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2014-2015 Azmath Moosa ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 3 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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module tb_Test_Bed;
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// Inputs
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reg Clk;
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reg RST;
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reg [0:3] Interrupt;
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// Instantiate the Unit Under Test (UUT)
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Test_Bed uut (
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.Clk(Clk),
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.RST(RST),
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.Interrupt(Interrupt)
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);
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initial begin
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// Initialize Inputs
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Clk = 0;
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RST = 1;
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Interrupt = 0;
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// Wait 100 ns for global reset to finish
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#60;
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RST = 0;
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// Add stimulus here
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end
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always begin
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#50 Clk = ~Clk;
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end
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// always begin
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// #3400 Interrupt[1] <= 1;
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// #100 Interrupt[1] <= 0;
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// end
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endmodule
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