Subversion Repositories fluid_core_2

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//// Copyright (C) 2014-2015 Azmath Moosa                         ////

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`timescale 1ns / 1ps

module tb_staller;

        // Inputs

        reg Clk;

        reg RST;

        reg Stall;

        // Outputs

        wire [0:3] stall_lines;

        // Instantiate the Unit Under Test (UUT)

        Staller uut (

                .Clk(Clk),

                .RST(RST),

                .Stall(Stall),

                .stall_lines(stall_lines)

        );

        initial begin

                // Initialize Inputs

                Clk = 0;

                RST = 1;

                Stall = 0;

                // Wait 100 ns for global reset to finish

                #5 RST = 0;

      #65 Stall = 1;

                #5 Stall = 0;

                // Add stimulus here

        end

        always begin

                #10 Clk = ~Clk;

        end

endmodule