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azmathmoos |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2014-2015 Azmath Moosa ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 3 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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`include "Configuration.v"
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module EX_Stage(
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input Clk,
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input RST,
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inout [0:3] stkFlag,
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input ret,
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input [0:`ID_EX_reg_w] ID_EX_reg,
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output [0:`EX_MEM_reg_w] EX_MEM_reg,
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input [0:`dpw] b_EX_MEM_reg, b_MEM_WB_reg
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);
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reg [0:`dpw] bb_MEM_WB_reg;
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wire [0:`type_msb] Type;
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wire [0:`wb_dst_msb] WB_Dest;
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wire [0:`bc_msb] Rd_BC;
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wire [0:`operation_msb] Operation;
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wire [0:`mod_sel_msb] Module;
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wire [0:`dpw] OP1, OP2, OP3, E0, E1;
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wire [0:3] Flag, aluFlag;
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reg [0:3] prev_Flag;
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wire [0:1] reg_src_A, reg_src_B, st_src;
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wire [0:2] load_hazard_abs;
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assign Type = ID_EX_reg[0:`type_msb];
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assign WB_Dest = ID_EX_reg[`type_msb+1:`type_msb+1+`wb_dst_msb];
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assign Module = ID_EX_reg[`type_msb+1+`wb_dst_msb+1:`type_msb+1+`wb_dst_msb+1+`mod_sel_msb];
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assign Operation = ID_EX_reg[`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1:`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb];
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assign Rd_BC = ID_EX_reg[`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1:`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb];
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assign OP1 = (reg_src_A[0] & load_hazard_abs[0]) | (reg_src_A[1] & ~load_hazard_abs[0]) ? b_MEM_WB_reg : (reg_src_A[0] & ~load_hazard_abs[0]) ? b_EX_MEM_reg : (reg_src_A[1] & load_hazard_abs[0]) ? bb_MEM_WB_reg : ID_EX_reg[`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+`dpw+`dpw+3:`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+`dpw+`dpw+3+`dpw];
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assign OP2 = (reg_src_B[0] & load_hazard_abs[1]) | (reg_src_B[1] & ~load_hazard_abs[1]) ? b_MEM_WB_reg : (reg_src_B[0] & ~load_hazard_abs[1]) ? b_EX_MEM_reg : (reg_src_B[1] & load_hazard_abs[1]) ? bb_MEM_WB_reg : ID_EX_reg[`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+`dpw+2:`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+`dpw+2+`dpw];
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// assign OP1 = reg_src_A[0] ? b_EX_MEM_reg : reg_src_A[1] ? load_hazard_abs[0] ? bb_MEM_WB_reg : b_MEM_WB_reg : ID_EX_reg[`type_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+`dpw+`dpw+3:`type_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+`dpw+`dpw+3+`dpw];
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// assign OP2 = reg_src_B[0] ? b_EX_MEM_reg : reg_src_B[1] ? load_hazard_abs[1] ? bb_MEM_WB_reg : b_MEM_WB_reg : ID_EX_reg[`type_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+`dpw+2:`type_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+`dpw+2+`dpw];
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assign reg_src_A = ID_EX_reg[`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+1+`dpw+`dpw+`dpw+3:`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+1+`dpw+`dpw+`dpw+4];
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assign reg_src_B = ID_EX_reg[`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+1+`dpw+`dpw+`dpw+5:`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+1+`dpw+`dpw+`dpw+6];
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assign st_src = ID_EX_reg[`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+1+`dpw+`dpw+`dpw+7:`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+1+`dpw+`dpw+`dpw+8];
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assign load_hazard_abs = ID_EX_reg[`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+1+`dpw+`dpw+`dpw+9:`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+1+`dpw+`dpw+`dpw+11];
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//----Sub Modules----//
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int_ALU int_ALU_inst(
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.Module(Module),
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.Operation(Operation),
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.OP1(OP1),
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.OP2(OP2),
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.Result(E1),
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.Flag(aluFlag),
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.prev_Flag(prev_Flag)
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);
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Shifter barrel_shifter_inst(
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.Module(Module),
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.Operation(Operation),
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.OP1(OP1),
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.OP2(OP2),
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.Result(E1)
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);
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assign Flag = ret ? stkFlag : aluFlag;
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assign stkFlag = ~ret ? Flag : 'bz;
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always@(posedge Clk) begin
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prev_Flag <= Flag;
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bb_MEM_WB_reg <= b_MEM_WB_reg; //store previous MEM_WB_reg coz we can't read it back from RF
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end
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assign E0 = (Type==`type_store) ? st_src[0] ? b_EX_MEM_reg : st_src[1] ? load_hazard_abs[2] ? bb_MEM_WB_reg : b_MEM_WB_reg : ID_EX_reg[`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+1:`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+1+`dpw] : (Type==`type_other) ? Flag : (Type==`type_branch) ? prev_Flag : 'bZ ;
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assign EX_MEM_reg = {Type,WB_Dest,Rd_BC,E0,E1};
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endmodule
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