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azmathmoos |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2014-2015 Azmath Moosa ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 3 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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`include "Configuration.v"
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module MEM_Stage(
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input Clk,
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input RST,
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input [0:`EX_MEM_reg_w] EX_MEM_reg,
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output [0:`MEM_WB_reg_w] MEM_WB_reg,
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output [0:`memory_bus_w] ex_mem_addr,
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inout [0:`dpw] ex_mem_data,
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output mem_Clk,
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output mem_wr,
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output branch, linked,
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output return_back,
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output [0:`pc_w] branch_target
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);
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wire [0:`type_msb] Type;
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wire [0:`wb_dst_msb] WB_Dest;
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wire [0:`bc_msb] Rd_BC;
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wire [0:`dpw] E1, E0, M0;
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wire C,Z,S,O;
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assign Type = EX_MEM_reg[0:`type_msb];
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assign WB_Dest = EX_MEM_reg[`type_msb+1:`type_msb+1+`wb_dst_msb];
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assign Rd_BC = EX_MEM_reg[`type_msb+1+`wb_dst_msb+1:`type_msb+1+`wb_dst_msb+1+`bc_msb];
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assign E0 = EX_MEM_reg[`type_msb+1+`wb_dst_msb+1+`bc_msb+1:`type_msb+1+`wb_dst_msb+1+`bc_msb+1+`dpw];
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assign E1 = EX_MEM_reg[`type_msb+1+`wb_dst_msb+1+`bc_msb+1+`dpw+1:`type_msb+1+`wb_dst_msb+1+`bc_msb+1+`dpw+1+`dpw];
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assign {C,Z,S,O} = E0[`dpw+1-4:`dpw];
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assign ex_mem_addr = E1;
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assign mem_wr = (Type==`type_store) ? 1: 0;
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assign ex_mem_data = (Type==`type_store) ? E0 : 'bZ;
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assign M0 = (Type==`type_load) ? ex_mem_data : E1;
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assign mem_Clk = ((Type==`type_load) || (Type==`type_store)) ? ~Clk : 'bZ;
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//--branch logic--//
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reg bc, ret;
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always@(*) begin
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if (Type==`type_branch) begin
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case (Rd_BC[1:`bc_msb])
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`bLT: bc <= S^O;
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`bLE: bc <= Z + (S^O);
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`bNEG: bc <= S;
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`bPOS: bc <= ~S;
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`bEQ: bc <= Z;
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`bNEQ: bc <= ~Z;
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`bGE: bc <= ~(S^O);
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`bGT: bc <= ~(Z+(S^O));
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`bLTU: bc <= C;
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`bLEU: bc <= C + Z;
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`bGTU: bc <= ~(C+Z);
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`bGEU: bc <= ~C;
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`bOVF: bc <= O;
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`bNOVF: bc <= ~O;
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`bALL: bc <= 1;
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`bRET: begin
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bc <= 1;
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ret <= 1;
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end
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endcase
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end else begin
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bc <= 0;
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ret <= 0;
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end
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end
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assign branch = (Type==`type_branch) & bc & ~ret;
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assign linked = Rd_BC[0];
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assign return_back = ret;
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assign branch_target = (Type==`type_branch) ? E1:'bZ;
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assign MEM_WB_reg = {Type,WB_Dest, Rd_BC[2:`bc_msb], M0};
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endmodule
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