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//////////////////////////////////////////////////////////////////////

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//// Copyright (C) 2014-2015 Azmath Moosa                         ////

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`timescale 1ns / 1ps

`include "Configuration.v"

module Reg_File(

        input Clk,

        input RST,

        input [0:`reg_sel_w] reg_a,

        input [0:`reg_sel_w] reg_b,

        input [0:`reg_sel_w] wb_reg,

        input [0: `dpw] word,

        output [0:`dpw] op_a,

        output [0:`dpw] op_b,

        input write

    );

//------------Register Array---------------//

        reg [0:`dpw] registers[0:`reg_n];

        //Init for Testing

        initial begin

        registers[0] <= 0;

        registers[1] <= 0;

        registers[2] <= 0;

        registers[3] <= 0;

        registers[4] <= 0;

        registers[5] <= 0;

        registers[6] <= 0;

        registers[7] <= 0;

        end

        //Write Back Stage

        always@(posedge Clk) begin                                                      //---The reg_a and word lines are ready before the edge, the rising edge of next cycle completes the write back---//

                if (write) begin//write

                        registers[wb_reg] <= word;

                end

        end

        //ID stage - Read

        assign op_a = registers[reg_a];

        assign op_b = registers[reg_b];

endmodule