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azmathmoos |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2014-2015 Azmath Moosa ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 3 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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`include "Configuration.v"
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module interrupt_unit(
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input Clk,
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input [0:`intr_msb] intr_req,
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input [0:log2(`intr_msb)] intr_inx,
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input [0:`pc_w] new_vector,
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input write, return_back,
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output intr,
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output [0:`pc_w] vector
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);
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reg [0:`pc_w] isr_vectors [0:`intr_msb+1];
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reg [0:`intr_msb] masks;
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reg temp_unblock;
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reg [0:log2(`intr_msb)-1] vctr_inx;
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integer i;
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always@(*) begin
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for ( i = `intr_msb; (i >= 0); i = i - 1) begin
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if (intr_req[i] == 1) begin
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vctr_inx <= i;
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end
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end
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end
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initial begin
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temp_unblock <= 1;
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end
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assign intr = |(masks & intr_req ) & temp_unblock; //(~(vctr_inx == 0)&&(masks[vctr_inx]));
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assign vector = intr ? isr_vectors[vctr_inx]:'bz;
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always@(posedge Clk) begin
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if (write) begin//write
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if (intr_inx == 0) masks <= new_vector; //(aligned by MSB)
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else begin
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isr_vectors[intr_inx] <= new_vector;
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end
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end
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if (intr) temp_unblock <= 0;
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else if (return_back) temp_unblock <= 1;
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end
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//--- Constant Function ----//
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function integer log2;
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input integer value;
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begin
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value = value-1;
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for (log2=0; value>0; log2=log2+1)
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value = value>>1;
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end
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endfunction
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endmodule
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