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[/] [fluid_core_2/] [trunk/] [xilinx14.5 project/] [Configuration.v] - Blame information for rev 4

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`timescale 1ns / 1ps
/*----------NOTES---------------/
        1. All numerical values are counted from 0
 
*/
 
`ifndef dpw
//----Processor Interface------//
`define dpw 31                          // -- Datapath Width -- //
`define inst_w 15                       // -- Instruction Width -- //
`define pc_w 5                          // -- Program Counter Width i.e. Instruction Memory Space -- //
`define memory_bus_w 3  // -- Memory Bus Width i.e. Data Memory Space -- //
`define intr_msb 3              // -- Interrupt Bus i.e. No. of Ext Interrupts to support -- //
 
 
`define reg_n 7                 // -- Number of Registers -- //
`define reg_sel_w 2             // -- Register Address Width -- //
 
//------ISA Specifics----------//
`define uop_vector_msb 4
`define uop_msb 12                      // -- Type|WB_Destination|ADM|Module_Sel|Operation -- [2|2|4|2|3] -- //
`define uop_n 25
`define type_msb 1
`define wb_dst_msb 1
`define mod_sel_msb 1
`define operation_msb 2
`define bc_msb 4
 
 
 
 
        //-----Pipeline Registers-----//
`define IF_ID_reg_w `inst_w
`define ID_EX_reg_w `type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+1+`dpw+`dpw+`dpw+2+6+3 //55 //Type + Mod_Sel + Operation + reg_sel_w + (dpw x 3) + (2 bit reg_src x 3) + (3 bit load_hazard_a/b/s)
`define EX_MEM_reg_w `type_msb+1+`wb_dst_msb+1+`bc_msb+1+`dpw+`dpw+1
`define MEM_WB_reg_w `type_msb+1+`wb_dst_msb+1+`reg_sel_w+1+`dpw
 
/********************************************************************************
//---------------------------------MicroOp Store-------------------------------//
********************************************************************************/
 
        //------Module Identifiers-------//
        `define int_ALU 2'b01
        `define barrel_Shifter 2'b10
 
        //------Empty Instructions----//
        `define none 2'b00
        `define op_none 3'b000
 
        //---ALU Operations---//
        `define ADD     3'b001
        `define SUB     3'b010
        `define ADC     3'b011
        `define SBC     3'b100
        `define AND     3'b101
        `define OR              3'b110
        `define XOR     3'b111
 
        //---Branch Conditions---//
        `define bLT 4'd1
        `define bLE 4'd2
 
        `define bEQ 4'd3
        `define bZ 4'd3
        `define bNEQ 4'd4
        `define bNZ 4'd4
 
        `define bGE 4'd5
        `define bGT 4'd6
 
        `define bLTU 4'd7
        `define bCRY 4'd7
 
        `define bLEU 4'd8
 
        `define bGEU 4'd9
        `define bNCRY 4'd9
 
        `define bGTU 4'd10
        `define bNEG 4'd11
        `define bPOS 4'd12
 
        `define bOVF 4'd13
        `define bNOVF 4'd14
 
        `define bALL 4'd0
 
        `define bRET 5'd15
 
        `define lnk 1'b1
        `define ulnk 1'b0
 
        //----Declarations for easing readability of Micro_Ops------//
        `define type_other 2'b00
        `define type_load 2'b01
        `define type_store 2'b10
        `define type_branch 2'b11 //never make this 00, conflict in reg_history
 
        //----S0,S1,S2,Imm---//
        `define RRR 4'b0111
        `define RRI 4'b0100
        `define RI  4'b0001
        `define sRR 4'b1100
        `define sRI 4'b1001
 
        //---- Write Back Destination ----//
        `define wb_rf 2'b00
        `define wb_uop 2'b01
        `define wb_int  2'b10
        `define wb_none 2'b11
 
        // ---- Constant Functions ---- //
 
`endif

Line No.	Rev	Author	Line
1	4	azmathmoos	`timescale 1ns / 1ps
2			`/*----------NOTES---------------/`
3			`1. All numerical values are counted from 0`
4
5			`*/`
6
7			`ifndef dpw
8			`//----Processor Interface------//`
9			`define dpw 31 // -- Datapath Width -- //
10			`define inst_w 15 // -- Instruction Width -- //
11			`define pc_w 5 // -- Program Counter Width i.e. Instruction Memory Space -- //
12			`define memory_bus_w 3 // -- Memory Bus Width i.e. Data Memory Space -- //
13			`define intr_msb 3 // -- Interrupt Bus i.e. No. of Ext Interrupts to support -- //
14
15
16			`define reg_n 7 // -- Number of Registers -- //
17			`define reg_sel_w 2 // -- Register Address Width -- //
18
19			`//------ISA Specifics----------//`
20			`define uop_vector_msb 4
21			`define uop_msb 12 // -- Type\|WB_Destination\|ADM\|Module_Sel\|Operation -- [2\|2\|4\|2\|3] -- //
22			`define uop_n 25
23			`define type_msb 1
24			`define wb_dst_msb 1
25			`define mod_sel_msb 1
26			`define operation_msb 2
27			`define bc_msb 4
28
29
30
31
32			`//-----Pipeline Registers-----//`
33			`define IF_ID_reg_w `inst_w
34			`define ID_EX_reg_w `type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+1+`dpw+`dpw+`dpw+2+6+3 //55 //Type + Mod_Sel + Operation + reg_sel_w + (dpw x 3) + (2 bit reg_src x 3) + (3 bit load_hazard_a/b/s)
35			`define EX_MEM_reg_w `type_msb+1+`wb_dst_msb+1+`bc_msb+1+`dpw+`dpw+1
36			`define MEM_WB_reg_w `type_msb+1+`wb_dst_msb+1+`reg_sel_w+1+`dpw
37
38			`/********************************************************************************`
39			`//---------------------------------MicroOp Store-------------------------------//`
40			`********************************************************************************/`
41
42			`//------Module Identifiers-------//`
43			`define int_ALU 2'b01
44			`define barrel_Shifter 2'b10
45
46			`//------Empty Instructions----//`
47			`define none 2'b00
48			`define op_none 3'b000
49
50			`//---ALU Operations---//`
51			`define ADD 3'b001
52			`define SUB 3'b010
53			`define ADC 3'b011
54			`define SBC 3'b100
55			`define AND 3'b101
56			`define OR 3'b110
57			`define XOR 3'b111
58
59			`//---Branch Conditions---//`
60			`define bLT 4'd1
61			`define bLE 4'd2
62
63			`define bEQ 4'd3
64			`define bZ 4'd3
65			`define bNEQ 4'd4
66			`define bNZ 4'd4
67
68			`define bGE 4'd5
69			`define bGT 4'd6
70
71			`define bLTU 4'd7
72			`define bCRY 4'd7
73
74			`define bLEU 4'd8
75
76			`define bGEU 4'd9
77			`define bNCRY 4'd9
78
79			`define bGTU 4'd10
80			`define bNEG 4'd11
81			`define bPOS 4'd12
82
83			`define bOVF 4'd13
84			`define bNOVF 4'd14
85
86			`define bALL 4'd0
87
88			`define bRET 5'd15
89
90			`define lnk 1'b1
91			`define ulnk 1'b0
92
93			`//----Declarations for easing readability of Micro_Ops------//`
94			`define type_other 2'b00
95			`define type_load 2'b01
96			`define type_store 2'b10
97			`define type_branch 2'b11 //never make this 00, conflict in reg_history
98
99			`//----S0,S1,S2,Imm---//`
100			`define RRR 4'b0111
101			`define RRI 4'b0100
102			`define RI 4'b0001
103			`define sRR 4'b1100
104			`define sRI 4'b1001
105
106			`//---- Write Back Destination ----//`
107			`define wb_rf 2'b00
108			`define wb_uop 2'b01
109			`define wb_int 2'b10
110			`define wb_none 2'b11
111
112			`// ---- Constant Functions ---- //`
113
114			`endif

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[/] [fluid_core_2/] [trunk/] [xilinx14.5 project/] [Configuration.v] - Blame information for rev 4