Subversion Repositories fluid_core_2

Release 14.5 par P.58f (nt)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

AZMATH-PC::  Mon Apr 27 23:01:54 2015

par -w -intstyle ise -pl high -rl high -xe n -t 1 FluidCore_map.ncd

FluidCore.ncd FluidCore.pcf

Constraints file: FluidCore.pcf.

Loading device for application Rf_Device from file '3s500e.nph' in environment C:\Xilinx\14.5\ISE_DS\ISE\.

   "FluidCore" is an NCD, version 3.2, device xc3s500e, package fg320, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)

Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)

INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par

   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all

   internal clocks in this design. Because there are not defined timing requirements, a timing score will not be

   reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.

   Note: For the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high".

Device speed data version:  "PRODUCTION 1.27 2013-03-26".

Design Summary Report:

 Number of External IOBs                          65 out of 232    28%

   Number of External Input IOBs                 21

      Number of External Input IBUFs             21

   Number of External Output IOBs                12

      Number of External Output IOBs             12

   Number of External Bidir IOBs                 32

      Number of External Bidir IOBs              32

   Number of BUFGMUXs                        4 out of 24     16%

   Number of Slices                       1064 out of 4656   22%

      Number of SLICEMs                      6 out of 2328    1%

Overall effort level (-ol):   Not applicable because -pl and -rl switches are used

Router effort level (-rl):    High

Starting initial Timing Analysis.  REAL time: 5 secs

Finished initial Timing Analysis.  REAL time: 5 secs

Starting Router

Phase  1  : 6927 unrouted;      REAL time: 10 secs

Phase  2  : 6209 unrouted;      REAL time: 10 secs

Phase  3  : 1771 unrouted;      REAL time: 11 secs

Phase  4  : 1843 unrouted; (Par is working to improve performance)     REAL time: 13 secs

Phase  5  : 0 unrouted; (Par is working to improve performance)     REAL time: 14 secs

Updating file: FluidCore.ncd with current fully routed design.

Phase  6  : 0 unrouted; (Par is working to improve performance)     REAL time: 15 secs

Phase  7  : 0 unrouted; (Par is working to improve performance)     REAL time: 43 secs

Phase  8  : 0 unrouted; (Par is working to improve performance)     REAL time: 44 secs

Phase  9  : 0 unrouted; (Par is working to improve performance)     REAL time: 44 secs

Phase 10  : 0 unrouted; (Par is working to improve performance)     REAL time: 44 secs

Phase 11  : 0 unrouted; (Par is working to improve performance)     REAL time: 44 secs

Phase 12  : 0 unrouted; (Par is working to improve performance)     REAL time: 45 secs

Total REAL time to Router completion: 45 secs

Total CPU time to Router completion: 44 secs

Partition Implementation Status

-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************

Generating Clock Report

**************************

+---------------------+--------------+------+------+------------+-------------+

|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|

+---------------------+--------------+------+------+------------+-------------+

|ID_EX_reg/pipeline_r |              |      |      |            |             |

|          egister<5> | BUFGMUX_X2Y11| No   |   36 |  0.036     |  0.166      |

+---------------------+--------------+------+------+------------+-------------+

|            Clk_IBUF |  BUFGMUX_X1Y0| No   |  386 |  0.085     |  0.203      |

+---------------------+--------------+------+------+------------+-------------+

|  EX_MEM_reg/Clk_RST | BUFGMUX_X1Y10| No   |  263 |  0.083     |  0.200      |

+---------------------+--------------+------+------+------------+-------------+

|    Interrupt_3_IBUF | BUFGMUX_X2Y10| No   |    2 |  0.002     |  0.145      |

+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing

only delays for the net. Note this is different from Clock Skew which

is reported in TRCE timing report. Clock Skew is the difference between

the minimum and maximum path delays which includes logic delays.

* The fanout is the number of component pins not the individual BEL loads,

for example SLICE loads not FF loads.

Timing Score: 0 (Setup: 0, Hold: 0)

Asterisk (*) preceding a constraint indicates it was not met.

   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------

  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing

                                            |             |    Slack   | Achievable | Errors |    Score

----------------------------------------------------------------------------------------------------------

  Autotimespec constraint for clock net ID_ | SETUP       |         N/A|     4.865ns|     N/A|           0

  EX_reg/pipeline_register<5>               | HOLD        |     1.489ns|            |       0|           0

----------------------------------------------------------------------------------------------------------

  Autotimespec constraint for clock net Clk | SETUP       |         N/A|     6.237ns|     N/A|           0

  _IBUF                                     | HOLD        |     1.729ns|            |       0|           0

----------------------------------------------------------------------------------------------------------

  Autotimespec constraint for clock net EX_ | SETUP       |         N/A|     6.937ns|     N/A|           0

  MEM_reg/Clk_RST                           | HOLD        |     1.025ns|            |       0|           0

----------------------------------------------------------------------------------------------------------

All constraints were met.

INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the

   constraint is not analyzed due to the following: No paths covered by this

   constraint; Other constraints intersect with this constraint; or This

   constraint was disabled by a Path Tracing Control. Please run the Timespec

   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 46 secs

Total CPU time to PAR completion: 45 secs

Peak Memory Usage:  260 MB

Placer: Placement generated during map.

Routing: Completed - No errors found.

Number of error messages: 0

Number of warning messages: 0

Number of info messages: 1

Writing design to file FluidCore.ncd

PAR done!