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[/] [fluid_core_2/] [trunk/] [xilinx14.5 project/] [ID_Stage.v] - Blame information for rev 4

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1 4 azmathmoos
`timescale 1ns / 1ps
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`include "Configuration.v"
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module ID_Stage(
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        input [0:`IF_ID_reg_w] IF_ID_reg,
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        input Clk,
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        input RST,
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        output [0:`reg_sel_w] RF_a,
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        output [0:`reg_sel_w] RF_b,
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        input [0:`dpw] RF_op_a,
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        input [0:`dpw] RF_op_b,
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        output [0:`ID_EX_reg_w] ID_EX_reg,
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        //---op forwarding pins---//
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        //output [0:`type_msb] curr_type,
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        input [0:1] reg_src_A, reg_src_B, st_src,
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        input [0:2] load_hazard_abs,
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        output rrr_adm, rri_adm, not_branch,
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        output [0:`uop_vector_msb] uop_vector,
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        input [0:`uop_msb] uop
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    );
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//-----------------------MicroOperation--------------------------//
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//      wire [0:`uop_vector_msb] uop_vector;
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//      wire [0:`uop_msb] uop;
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        assign uop_vector = IF_ID_reg[0:`uop_vector_msb];
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        wire [0:3] adm;
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        wire [0:`type_msb] Type;
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        wire [0:`wb_dst_msb] WB_Dest;
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        wire [0:`mod_sel_msb] Mod_Sel;
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        wire [0:`operation_msb] Operation;
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        wire bS0, bS1, bS2, bImm;
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        assign Type = uop[0:`type_msb];
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        assign WB_Dest = uop[`type_msb+1:`type_msb+1+`wb_dst_msb];
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        assign adm = uop[`type_msb+1+`wb_dst_msb+1:`type_msb+1+`wb_dst_msb+4];
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        assign bS0 = uop[`type_msb+1+`wb_dst_msb+1];
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        assign bS1 = uop[`type_msb+1+`wb_dst_msb+2];
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        assign bS2 = uop[`type_msb+1+`wb_dst_msb+3];
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        assign bImm = uop[`type_msb+1+`wb_dst_msb+4];
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        assign Mod_Sel = uop[`type_msb+1+`wb_dst_msb+5:`type_msb+1+`wb_dst_msb+5+`mod_sel_msb];
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        assign Operation = uop[`type_msb+1+`wb_dst_msb+5+`mod_sel_msb+1:`type_msb+1+`wb_dst_msb+5+`mod_sel_msb+1+`operation_msb];
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//------------fetch operands------------------//
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        wire [0:`inst_w-`uop_vector_msb-1] raw_operands;
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        assign raw_operands = IF_ID_reg[`uop_vector_msb+1:`inst_w];
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        wire [0:`dpw] S0, S1, S2, Imm;
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        reg [0:`dpw] buff_op_a, buff_op_b;
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        wire [0:`bc_msb] Rd_BC;
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        assign Rd_BC = raw_operands[0:`bc_msb];
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        //update RF_a in negative half of cycle -- no need for that wrong comment!
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        assign RF_a = bS0 ? Rd_BC[1:`bc_msb] : bS2 ? raw_operands[`bc_msb+1+`reg_sel_w+1:`bc_msb+1+`reg_sel_w+1+`reg_sel_w]:0 ;
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        assign S0 = bS0 ? buff_op_a : 0;
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        assign RF_b = bS1 ? raw_operands[`bc_msb+1:`bc_msb+1+`reg_sel_w]:0;
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        assign S1 = bS1 ? buff_op_b : 0;
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        assign Imm = bImm ? raw_operands[`bc_msb+1:`inst_w-`uop_vector_msb-1]:raw_operands[`bc_msb+1+`reg_sel_w+1:`inst_w-`uop_vector_msb-1];
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        assign S2 = bS2 ? buff_op_a : Imm;
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        //latch on to reg file in the negative half
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        always@(*) begin
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                if (~Clk) begin
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                        buff_op_a <= RF_op_a;
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                        buff_op_b <= RF_op_b;
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                end
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        end
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//----Operand Forwarding----//
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        assign not_branch = (|(Type ^ `type_branch));
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        assign rrr_adm = (adm == `RRR);//(~(|(adm ^ `RRR)));
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        assign rri_adm = (adm == `RRI);
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//-----next stage----//
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        assign ID_EX_reg = {Type,WB_Dest,Mod_Sel,Operation,Rd_BC,S0,S1,S2,reg_src_A,reg_src_B,st_src,load_hazard_abs};//
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endmodule

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