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azmathmoos |
Release 14.5 - xst P.58f (nt)
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Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.08 secs
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--> Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.08 secs
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--> Reading design: Shifter.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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9.1) Device utilization summary
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9.2) Partition Resource Summary
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9.3) TIMING REPORT
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "Shifter.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "Shifter"
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Output Format : NGC
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Target Device : xc3s500e-4-fg320
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---- Source Options
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Top Module Name : Shifter
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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Safe Implementation : No
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FSM Style : LUT
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RAM Extraction : Yes
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RAM Style : Auto
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ROM Extraction : Yes
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Mux Style : Auto
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Decoder Extraction : YES
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Priority Encoder Extraction : Yes
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Shift Register Extraction : YES
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Logical Shifter Extraction : YES
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XOR Collapsing : YES
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ROM Style : Auto
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Mux Extraction : Yes
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Resource Sharing : YES
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Asynchronous To Synchronous : NO
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Multiplier Style : LUT
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Automatic Register Balancing : Yes
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---- Target Options
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Add IO Buffers : YES
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Global Maximum Fanout : 100000
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Add Generic Clock Buffer(BUFG) : 24
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Register Duplication : YES
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Move First FlipFlop Stage : YES
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Move Last FlipFlop Stage : YES
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Slice Packing : YES
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Optimize Instantiated Primitives : NO
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Use Clock Enable : Yes
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Use Synchronous Set : Yes
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Use Synchronous Reset : Yes
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Pack IO Registers into IOBs : True
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 2
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Keep Hierarchy : No
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Netlist Hierarchy : As_Optimized
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RTL Output : Yes
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Global Optimization : AllClockNets
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Read Cores : YES
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Write Timing Constraints : NO
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Cross Clock Analysis : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : Maintain
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Slice Utilization Ratio : 100
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BRAM Utilization Ratio : 100
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Verilog 2001 : YES
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Auto BRAM Packing : NO
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Slice Utilization Ratio Delta : 5
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling verilog file "Shifter.v" in library work
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Compiling verilog include file "Configuration.v"
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Module compiled
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No errors in compilation
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Analysis of file <"Shifter.prj"> succeeded.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for module in library .
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing top module .
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Module is correct for synthesis.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Performing bidirectional port resolution...
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Synthesizing Unit .
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Related source file is "Shifter.v".
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WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:737 - Found 32-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
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Found 32-bit shifter logical left for signal created at line 15.
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Found 32-bit shifter logical right for signal created at line 16.
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Summary:
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inferred 2 Combinational logic shifter(s).
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Unit synthesized.
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=========================================================================
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HDL Synthesis Report
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Macro Statistics
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# Latches : 1
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32-bit latch : 1
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# Logic shifters : 2
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32-bit shifter logical left : 1
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32-bit shifter logical right : 1
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=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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=========================================================================
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=========================================================================
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Advanced HDL Synthesis Report
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Macro Statistics
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# Latches : 1
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32-bit latch : 1
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# Logic shifters : 2
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32-bit shifter logical left : 1
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32-bit shifter logical right : 1
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=========================================================================
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=========================================================================
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* Low Level Synthesis *
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=========================================================================
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Optimizing unit ...
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Mapping all equations...
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Building and optimizing final netlist ...
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Found area constraint ratio of 100 (+ 5) on block Shifter, actual ratio is 4.
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Final Macro Processing ...
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=========================================================================
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Final Register Report
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Found no macro
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=========================================================================
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=========================================================================
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* Partition Report *
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=========================================================================
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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=========================================================================
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* Final Report *
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=========================================================================
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Final Results
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RTL Top Level Output File Name : Shifter.ngr
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Top Level Output File Name : Shifter
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Output Format : NGC
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Optimization Goal : Speed
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Keep Hierarchy : No
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Design Statistics
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# IOs : 101
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Cell Usage :
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# BELS : 418
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# GND : 1
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# LUT2 : 13
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# LUT3 : 149
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# LUT4 : 193
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# MUXCY : 7
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# MUXF5 : 54
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# VCC : 1
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# FlipFlops/Latches : 32
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# LD : 32
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# Clock Buffers : 1
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# BUFG : 1
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# IO Buffers : 99
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# IBUF : 67
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# OBUF : 32
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=========================================================================
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Device utilization summary:
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---------------------------
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Selected Device : 3s500efg320-4
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Number of Slices: 196 out of 4656 4%
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Number of 4 input LUTs: 355 out of 9312 3%
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Number of IOs: 101
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Number of bonded IOBs: 99 out of 232 42%
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IOB Flip Flops: 32
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Number of GCLKs: 1 out of 24 4%
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---------------------------
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Partition Resource Summary:
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---------------------------
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No Partitions were found in this design.
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---------------------------
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=========================================================================
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TIMING REPORT
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NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
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FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
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GENERATED AFTER PLACE-and-ROUTE.
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Clock Information:
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------------------
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-----------------------------------+------------------------+-------+
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Clock Signal | Clock buffer(FF name) | Load |
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-----------------------------------+------------------------+-------+
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Result_not00021(Result_not00021:O) | BUFG(*)(Result_0) | 32 |
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-----------------------------------+------------------------+-------+
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(*) This 1 clock signal(s) are generated by combinatorial logic,
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and XST is not able to identify which are the primary clock signals.
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Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
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Asynchronous Control Signals Information:
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----------------------------------------
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No asynchronous control signals found in this design
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Timing Summary:
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---------------
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Speed Grade: -4
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Minimum period: No path found
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Minimum input arrival time before clock: 9.422ns
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Maximum output required time after clock: 4.368ns
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Maximum combinational path delay: No path found
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Timing Detail:
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--------------
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All values displayed in nanoseconds (ns)
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=========================================================================
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Timing constraint: Default OFFSET IN BEFORE for Clock 'Result_not00021'
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Total number of paths / destination ports: 4086 / 32
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-------------------------------------------------------------------------
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Offset: 9.422ns (Levels of Logic = 8)
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Source: OP2<30> (PAD)
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Destination: Result_5 (LATCH)
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Destination Clock: Result_not00021 falling
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Data Path: OP2<30> to Result_5
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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IBUF:I->O 71 1.218 1.450 OP2_30_IBUF (OP2_30_IBUF)
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LUT3:I0->O 2 0.704 0.526 Sh117_SW0 (N121)
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LUT3:I1->O 5 0.704 0.712 Sh117 (Sh117)
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LUT4:I1->O 1 0.704 0.000 Sh1491 (Sh1491)
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MUXF5:I1->O 2 0.321 0.451 Sh149_f5 (Sh149)
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LUT4:I3->O 1 0.704 0.595 Result_mux0000<5>73 (Result_mux0000<5>73)
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LUT3:I0->O 1 0.704 0.000 Result_mux0000<5>119_F (N257)
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MUXF5:I0->O 1 0.321 0.000 Result_mux0000<5>119 (Result_mux0000<5>)
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LD:D 0.308 Result_5
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----------------------------------------
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Total 9.422ns (5.688ns logic, 3.734ns route)
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(60.4% logic, 39.6% route)
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=========================================================================
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Timing constraint: Default OFFSET OUT AFTER for Clock 'Result_not00021'
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Total number of paths / destination ports: 32 / 32
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-------------------------------------------------------------------------
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Offset: 4.368ns (Levels of Logic = 1)
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Source: Result_31 (LATCH)
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Destination: Result<0> (PAD)
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Source Clock: Result_not00021 falling
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Data Path: Result_31 to Result<0>
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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LD:G->Q 1 0.676 0.420 Result_31 (Result_31)
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OBUF:I->O 3.272 Result_0_OBUF (Result<0>)
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----------------------------------------
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Total 4.368ns (3.948ns logic, 0.420ns route)
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(90.4% logic, 9.6% route)
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=========================================================================
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Total REAL time to Xst completion: 7.00 secs
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Total CPU time to Xst completion: 7.46 secs
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-->
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Total memory usage is 203444 kilobytes
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Number of errors : 0 ( 0 filtered)
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Number of warnings : 2 ( 0 filtered)
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Number of infos : 1 ( 0 filtered)
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