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[/] [fluid_core_2/] [trunk/] [xilinx14.5 project/] [Staller.v] - Blame information for rev 4

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1 4 azmathmoos 
`timescale 1ns / 1ps
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`include "Configuration.v"
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module Staller(
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        input Clk,
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        input RST,
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        input bubble,
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        input load_hazard,
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        output stall,
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        output [0:4] bubble_lines
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    );
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        reg [0:8] bubble_reg;
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        reg stall_reg;
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                initial begin
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                        stall_reg <= 0;
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                end
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        wire Clk_RST;
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        assign Clk_RST = Clk || RST;
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        always@(posedge Clk_RST) begin
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                if (RST) begin
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                        bubble_reg <= 9'b111100000;
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                end else begin
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                  if (bubble) begin
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                        bubble_reg <= 9'b111100000;
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                  end else begin
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                        bubble_reg <= {1,bubble_reg[0:7]};
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                  end
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                  if (~stall_reg) begin
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                        if (load_hazard) begin
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                                stall_reg <= 1;
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                        end else begin
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                                stall_reg <= 0;
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                        end
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                   end else begin
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                                stall_reg <= 0;
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                        end
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                end
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        end
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        assign bubble_lines = bubble_reg[4:8];
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        assign stall = stall_reg;
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endmodule

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