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azmathmoos |
Release 14.5 - xst P.58f (nt)
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Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.08 secs
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--> Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.08 secs
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--> Reading design: Test_Bed.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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9.1) Device utilization summary
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9.2) Partition Resource Summary
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9.3) TIMING REPORT
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "Test_Bed.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "Test_Bed"
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Output Format : NGC
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Target Device : xc3s500e-4-fg320
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---- Source Options
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Top Module Name : Test_Bed
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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Safe Implementation : No
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FSM Style : LUT
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RAM Extraction : Yes
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RAM Style : Auto
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ROM Extraction : Yes
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Mux Style : Auto
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Decoder Extraction : YES
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Priority Encoder Extraction : Yes
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Shift Register Extraction : YES
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Logical Shifter Extraction : YES
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XOR Collapsing : YES
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ROM Style : Auto
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Mux Extraction : Yes
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Resource Sharing : YES
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Asynchronous To Synchronous : NO
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Multiplier Style : Auto
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Automatic Register Balancing : Yes
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---- Target Options
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Add IO Buffers : YES
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Global Maximum Fanout : 500
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Add Generic Clock Buffer(BUFG) : 24
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Register Duplication : YES
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Move First FlipFlop Stage : YES
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Move Last FlipFlop Stage : YES
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Slice Packing : YES
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Optimize Instantiated Primitives : NO
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Use Clock Enable : Yes
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Use Synchronous Set : Yes
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Use Synchronous Reset : Yes
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Pack IO Registers into IOBs : True
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 2
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Keep Hierarchy : No
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Netlist Hierarchy : As_Optimized
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RTL Output : Yes
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Global Optimization : AllClockNets
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Read Cores : YES
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Write Timing Constraints : NO
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Cross Clock Analysis : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : Maintain
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Slice Utilization Ratio : 100
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BRAM Utilization Ratio : 100
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Verilog 2001 : YES
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Auto BRAM Packing : NO
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Slice Utilization Ratio Delta : 5
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling verilog file "uOP_Store.v" in library work
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Compiling verilog include file "Configuration.v"
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Compiling verilog file "int_ALU.v" in library work
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Compiling verilog include file "Configuration.v"
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Module compiled
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Compiling verilog file "WB_Stage.v" in library work
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Compiling verilog include file "Configuration.v"
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Module compiled
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Compiling verilog file "Staller.v" in library work
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Compiling verilog include file "Configuration.v"
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Module compiled
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Compiling verilog file "Reg_Hist.v" in library work
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Compiling verilog include file "Configuration.v"
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Module compiled
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Compiling verilog file "Reg_File.v" in library work
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Compiling verilog include file "Configuration.v"
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Module compiled
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Compiling verilog file "P_Reg.v" in library work
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Compiling verilog include file "Configuration.v"
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Module compiled
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Compiling verilog file "MEM_Stage.v" in library work
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Compiling verilog include file "Configuration.v"
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Module compiled
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Compiling verilog file "interrupt_unit.v" in library work
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Compiling verilog include file "Configuration.v"
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Module compiled
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Compiling verilog file "IF_Stage.v" in library work
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Compiling verilog include file "Configuration.v"
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Module compiled
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Compiling verilog file "ID_Stage.v" in library work
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Compiling verilog include file "Configuration.v"
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Module compiled
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Compiling verilog file "EX_Stage.v" in library work
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Compiling verilog include file "Configuration.v"
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Module compiled
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Compiling verilog file "ioPort.v" in library work
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Compiling verilog include file "Configuration.v"
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Module compiled
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Compiling verilog file "Inst_Mem.v" in library work
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Compiling verilog include file "Configuration.v"
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Compiling verilog include file "Programming.v"
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Module compiled
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WARNING:HDLCompilers:299 - "Inst_Mem.v" line 15 Too many digits specified in binary constant
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Compiling verilog file "FluidCore.v" in library work
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Compiling verilog include file "Configuration.v"
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Module compiled
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Compiling verilog file "data_mem.v" in library work
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Compiling verilog include file "Configuration.v"
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Module compiled
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Compiling verilog file "Test_Bed.v" in library work
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Compiling verilog include file "Configuration.v"
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Module compiled
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Module compiled
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No errors in compilation
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Analysis of file <"Test_Bed.prj"> succeeded.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library with parameters.
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p_reg_w = "00000000000000000000000000001111"
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Analyzing hierarchy for module in library with parameters.
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p_reg_w = "00000000000000000000000001110101"
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Analyzing hierarchy for module in library with parameters.
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p_reg_w = "00000000000000000000000001000111"
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Analyzing hierarchy for module in library with parameters.
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p_reg_w = "00000000000000000000000000100110"
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing top module .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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p_reg_w = 32'sb00000000000000000000000000001111
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Module is correct for synthesis.
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Analyzing module in library .
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p_reg_w = 32'sb00000000000000000000000001110101
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Module is correct for synthesis.
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Analyzing module in library .
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p_reg_w = 32'sb00000000000000000000000001000111
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Module is correct for synthesis.
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Analyzing module in library .
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p_reg_w = 32'sb00000000000000000000000000100110
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Calling function .
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Calling function .
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INFO:Xst:1607 - Contents of array may be accessed with an index that does not cover the full array size.
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Performing bidirectional port resolution...
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Synthesizing Unit .
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Related source file is "Inst_Mem.v".
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WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:1781 - Signal is used but never assigned. Tied to default value.
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WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process.
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Found 13x16-bit ROM for signal <$COND_19>.
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Summary:
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inferred 1 ROM(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "data_mem.v".
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Found 10x32-bit single-port RAM for signal .
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Found 32-bit tristate buffer for signal .
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Found 32-bit register for signal .
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Summary:
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inferred 1 RAM(s).
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inferred 32 D-type flip-flop(s).
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inferred 32 Tristate(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "ioPort.v".
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Found 4-bit tristate buffer for signal .
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Found 4-bit tristate buffer for signal .
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Found 4-bit register for signal .
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Summary:
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inferred 4 D-type flip-flop(s).
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inferred 8 Tristate(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "Staller.v".
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Found 9-bit register for signal .
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Found 1-bit register for signal .
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Summary:
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inferred 10 D-type flip-flop(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "P_Reg.v".
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Found 16-bit register for signal .
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Summary:
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inferred 16 D-type flip-flop(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "P_Reg.v".
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Found 118-bit register for signal .
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Summary:
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inferred 118 D-type flip-flop(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "P_Reg.v".
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Found 72-bit register for signal .
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Summary:
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inferred 72 D-type flip-flop(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "P_Reg.v".
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Found 39-bit register for signal .
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Summary:
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inferred 39 D-type flip-flop(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "IF_Stage.v".
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Found 4-bit tristate buffer for signal .
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Found 10-bit 4-to-1 multiplexer for signal <$varindex0000> created at line 57.
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Found 6-bit adder carry out for signal created at line 44.
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| 372 |
|
|
Found 16-bit register for signal .
|
| 373 |
|
|
Found 6-bit register for signal .
|
| 374 |
|
|
Found 6-bit adder for signal created at line 51.
|
| 375 |
|
|
Found 40-bit register for signal .
|
| 376 |
|
|
Found 2-bit updown counter for signal .
|
| 377 |
|
|
Found 2-bit adder for signal created at line 41.
|
| 378 |
|
|
Summary:
|
| 379 |
|
|
inferred 1 Counter(s).
|
| 380 |
|
|
inferred 62 D-type flip-flop(s).
|
| 381 |
|
|
inferred 3 Adder/Subtractor(s).
|
| 382 |
|
|
inferred 10 Multiplexer(s).
|
| 383 |
|
|
inferred 4 Tristate(s).
|
| 384 |
|
|
Unit synthesized.
|
| 385 |
|
|
|
| 386 |
|
|
|
| 387 |
|
|
Synthesizing Unit .
|
| 388 |
|
|
Related source file is "Reg_File.v".
|
| 389 |
|
|
WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
| 390 |
|
|
Found 256-bit register for signal .
|
| 391 |
|
|
INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred for signal . You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time.
|
| 392 |
|
|
Summary:
|
| 393 |
|
|
inferred 256 D-type flip-flop(s).
|
| 394 |
|
|
inferred 64 Multiplexer(s).
|
| 395 |
|
|
Unit synthesized.
|
| 396 |
|
|
|
| 397 |
|
|
|
| 398 |
|
|
Synthesizing Unit .
|
| 399 |
|
|
Related source file is "Reg_Hist.v".
|
| 400 |
|
|
Found 1-bit xor2 for signal created at line 25.
|
| 401 |
|
|
Found 1-bit xor2 for signal created at line 25.
|
| 402 |
|
|
Found 1-bit xor2 for signal created at line 25.
|
| 403 |
|
|
Found 1-bit xor2 for signal created at line 26.
|
| 404 |
|
|
Found 1-bit xor2 for signal created at line 26.
|
| 405 |
|
|
Found 1-bit xor2 for signal created at line 26.
|
| 406 |
|
|
Found 1-bit xor2 for signal created at line 27.
|
| 407 |
|
|
Found 1-bit xor2 for signal created at line 27.
|
| 408 |
|
|
Found 1-bit xor2 for signal created at line 27.
|
| 409 |
|
|
Found 1-bit xor2 for signal created at line 28.
|
| 410 |
|
|
Found 1-bit xor2 for signal created at line 28.
|
| 411 |
|
|
Found 1-bit xor2 for signal created at line 28.
|
| 412 |
|
|
Found 1-bit xor2 for signal created at line 29.
|
| 413 |
|
|
Found 1-bit xor2 for signal created at line 29.
|
| 414 |
|
|
Found 1-bit xor2 for signal created at line 29.
|
| 415 |
|
|
Found 1-bit xor2 for signal created at line 30.
|
| 416 |
|
|
Found 1-bit xor2 for signal created at line 30.
|
| 417 |
|
|
Found 1-bit xor2 for signal created at line 30.
|
| 418 |
|
|
Unit synthesized.
|
| 419 |
|
|
|
| 420 |
|
|
|
| 421 |
|
|
Synthesizing Unit .
|
| 422 |
|
|
Related source file is "MEM_Stage.v".
|
| 423 |
|
|
WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
| 424 |
|
|
WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
| 425 |
|
|
Found 32-bit tristate buffer for signal .
|
| 426 |
|
|
Found 6-bit tristate buffer for signal .
|
| 427 |
|
|
Found 1-bit tristate buffer for signal .
|
| 428 |
|
|
Found 1-bit adder for signal .
|
| 429 |
|
|
Found 1-bit adder for signal created at line 52.
|
| 430 |
|
|
Found 1-bit adder for signal created at line 55.
|
| 431 |
|
|
Found 1-bit xor2 for signal created at line 52.
|
| 432 |
|
|
Summary:
|
| 433 |
|
|
inferred 3 Adder/Subtractor(s).
|
| 434 |
|
|
inferred 39 Tristate(s).
|
| 435 |
|
|
Unit synthesized.
|
| 436 |
|
|
|
| 437 |
|
|
|
| 438 |
|
|
Synthesizing Unit .
|
| 439 |
|
|
Related source file is "WB_Stage.v".
|
| 440 |
|
|
WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
| 441 |
|
|
Found 3-bit tristate buffer for signal .
|
| 442 |
|
|
Found 32-bit tristate buffer for signal .
|
| 443 |
|
|
Summary:
|
| 444 |
|
|
inferred 35 Tristate(s).
|
| 445 |
|
|
Unit synthesized.
|
| 446 |
|
|
|
| 447 |
|
|
|
| 448 |
|
|
Synthesizing Unit .
|
| 449 |
|
|
Related source file is "interrupt_unit.v".
|
| 450 |
|
|
Found 5x6-bit dual-port RAM for signal .
|
| 451 |
|
|
WARNING:Xst:737 - Found 2-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
| 452 |
|
|
Found 6-bit tristate buffer for signal .
|
| 453 |
|
|
Found 4-bit register for signal .
|
| 454 |
|
|
Found 1-bit register for signal .
|
| 455 |
|
|
Summary:
|
| 456 |
|
|
inferred 1 RAM(s).
|
| 457 |
|
|
inferred 5 D-type flip-flop(s).
|
| 458 |
|
|
inferred 6 Tristate(s).
|
| 459 |
|
|
Unit synthesized.
|
| 460 |
|
|
|
| 461 |
|
|
|
| 462 |
|
|
Synthesizing Unit .
|
| 463 |
|
|
Related source file is "uOP_Store.v".
|
| 464 |
|
|
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
| 465 |
|
|
WARNING:Xst:1781 - Signal is used but never assigned. Tied to default value.
|
| 466 |
|
|
Found 24x13-bit ROM for signal <$COND_13>.
|
| 467 |
|
|
Summary:
|
| 468 |
|
|
inferred 1 ROM(s).
|
| 469 |
|
|
Unit synthesized.
|
| 470 |
|
|
|
| 471 |
|
|
|
| 472 |
|
|
Synthesizing Unit .
|
| 473 |
|
|
Related source file is "int_ALU.v".
|
| 474 |
|
|
WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
| 475 |
|
|
WARNING:Xst:737 - Found 32-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
| 476 |
|
|
WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
| 477 |
|
|
WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
| 478 |
|
|
WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
| 479 |
|
|
WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
| 480 |
|
|
Found 32-bit adder carry out for signal created at line 29.
|
| 481 |
|
|
Found 32-bit adder carry out for signal created at line 30.
|
| 482 |
|
|
Found 1-bit xor4 for signal created at line 39.
|
| 483 |
|
|
Found 32-bit adder for signal .
|
| 484 |
|
|
Found 32-bit 8-to-1 multiplexer for signal created at line 28.
|
| 485 |
|
|
Found 32-bit xor2 for signal created at line 35.
|
| 486 |
|
|
Summary:
|
| 487 |
|
|
inferred 5 Adder/Subtractor(s).
|
| 488 |
|
|
inferred 32 Multiplexer(s).
|
| 489 |
|
|
inferred 1 Xor(s).
|
| 490 |
|
|
Unit synthesized.
|
| 491 |
|
|
|
| 492 |
|
|
|
| 493 |
|
|
Synthesizing Unit .
|
| 494 |
|
|
Related source file is "ID_Stage.v".
|
| 495 |
|
|
WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
| 496 |
|
|
WARNING:Xst:737 - Found 32-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
| 497 |
|
|
WARNING:Xst:737 - Found 32-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
| 498 |
|
|
Unit synthesized.
|
| 499 |
|
|
|
| 500 |
|
|
|
| 501 |
|
|
Synthesizing Unit .
|
| 502 |
|
|
Related source file is "EX_Stage.v".
|
| 503 |
|
|
WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
| 504 |
|
|
WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
| 505 |
|
|
Found 4-bit tristate buffer for signal .
|
| 506 |
|
|
Found 32-bit register for signal .
|
| 507 |
|
|
Found 32-bit tristate buffer for signal .
|
| 508 |
|
|
Found 4-bit register for signal .
|
| 509 |
|
|
Summary:
|
| 510 |
|
|
inferred 36 D-type flip-flop(s).
|
| 511 |
|
|
inferred 36 Tristate(s).
|
| 512 |
|
|
Unit synthesized.
|
| 513 |
|
|
|
| 514 |
|
|
|
| 515 |
|
|
Synthesizing Unit .
|
| 516 |
|
|
Related source file is "FluidCore.v".
|
| 517 |
|
|
WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
| 518 |
|
|
WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process.
|
| 519 |
|
|
Unit synthesized.
|
| 520 |
|
|
|
| 521 |
|
|
|
| 522 |
|
|
Synthesizing Unit .
|
| 523 |
|
|
Related source file is "Test_Bed.v".
|
| 524 |
|
|
WARNING:Xst:1306 - Output is never assigned.
|
| 525 |
|
|
Unit synthesized.
|
| 526 |
|
|
|
| 527 |
|
|
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
|
| 528 |
|
|
|
| 529 |
|
|
=========================================================================
|
| 530 |
|
|
HDL Synthesis Report
|
| 531 |
|
|
|
| 532 |
|
|
Macro Statistics
|
| 533 |
|
|
# RAMs : 2
|
| 534 |
|
|
10x32-bit single-port RAM : 1
|
| 535 |
|
|
5x6-bit dual-port RAM : 1
|
| 536 |
|
|
# ROMs : 2
|
| 537 |
|
|
13x16-bit ROM : 1
|
| 538 |
|
|
24x13-bit ROM : 1
|
| 539 |
|
|
# Adders/Subtractors : 11
|
| 540 |
|
|
1-bit adder : 3
|
| 541 |
|
|
2-bit adder : 1
|
| 542 |
|
|
32-bit adder : 1
|
| 543 |
|
|
32-bit adder carry out : 2
|
| 544 |
|
|
33-bit adder : 2
|
| 545 |
|
|
6-bit adder : 1
|
| 546 |
|
|
6-bit adder carry out : 1
|
| 547 |
|
|
# Counters : 1
|
| 548 |
|
|
2-bit updown counter : 1
|
| 549 |
|
|
# Registers : 26
|
| 550 |
|
|
1-bit register : 2
|
| 551 |
|
|
10-bit register : 4
|
| 552 |
|
|
118-bit register : 1
|
| 553 |
|
|
16-bit register : 2
|
| 554 |
|
|
32-bit register : 10
|
| 555 |
|
|
39-bit register : 1
|
| 556 |
|
|
4-bit register : 3
|
| 557 |
|
|
6-bit register : 1
|
| 558 |
|
|
72-bit register : 1
|
| 559 |
|
|
9-bit register : 1
|
| 560 |
|
|
# Latches : 9
|
| 561 |
|
|
1-bit latch : 5
|
| 562 |
|
|
2-bit latch : 1
|
| 563 |
|
|
32-bit latch : 3
|
| 564 |
|
|
# Multiplexers : 4
|
| 565 |
|
|
10-bit 4-to-1 multiplexer : 1
|
| 566 |
|
|
32-bit 8-to-1 multiplexer : 3
|
| 567 |
|
|
# Tristates : 12
|
| 568 |
|
|
1-bit tristate buffer : 1
|
| 569 |
|
|
3-bit tristate buffer : 1
|
| 570 |
|
|
32-bit tristate buffer : 4
|
| 571 |
|
|
4-bit tristate buffer : 4
|
| 572 |
|
|
6-bit tristate buffer : 2
|
| 573 |
|
|
# Xors : 21
|
| 574 |
|
|
1-bit xor2 : 19
|
| 575 |
|
|
1-bit xor4 : 1
|
| 576 |
|
|
32-bit xor2 : 1
|
| 577 |
|
|
|
| 578 |
|
|
=========================================================================
|
| 579 |
|
|
|
| 580 |
|
|
=========================================================================
|
| 581 |
|
|
* Advanced HDL Synthesis *
|
| 582 |
|
|
=========================================================================
|
| 583 |
|
|
|
| 584 |
|
|
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process.
|
| 585 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 586 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 587 |
|
|
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process.
|
| 588 |
|
|
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process.
|
| 589 |
|
|
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process.
|
| 590 |
|
|
|
| 591 |
|
|
Synthesizing (advanced) Unit .
|
| 592 |
|
|
INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style.
|
| 593 |
|
|
-----------------------------------------------------------------------
|
| 594 |
|
|
| ram_type | Distributed | |
|
| 595 |
|
|
-----------------------------------------------------------------------
|
| 596 |
|
|
| Port A |
|
| 597 |
|
|
| aspect ratio | 10-word x 32-bit | |
|
| 598 |
|
|
| clkA | connected to signal | rise |
|
| 599 |
|
|
| weA | connected to signal | high |
|
| 600 |
|
|
| addrA | connected to signal | |
|
| 601 |
|
|
| diA | connected to signal | |
|
| 602 |
|
|
| doA | connected to internal node | |
|
| 603 |
|
|
-----------------------------------------------------------------------
|
| 604 |
|
|
Unit synthesized (advanced).
|
| 605 |
|
|
|
| 606 |
|
|
Synthesizing (advanced) Unit .
|
| 607 |
|
|
INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
|
| 608 |
|
|
-----------------------------------------------------------------------
|
| 609 |
|
|
| ram_type | Distributed | |
|
| 610 |
|
|
-----------------------------------------------------------------------
|
| 611 |
|
|
| Port A |
|
| 612 |
|
|
| aspect ratio | 5-word x 6-bit | |
|
| 613 |
|
|
| clkA | connected to signal | rise |
|
| 614 |
|
|
| weA | connected to signal <_cmp_eq0000_0> | low |
|
| 615 |
|
|
| addrA | connected to signal | |
|
| 616 |
|
|
| diA | connected to signal | |
|
| 617 |
|
|
-----------------------------------------------------------------------
|
| 618 |
|
|
| Port B |
|
| 619 |
|
|
| aspect ratio | 5-word x 6-bit | |
|
| 620 |
|
|
| addrB | connected to signal | |
|
| 621 |
|
|
| doB | connected to internal node | |
|
| 622 |
|
|
-----------------------------------------------------------------------
|
| 623 |
|
|
Unit synthesized (advanced).
|
| 624 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 625 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 626 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 627 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 628 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 629 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 630 |
|
|
|
| 631 |
|
|
=========================================================================
|
| 632 |
|
|
Advanced HDL Synthesis Report
|
| 633 |
|
|
|
| 634 |
|
|
Macro Statistics
|
| 635 |
|
|
# RAMs : 2
|
| 636 |
|
|
10x32-bit single-port distributed RAM : 1
|
| 637 |
|
|
5x6-bit dual-port distributed RAM : 1
|
| 638 |
|
|
# ROMs : 2
|
| 639 |
|
|
13x16-bit ROM : 1
|
| 640 |
|
|
24x13-bit ROM : 1
|
| 641 |
|
|
# Adders/Subtractors : 11
|
| 642 |
|
|
1-bit adder : 3
|
| 643 |
|
|
2-bit adder : 1
|
| 644 |
|
|
32-bit adder : 1
|
| 645 |
|
|
32-bit adder carry out : 2
|
| 646 |
|
|
33-bit adder : 2
|
| 647 |
|
|
6-bit adder : 1
|
| 648 |
|
|
6-bit adder carry out : 1
|
| 649 |
|
|
# Counters : 1
|
| 650 |
|
|
2-bit updown counter : 1
|
| 651 |
|
|
# Registers : 644
|
| 652 |
|
|
Flip-Flops : 644
|
| 653 |
|
|
# Latches : 9
|
| 654 |
|
|
1-bit latch : 5
|
| 655 |
|
|
2-bit latch : 1
|
| 656 |
|
|
32-bit latch : 3
|
| 657 |
|
|
# Multiplexers : 69
|
| 658 |
|
|
1-bit 4-to-1 multiplexer : 4
|
| 659 |
|
|
1-bit 8-to-1 multiplexer : 64
|
| 660 |
|
|
32-bit 8-to-1 multiplexer : 1
|
| 661 |
|
|
# Xors : 21
|
| 662 |
|
|
1-bit xor2 : 19
|
| 663 |
|
|
1-bit xor4 : 1
|
| 664 |
|
|
32-bit xor2 : 1
|
| 665 |
|
|
|
| 666 |
|
|
=========================================================================
|
| 667 |
|
|
|
| 668 |
|
|
=========================================================================
|
| 669 |
|
|
* Low Level Synthesis *
|
| 670 |
|
|
=========================================================================
|
| 671 |
|
|
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process.
|
| 672 |
|
|
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process.
|
| 673 |
|
|
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process.
|
| 674 |
|
|
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process.
|
| 675 |
|
|
|
| 676 |
|
|
ERROR:Xst:528 - Multi-source in Unit on signal >; this signal is connected to multiple drivers.
|
| 677 |
|
|
Drivers are:
|
| 678 |
|
|
Output signal of BUFT instance
|
| 679 |
|
|
Output signal of BUFT instance
|
| 680 |
|
|
Signal > in Unit is assigned to GND
|
| 681 |
|
|
|
| 682 |
|
|
ERROR:Xst:528 - Multi-source in Unit on signal >; this signal is connected to multiple drivers.
|
| 683 |
|
|
Drivers are:
|
| 684 |
|
|
Output signal of BUFT instance
|
| 685 |
|
|
Output signal of BUFT instance
|
| 686 |
|
|
Signal > in Unit is assigned to GND
|
| 687 |
|
|
|
| 688 |
|
|
ERROR:Xst:528 - Multi-source in Unit on signal >; this signal is connected to multiple drivers.
|
| 689 |
|
|
Drivers are:
|
| 690 |
|
|
Output signal of BUFT instance
|
| 691 |
|
|
Output signal of BUFT instance
|
| 692 |
|
|
Signal > in Unit is assigned to GND
|
| 693 |
|
|
|
| 694 |
|
|
ERROR:Xst:528 - Multi-source in Unit on signal >; this signal is connected to multiple drivers.
|
| 695 |
|
|
Drivers are:
|
| 696 |
|
|
Output signal of BUFT instance
|
| 697 |
|
|
Output signal of BUFT instance
|
| 698 |
|
|
Signal > in Unit is assigned to GND
|
| 699 |
|
|
|
| 700 |
|
|
ERROR:Xst:528 - Multi-source in Unit on signal >; this signal is connected to multiple drivers.
|
| 701 |
|
|
Drivers are:
|
| 702 |
|
|
Output signal of BUFT instance
|
| 703 |
|
|
Output signal of BUFT instance
|
| 704 |
|
|
Signal > in Unit is assigned to GND
|
| 705 |
|
|
|
| 706 |
|
|
ERROR:Xst:528 - Multi-source in Unit on signal >; this signal is connected to multiple drivers.
|
| 707 |
|
|
Drivers are:
|
| 708 |
|
|
Output signal of BUFT instance
|
| 709 |
|
|
Output signal of BUFT instance
|
| 710 |
|
|
Signal > in Unit is assigned to GND
|
| 711 |
|
|
|
| 712 |
|
|
ERROR:Xst:528 - Multi-source in Unit on signal >; this signal is connected to multiple drivers.
|
| 713 |
|
|
Drivers are:
|
| 714 |
|
|
Output signal of BUFT instance
|
| 715 |
|
|
Output signal of BUFT instance
|
| 716 |
|
|
Signal > in Unit is assigned to GND
|
| 717 |
|
|
|
| 718 |
|
|
ERROR:Xst:528 - Multi-source in Unit on signal >; this signal is connected to multiple drivers.
|
| 719 |
|
|
Drivers are:
|
| 720 |
|
|
Output signal of BUFT instance
|
| 721 |
|
|
Output signal of BUFT instance
|
| 722 |
|
|
Signal > in Unit is assigned to GND
|
| 723 |
|
|
|
| 724 |
|
|
ERROR:Xst:528 - Multi-source in Unit on signal >; this signal is connected to multiple drivers.
|
| 725 |
|
|
Drivers are:
|
| 726 |
|
|
Output signal of BUFT instance
|
| 727 |
|
|
Output signal of BUFT instance
|
| 728 |
|
|
Signal > in Unit is assigned to GND
|
| 729 |
|
|
|
| 730 |
|
|
ERROR:Xst:528 - Multi-source in Unit on signal >; this signal is connected to multiple drivers.
|
| 731 |
|
|
Drivers are:
|
| 732 |
|
|
Output signal of BUFT instance
|
| 733 |
|
|
Output signal of BUFT instance
|
| 734 |
|
|
Signal > in Unit is assigned to GND
|
| 735 |
|
|
|
| 736 |
|
|
ERROR:Xst:528 - Multi-source in Unit on signal >; this signal is connected to multiple drivers.
|
| 737 |
|
|
Drivers are:
|
| 738 |
|
|
Output signal of BUFT instance
|
| 739 |
|
|
Output signal of BUFT instance
|
| 740 |
|
|
Signal > in Unit is assigned to GND
|
| 741 |
|
|
|
| 742 |
|
|
ERROR:Xst:528 - Multi-source in Unit on signal >; this signal is connected to multiple drivers.
|
| 743 |
|
|
Drivers are:
|
| 744 |
|
|
Output signal of BUFT instance
|
| 745 |
|
|
Output signal of BUFT instance
|
| 746 |
|
|
Signal > in Unit is assigned to GND
|
| 747 |
|
|
|
| 748 |
|
|
ERROR:Xst:528 - Multi-source in Unit on signal >; this signal is connected to multiple drivers.
|
| 749 |
|
|
Drivers are:
|
| 750 |
|
|
Output signal of BUFT instance
|
| 751 |
|
|
Output signal of BUFT instance
|
| 752 |
|
|
Signal > in Unit is assigned to GND
|
| 753 |
|
|
|
| 754 |
|
|
ERROR:Xst:528 - Multi-source in Unit on signal >; this signal is connected to multiple drivers.
|
| 755 |
|
|
Drivers are:
|
| 756 |
|
|
Output signal of BUFT instance
|
| 757 |
|
|
Output signal of BUFT instance
|
| 758 |
|
|
Signal > in Unit is assigned to GND
|
| 759 |
|
|
|
| 760 |
|
|
ERROR:Xst:528 - Multi-source in Unit on signal >; this signal is connected to multiple drivers.
|
| 761 |
|
|
Drivers are:
|
| 762 |
|
|
Output signal of BUFT instance
|
| 763 |
|
|
Output signal of BUFT instance
|
| 764 |
|
|
Signal > in Unit is assigned to GND
|
| 765 |
|
|
|
| 766 |
|
|
ERROR:Xst:528 - Multi-source in Unit on signal >; this signal is connected to multiple drivers.
|
| 767 |
|
|
Drivers are:
|
| 768 |
|
|
Output signal of BUFT instance
|
| 769 |
|
|
Output signal of BUFT instance
|
| 770 |
|
|
Signal > in Unit is assigned to GND
|
| 771 |
|
|
|
| 772 |
|
|
ERROR:Xst:528 - Multi-source in Unit on signal >; this signal is connected to multiple drivers.
|
| 773 |
|
|
Drivers are:
|
| 774 |
|
|
Output signal of BUFT instance
|
| 775 |
|
|
Output signal of BUFT instance
|
| 776 |
|
|
Signal > in Unit is assigned to GND
|
| 777 |
|
|
|
| 778 |
|
|
ERROR:Xst:528 - Multi-source in Unit on signal >; this signal is connected to multiple drivers.
|
| 779 |
|
|
Drivers are:
|
| 780 |
|
|
Output signal of BUFT instance
|
| 781 |
|
|
Output signal of BUFT instance
|
| 782 |
|
|
Signal > in Unit is assigned to GND
|
| 783 |
|
|
|
| 784 |
|
|
ERROR:Xst:528 - Multi-source in Unit on signal >; this signal is connected to multiple drivers.
|
| 785 |
|
|
Drivers are:
|
| 786 |
|
|
Output signal of BUFT instance
|
| 787 |
|
|
Output signal of BUFT instance
|
| 788 |
|
|
Signal > in Unit is assigned to GND
|
| 789 |
|
|
|
| 790 |
|
|
ERROR:Xst:528 - Multi-source in Unit on signal >; this signal is connected to multiple drivers.
|
| 791 |
|
|
Drivers are:
|
| 792 |
|
|
Output signal of BUFT instance
|
| 793 |
|
|
Output signal of BUFT instance
|
| 794 |
|
|
Signal > in Unit is assigned to GND
|
| 795 |
|
|
|
| 796 |
|
|
ERROR:Xst:528 - Multi-source in Unit on signal >; this signal is connected to multiple drivers.
|
| 797 |
|
|
Drivers are:
|
| 798 |
|
|
Output signal of BUFT instance
|
| 799 |
|
|
Output signal of BUFT instance
|
| 800 |
|
|
Signal > in Unit is assigned to GND
|
| 801 |
|
|
|
| 802 |
|
|
ERROR:Xst:528 - Multi-source in Unit on signal >; this signal is connected to multiple drivers.
|
| 803 |
|
|
Drivers are:
|
| 804 |
|
|
Output signal of BUFT instance
|
| 805 |
|
|
Output signal of BUFT instance
|
| 806 |
|
|
Signal > in Unit is assigned to GND
|
| 807 |
|
|
|
| 808 |
|
|
ERROR:Xst:528 - Multi-source in Unit on signal >; this signal is connected to multiple drivers.
|
| 809 |
|
|
Drivers are:
|
| 810 |
|
|
Output signal of BUFT instance
|
| 811 |
|
|
Output signal of BUFT instance
|
| 812 |
|
|
Signal > in Unit is assigned to GND
|
| 813 |
|
|
|
| 814 |
|
|
ERROR:Xst:528 - Multi-source in Unit on signal >; this signal is connected to multiple drivers.
|
| 815 |
|
|
Drivers are:
|
| 816 |
|
|
Output signal of BUFT instance
|
| 817 |
|
|
Output signal of BUFT instance
|
| 818 |
|
|
Signal > in Unit is assigned to GND
|
| 819 |
|
|
|
| 820 |
|
|
ERROR:Xst:528 - Multi-source in Unit on signal >; this signal is connected to multiple drivers.
|
| 821 |
|
|
Drivers are:
|
| 822 |
|
|
Output signal of BUFT instance
|
| 823 |
|
|
Output signal of BUFT instance
|
| 824 |
|
|
Signal > in Unit is assigned to GND
|
| 825 |
|
|
|
| 826 |
|
|
ERROR:Xst:528 - Multi-source in Unit on signal >; this signal is connected to multiple drivers.
|
| 827 |
|
|
Drivers are:
|
| 828 |
|
|
Output signal of BUFT instance
|
| 829 |
|
|
Output signal of BUFT instance
|
| 830 |
|
|
Signal > in Unit is assigned to GND
|
| 831 |
|
|
|
| 832 |
|
|
ERROR:Xst:528 - Multi-source in Unit on signal >; this signal is connected to multiple drivers.
|
| 833 |
|
|
Drivers are:
|
| 834 |
|
|
Output signal of BUFT instance
|
| 835 |
|
|
Output signal of BUFT instance
|
| 836 |
|
|
Signal > in Unit is assigned to GND
|
| 837 |
|
|
|
| 838 |
|
|
ERROR:Xst:528 - Multi-source in Unit on signal >; this signal is connected to multiple drivers.
|
| 839 |
|
|
Drivers are:
|
| 840 |
|
|
Output signal of BUFT instance
|
| 841 |
|
|
Output signal of BUFT instance
|
| 842 |
|
|
Signal > in Unit is assigned to GND
|
| 843 |
|
|
|
| 844 |
|
|
|
| 845 |
|
|
Total REAL time to Xst completion: 4.00 secs
|
| 846 |
|
|
Total CPU time to Xst completion: 3.98 secs
|
| 847 |
|
|
|
| 848 |
|
|
-->
|
| 849 |
|
|
|
| 850 |
|
|
Total memory usage is 198948 kilobytes
|
| 851 |
|
|
|
| 852 |
|
|
Number of errors : 28 ( 0 filtered)
|
| 853 |
|
|
Number of warnings : 45 ( 0 filtered)
|
| 854 |
|
|
Number of infos : 5 ( 0 filtered)
|
| 855 |
|
|
|
