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azmathmoos |
Running: C:\Xilinx\14.5\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -o C:/Users/Azmath/Documents/M Tech Project/FC2/tb_Test_Bed_isim_beh.exe -prj C:/Users/Azmath/Documents/M Tech Project/FC2/tb_Test_Bed_beh.prj work.tb_Test_Bed work.glbl
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ISim P.58f (signature 0x7708f090)
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Number of CPUs detected in this system: 4
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Turning on mult-threading, number of parallel sub-compilation jobs: 8
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Determining compilation order of HDL files
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Analyzing Verilog file "C:/Users/Azmath/Documents/M Tech Project/FC2/Shifter.v" into library work
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Analyzing Verilog file "C:/Users/Azmath/Documents/M Tech Project/FC2/int_ALU.v" into library work
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WARNING:HDLCompiler:327 - "C:/Users/Azmath/Documents/M Tech Project/FC2/int_ALU.v" Line 25: Concatenation with unsized literal; will interpret as 32 bits
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Analyzing Verilog file "C:/Users/Azmath/Documents/M Tech Project/FC2/WB_Stage.v" into library work
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Analyzing Verilog file "C:/Users/Azmath/Documents/M Tech Project/FC2/uOP_Store.v" into library work
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Analyzing Verilog file "C:/Users/Azmath/Documents/M Tech Project/FC2/Staller.v" into library work
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WARNING:HDLCompiler:327 - "C:/Users/Azmath/Documents/M Tech Project/FC2/Staller.v" Line 29: Concatenation with unsized literal; will interpret as 32 bits
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Analyzing Verilog file "C:/Users/Azmath/Documents/M Tech Project/FC2/Reg_Hist.v" into library work
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Analyzing Verilog file "C:/Users/Azmath/Documents/M Tech Project/FC2/Reg_File.v" into library work
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Analyzing Verilog file "C:/Users/Azmath/Documents/M Tech Project/FC2/P_Reg.v" into library work
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Analyzing Verilog file "C:/Users/Azmath/Documents/M Tech Project/FC2/MEM_Stage.v" into library work
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Analyzing Verilog file "C:/Users/Azmath/Documents/M Tech Project/FC2/interrupt_unit.v" into library work
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Analyzing Verilog file "C:/Users/Azmath/Documents/M Tech Project/FC2/IF_Stage.v" into library work
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Analyzing Verilog file "C:/Users/Azmath/Documents/M Tech Project/FC2/ID_Stage.v" into library work
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Analyzing Verilog file "C:/Users/Azmath/Documents/M Tech Project/FC2/EX_Stage.v" into library work
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Analyzing Verilog file "C:/Users/Azmath/Documents/M Tech Project/FC2/ioPort.v" into library work
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Analyzing Verilog file "C:/Users/Azmath/Documents/M Tech Project/FC2/Inst_Mem.v" into library work
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WARNING:HDLCompiler:568 - "C:/Users/Azmath/Documents/M Tech Project/FC2/Inst_Mem.v" Line 19: Constant value is truncated to fit in <6> bits.
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WARNING:HDLCompiler:327 - "C:/Users/Azmath/Documents/M Tech Project/FC2/Inst_Mem.v" Line 15: Concatenation with unsized literal; will interpret as 32 bits
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WARNING:HDLCompiler:327 - "C:/Users/Azmath/Documents/M Tech Project/FC2/Inst_Mem.v" Line 16: Concatenation with unsized literal; will interpret as 32 bits
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WARNING:HDLCompiler:327 - "C:/Users/Azmath/Documents/M Tech Project/FC2/Inst_Mem.v" Line 17: Concatenation with unsized literal; will interpret as 32 bits
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WARNING:HDLCompiler:327 - "C:/Users/Azmath/Documents/M Tech Project/FC2/Inst_Mem.v" Line 18: Concatenation with unsized literal; will interpret as 32 bits
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WARNING:HDLCompiler:327 - "C:/Users/Azmath/Documents/M Tech Project/FC2/Inst_Mem.v" Line 19: Concatenation with unsized literal; will interpret as 32 bits
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WARNING:HDLCompiler:327 - "C:/Users/Azmath/Documents/M Tech Project/FC2/Inst_Mem.v" Line 20: Concatenation with unsized literal; will interpret as 32 bits
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WARNING:HDLCompiler:327 - "C:/Users/Azmath/Documents/M Tech Project/FC2/Inst_Mem.v" Line 22: Concatenation with unsized literal; will interpret as 32 bits
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WARNING:HDLCompiler:327 - "C:/Users/Azmath/Documents/M Tech Project/FC2/Inst_Mem.v" Line 23: Concatenation with unsized literal; will interpret as 32 bits
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WARNING:HDLCompiler:327 - "C:/Users/Azmath/Documents/M Tech Project/FC2/Inst_Mem.v" Line 26: Concatenation with unsized literal; will interpret as 32 bits
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WARNING:HDLCompiler:327 - "C:/Users/Azmath/Documents/M Tech Project/FC2/Inst_Mem.v" Line 27: Concatenation with unsized literal; will interpret as 32 bits
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WARNING:HDLCompiler:327 - "C:/Users/Azmath/Documents/M Tech Project/FC2/Inst_Mem.v" Line 28: Concatenation with unsized literal; will interpret as 32 bits
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WARNING:HDLCompiler:327 - "C:/Users/Azmath/Documents/M Tech Project/FC2/Inst_Mem.v" Line 29: Concatenation with unsized literal; will interpret as 32 bits
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WARNING:HDLCompiler:327 - "C:/Users/Azmath/Documents/M Tech Project/FC2/Inst_Mem.v" Line 30: Concatenation with unsized literal; will interpret as 32 bits
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Analyzing Verilog file "C:/Users/Azmath/Documents/M Tech Project/FC2/FluidCore.v" into library work
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Analyzing Verilog file "C:/Users/Azmath/Documents/M Tech Project/FC2/data_mem.v" into library work
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Analyzing Verilog file "C:/Users/Azmath/Documents/M Tech Project/FC2/Test_Bed.v" into library work
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Analyzing Verilog file "C:/Users/Azmath/Documents/M Tech Project/FC2/tb_Test_Bed.v" into library work
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Analyzing Verilog file "C:/Xilinx/14.5/ISE_DS/ISE//verilog/src/glbl.v" into library work
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Starting static elaboration
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WARNING:HDLCompiler:1016 - "C:/Users/Azmath/Documents/M Tech Project/FC2/tb_Test_Bed.v" Line 11: Port data is not connected to this instance
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WARNING:HDLCompiler:1016 - "C:/Users/Azmath/Documents/M Tech Project/FC2/Test_Bed.v" Line 46: Port io_data is not connected to this instance
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WARNING:HDLCompiler:1016 - "C:/Users/Azmath/Documents/M Tech Project/FC2/FluidCore.v" Line 89: Port exInstClk is not connected to this instance
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WARNING:HDLCompiler:327 - "C:/Users/Azmath/Documents/M Tech Project/FC2/Staller.v" Line 29: Concatenation with unsized literal; will interpret as 32 bits
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WARNING:HDLCompiler:189 - "C:/Users/Azmath/Documents/M Tech Project/FC2/FluidCore.v" Line 35: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit.
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WARNING:HDLCompiler:189 - "C:/Users/Azmath/Documents/M Tech Project/FC2/FluidCore.v" Line 111: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 5-bit.
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WARNING:HDLCompiler:189 - "C:/Users/Azmath/Documents/M Tech Project/FC2/FluidCore.v" Line 175: Size mismatch in connection of port . Formal port size is 13-bit while actual signal size is 32-bit.
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WARNING:HDLCompiler:327 - "C:/Users/Azmath/Documents/M Tech Project/FC2/int_ALU.v" Line 25: Concatenation with unsized literal; will interpret as 32 bits
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WARNING:HDLCompiler:189 - "C:/Users/Azmath/Documents/M Tech Project/FC2/FluidCore.v" Line 225: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 5-bit.
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WARNING:HDLCompiler:189 - "C:/Users/Azmath/Documents/M Tech Project/FC2/FluidCore.v" Line 228: Size mismatch in connection of port . Formal port size is 6-bit while actual signal size is 32-bit.
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WARNING:HDLCompiler:327 - "C:/Users/Azmath/Documents/M Tech Project/FC2/Inst_Mem.v" Line 15: Concatenation with unsized literal; will interpret as 32 bits
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WARNING:HDLCompiler:327 - "C:/Users/Azmath/Documents/M Tech Project/FC2/Inst_Mem.v" Line 16: Concatenation with unsized literal; will interpret as 32 bits
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WARNING:HDLCompiler:327 - "C:/Users/Azmath/Documents/M Tech Project/FC2/Inst_Mem.v" Line 17: Concatenation with unsized literal; will interpret as 32 bits
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WARNING:HDLCompiler:327 - "C:/Users/Azmath/Documents/M Tech Project/FC2/Inst_Mem.v" Line 18: Concatenation with unsized literal; will interpret as 32 bits
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WARNING:HDLCompiler:327 - "C:/Users/Azmath/Documents/M Tech Project/FC2/Inst_Mem.v" Line 19: Concatenation with unsized literal; will interpret as 32 bits
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WARNING:HDLCompiler:327 - "C:/Users/Azmath/Documents/M Tech Project/FC2/Inst_Mem.v" Line 20: Concatenation with unsized literal; will interpret as 32 bits
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WARNING:HDLCompiler:327 - "C:/Users/Azmath/Documents/M Tech Project/FC2/Inst_Mem.v" Line 22: Concatenation with unsized literal; will interpret as 32 bits
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WARNING:HDLCompiler:327 - "C:/Users/Azmath/Documents/M Tech Project/FC2/Inst_Mem.v" Line 23: Concatenation with unsized literal; will interpret as 32 bits
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WARNING:HDLCompiler:327 - "C:/Users/Azmath/Documents/M Tech Project/FC2/Inst_Mem.v" Line 26: Concatenation with unsized literal; will interpret as 32 bits
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WARNING:HDLCompiler:327 - "C:/Users/Azmath/Documents/M Tech Project/FC2/Inst_Mem.v" Line 27: Concatenation with unsized literal; will interpret as 32 bits
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WARNING:HDLCompiler:327 - "C:/Users/Azmath/Documents/M Tech Project/FC2/Inst_Mem.v" Line 28: Concatenation with unsized literal; will interpret as 32 bits
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WARNING:HDLCompiler:327 - "C:/Users/Azmath/Documents/M Tech Project/FC2/Inst_Mem.v" Line 29: Concatenation with unsized literal; will interpret as 32 bits
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WARNING:HDLCompiler:327 - "C:/Users/Azmath/Documents/M Tech Project/FC2/Inst_Mem.v" Line 30: Concatenation with unsized literal; will interpret as 32 bits
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WARNING:HDLCompiler:189 - "C:/Users/Azmath/Documents/M Tech Project/FC2/Test_Bed.v" Line 51: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 32-bit.
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Completed static elaboration
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Compiling module Staller
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Compiling module P_Reg(p_reg_w=15)
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Compiling module P_Reg(p_reg_w=118)
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Compiling module P_Reg(p_reg_w=72)
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Compiling module P_Reg(p_reg_w=38)
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Compiling module IF_Stage
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Compiling module Reg_File
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Compiling module Reg_Hist
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Compiling module ID_Stage
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Compiling module uOP_Store
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Compiling module int_ALU
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Compiling module Shifter
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Compiling module EX_Stage
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Compiling module MEM_Stage
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Compiling module WB_Stage
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Compiling module interrupt_unit
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Compiling module FluidCore
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Compiling module Inst_Mem
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Compiling module data_mem
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Compiling module ioPort
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Compiling module Test_Bed
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Compiling module tb_Test_Bed
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Compiling module glbl
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Time Resolution for simulation is 1ps.
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Waiting for 1 sub-compilation(s) to finish...
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Compiled 23 Verilog Units
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Built simulation executable C:/Users/Azmath/Documents/M Tech Project/FC2/tb_Test_Bed_isim_beh.exe
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Fuse Memory Usage: 27728 KB
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Fuse CPU Usage: 686 ms
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