Subversion Repositories fluid_core_2

`timescale 1ns / 1ps

`include "Configuration.v"

module interrupt_unit(

        input Clk,

        input [0:`intr_msb] intr_req,

        input [0:log2(`intr_msb)] intr_inx,

        input [0:`pc_w] new_vector,

        input write, return_back,

        output intr,

        output [0:`pc_w] vector

    );

        reg [0:`pc_w] isr_vectors [0:`intr_msb+1];

        reg [0:`intr_msb] masks;

        reg temp_unblock;

        reg [0:log2(`intr_msb)-1] vctr_inx;

        integer i;

        always@(*) begin

        for ( i = `intr_msb; (i >= 0); i = i - 1) begin

                if (intr_req[i] == 1) begin

                vctr_inx <= i;

                end

        end

        end

        initial begin

                temp_unblock <= 1;

        end

        assign intr = |(masks & intr_req ) & temp_unblock; //(~(vctr_inx == 0)&&(masks[vctr_inx]));

        assign vector = intr ? isr_vectors[vctr_inx]:'bz;

        always@(posedge Clk) begin

                if (write) begin//write

                        if (intr_inx == 0) masks <= new_vector; //(aligned by MSB)

                        else begin

                        isr_vectors[intr_inx] <= new_vector;

                        end

                end

                if (intr) temp_unblock <= 0;

                else if (return_back) temp_unblock <= 1;

        end

        //--- Constant Function ----//

        function integer log2;

          input integer value;

          begin

                 value = value-1;

                 for (log2=0; value>0; log2=log2+1)

                        value = value>>1;

          end

        endfunction

endmodule