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[/] [fluid_core_2/] [trunk/] [xilinx14.5 project/] [ioPort.v] - Blame information for rev 4

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1 4 azmathmoos
`timescale 1ns / 1ps
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`include "Configuration.v"
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module ioPort(
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        input en, rd, wr,
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        input Clk,
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        inout [0:3] fc_data,
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        inout [0:3] io_data
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    );
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        reg [0:3] io_data_buff;
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always @(posedge Clk) begin
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        if (en & wr) io_data_buff <= fc_data;
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end
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        assign fc_data = (rd) ? io_data:'bz;
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        assign io_data = (~rd) ? io_data_buff:'bz;
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endmodule

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