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-------------------------------------------------------------------------------
--| @file h2.vhd
--| @brief The H2 Processor: J1 processor translation and extension.
--| Moved bit 12 to bit 4 to allow for more ALU instructions.
--|
--| @author         Richard James Howe.
--| @copyright      Copyright 2017, 2019 Richard James Howe.
--| @license        MIT
--| @email          howe.r.j.89@gmail.com
--|
--| NB. It would be nice to be able to specify the CPU word length with a
--| generic, so we could instantiate a 32-bit CPU if we wanted to.
-------------------------------------------------------------------------------
 
library ieee,work,std;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
package h2_pkg is
        subtype word    is std_ulogic_vector(15 downto 0);
        subtype address is std_ulogic_vector(12 downto 0);
 
        constant hardware_cpu_id: word   := X"0666";
        constant simulation_cpu_id: word := X"1984";
 
        component h2 is
                generic(
                        asynchronous_reset:       boolean  := true; -- use asynchronous reset if true, synchronous if false
                        delay:                    time     := 0 ns; -- simulation only, gate delay
 
                        cpu_id:                   word     := hardware_cpu_id; -- Value for the CPU ID instruction
                        interrupt_address_length: positive := 3;               -- Log_2 of the number of interrupts
                        start_address:            natural  := 0;               -- Initial program counter value
                        stack_size_log2:          positive := 6;               -- Log_2 of the Size of the stack
                        use_interrupts:           boolean  := true             -- Enable Interrupts in the H2 Core
                );
                port(
                        clk:      in  std_ulogic;
                        rst:      in  std_ulogic; -- active high reset, configurable async/sync
                        stop:     in  std_ulogic; -- Assert high to halt the H2 core
 
                        -- IO interface
                        io_wr:    out std_ulogic; -- Output Write Enable
                        io_re:    out std_ulogic; -- Input  Read  Enable
                        io_din:   in  word;       -- Data Input from register
                        io_dout:  out word;       -- Data Output to register
                        io_daddr: out word;       -- Data Address for I/O action
 
                        irq:      in  std_ulogic; -- Interrupt Request
                        irq_addr: in  std_ulogic_vector(interrupt_address_length - 1 downto 0); -- Address to jump to on Interrupt Request
 
                        -- RAM interface, Dual port
                        pc:       out address;   -- program counter
                        insn:     in  word;      -- instruction
 
                        dwe:      out std_ulogic; -- RAM data write enable
                        dre:      out std_ulogic; -- RAM data read enable
                        din:      in  word;       -- RAM data input
                        dout:     out word;       -- RAM data output
                        daddr:    out address);   -- RAM address
        end component;
end;
 
library ieee,work,std;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all; -- only needed for calculations relating to generics
use work.h2_pkg.all;
 
entity h2 is
        generic(
                asynchronous_reset:       boolean  := true; -- use asynchronous reset if true, synchronous if false
                delay:                    time     := 0 ns; -- simulation only, gate delay
 
                cpu_id:                   word     := hardware_cpu_id; -- Value for the CPU ID instruction
                interrupt_address_length: positive := 3;               -- Log_2 of the number of interrupts
                start_address:            natural  := 0;               -- Initial program counter value
                stack_size_log2:          positive := 6;               -- Log_2 of the Size of the stack
                use_interrupts:           boolean  := true);           -- Enable Interrupts in the H2 Core
        port(
                clk:      in  std_ulogic;
                rst:      in  std_ulogic;
 
                -- IO interface
                stop:     in  std_ulogic; -- Assert high to halt the H2 core
 
                io_wr:    out std_ulogic; -- Output Write Enable
                io_re:    out std_ulogic; -- Input  Read  Enable
                io_din:   in  word;       -- Data  Input from register
                io_dout:  out word;       -- Data  Output to register
                io_daddr: out word;       -- Data  Address for I/O action
 
                irq:      in  std_ulogic; -- Interrupt Request
                irq_addr: in  std_ulogic_vector(interrupt_address_length - 1 downto 0); -- Address to jump to on Interrupt Request
 
                -- RAM interface, Dual port
                pc:       out address;    -- program counter
                insn:     in  word;       -- instruction
 
                dwe:      out std_ulogic; -- RAM data write enable
                dre:      out std_ulogic; -- RAM data read enable
                din:      in  word;       -- RAM data input
                dout:     out word;       -- RAM data output
                daddr:    out address);   -- RAM address
end;
 
architecture rtl of h2 is
        signal pc_c:        address := std_ulogic_vector(to_unsigned(start_address, address'length));
        signal pc_n:        address := (others => '0');
        signal pc_plus_one: address := (others => '0');
 
        constant stack_size: integer := 2 ** stack_size_log2;
        type     stack_type is array (stack_size - 1 downto 0) of word;
        subtype  depth is unsigned(stack_size_log2 - 1 downto 0);
 
        signal vstkp_c, vstkp_n:  depth := (others => '0');             -- variable stack pointer
        signal vstk_ram: stack_type     := (others => (others => '0')); -- variable stack
        signal dstk_we: std_ulogic      := '0';                         -- variable stack write enable
        signal dd: depth                := (others => '0');             -- variable stack delta
 
        signal rstkp_c, rstkp_n:  depth := (others => '0');             -- return stack pointer
        signal rstk_ram: stack_type     := (others => (others => '0')); -- return stack
        signal rstk_we: std_ulogic      := '0';                         -- return stack write enable
        signal rd: depth                := (others => '0');             -- return stack delta
 
        type instruction_info_type is record
                alu:     std_ulogic;
                lit:     std_ulogic;
                branch:  std_ulogic;
                branch0: std_ulogic;
                call:    std_ulogic;
        end record;
 
        signal is_instr: instruction_info_type := ('0', '0', '0', '0', '0');
        signal is_interrupt: std_ulogic := '0';
        signal is_ram_write: std_ulogic := '0';
 
        type compare_type is record
                more:  std_ulogic; -- signed greater than; T > N?
                equal: std_ulogic; -- equality; N = T?
                umore: std_ulogic; -- unsigned greater than; T > N?
                zero:  std_ulogic; -- zero test; T = 0?
        end record;
 
        signal compare: compare_type := ('0', '0', '0', '0');
 
        signal stop_c:     std_ulogic := '1'; -- processor wait state register (current)
        signal stop_n:     std_ulogic := '0'; -- processor wait state register (next)
 
        signal irq_en_c, irq_en_n: std_ulogic := '0'; -- interrupt enable
        signal irq_c, irq_n:       std_ulogic := '0'; -- pending interrupt request
        signal irq_addr_c, irq_addr_n: std_ulogic_vector(irq_addr'range) := (others => '0'); -- address of pending interrupt request vector
 
        signal tos_c, tos_n: word := (others => '0'); -- top of stack
        signal nos:          word := (others => '0'); -- next on stack
        signal rtos_c:       word := (others => '0'); -- top of return stack
        signal rstk_data:    word := (others => '0'); -- return stack input
        signal aluop:        std_ulogic_vector(4 downto 0) := (others => '0'); -- ALU operation
 
        signal instruction:  word := (others => '0'); -- processed 'insn'
begin
        assert stack_size > 4 report "stack size too small: " & integer'image(stack_size) severity failure;
        -- assert dd /= "10" severity warning; -- valid, but odd (now used)
 
        is_instr.branch  <= '1' when instruction(15 downto 13) = "000" else '0' after delay;
        is_instr.branch0 <= '1' when instruction(15 downto 13) = "001" else '0' after delay;
        is_instr.call    <= '1' when instruction(15 downto 13) = "010" else '0' after delay;
        is_instr.alu     <= '1' when instruction(15 downto 13) = "011" else '0' after delay;
        is_instr.lit     <= '1' when instruction(15)           = '1'   else '0' after delay;
        is_ram_write     <= '1' when is_instr.alu = '1' and instruction(5) = '1' else '0' after delay;
        compare.more     <= '1' when   signed(tos_c) >   signed(nos) else '0' after delay;
        compare.umore    <= '1' when unsigned(tos_c) > unsigned(nos) else '0' after delay;
        compare.equal    <= '1' when tos_c = nos else '0' after delay;
        compare.zero     <= '1' when unsigned(tos_c(15 downto 0)) = 0 else '0' after delay;
        nos              <= vstk_ram(to_integer(vstkp_c)) after delay;
        rtos_c           <= rstk_ram(to_integer(rstkp_c)) after delay;
        pc               <= pc_n after delay;
        pc_plus_one      <= std_ulogic_vector(unsigned(pc_c) + 1) after delay;
        dout             <= nos after delay;
        daddr            <= tos_c(13 downto 1) when is_ram_write = '1' else tos_n(13 downto 1) after delay;
        dwe              <= '1' when is_ram_write = '1' and tos_c(15 downto 14) = "00" else '0' after delay;
        dre              <= '1' when                        tos_n(15 downto 14) = "00" else '0' after delay;
        io_dout          <= nos after delay;
        io_daddr         <= tos_c after delay;
        io_wr            <= '1' when is_ram_write = '1' and tos_c(15 downto 14) /= "00" else '0' after delay;
        is_interrupt     <= '1' when irq_c = '1' and irq_en_c = '1' and use_interrupts else '0' after delay;
        irq_n            <= irq after delay;
        irq_addr_n       <= irq_addr after delay;
        stop_n           <= stop after delay;
        dd(0)            <= instruction(0) after delay;
        rd(0)            <= instruction(2) after delay;
        dd(dd'high downto 1) <= (others => '1') when instruction(1) = '1' else (others => '0') after delay; -- sign extend
        rd(rd'high downto 1) <= (others => '1') when instruction(3) = '1' else (others => '0') after delay; -- sign extend
        dstk_we          <= '1' when (is_instr.lit = '1' or (is_instr.alu = '1' and instruction(7) = '1')) else '0' after delay;
 
        next_state: process(clk, rst)
                procedure reset is
                begin
                        pc_c       <= std_ulogic_vector(to_unsigned(start_address, pc_c'length)) after delay;
                        stop_c     <= '1' after delay; -- start in stopped state
                        vstkp_c    <= (others => '0') after delay;
                        rstkp_c    <= (others => '0') after delay;
                        tos_c      <= (others => '0') after delay;
                        irq_addr_c <= (others => '0') after delay;
                        irq_en_c   <= '0' after delay;
                        irq_c      <= '0' after delay;
                end reset;
        begin
                if rst = '1' and asynchronous_reset then
                        reset;
                elsif rising_edge(clk) then
                        if rst = '1' and not asynchronous_reset then
                                reset;
                        else
                                assert stop_c = '0' or (stop_c = '1' and is_instr.branch = '1') severity failure;
                                assert (not rstk_we = '1') or (((is_instr.alu = '1' and instruction(6) = '1') or is_instr.call = '1')) severity failure;
                                assert (not dstk_we = '1') or (((is_instr.alu = '1' and instruction(7) = '1') or is_instr.lit = '1')) severity failure;
 
                                pc_c       <= pc_n after delay;
                                stop_c     <= stop_n after delay;
                                vstkp_c    <= vstkp_n after delay;
                                rstkp_c    <= rstkp_n after delay;
                                tos_c      <= tos_n after delay;
                                irq_addr_c <= irq_addr_n after delay;
                                irq_en_c   <= irq_en_n after delay;
                                irq_c      <= irq_n after delay;
                        end if;
                end if;
        end process;
 
        stack_write: process(clk)
        begin
                if rising_edge(clk) then
                        if dstk_we = '1' then
                                vstk_ram(to_integer(vstkp_n)) <= tos_c after delay;
                        end if;
                        if rstk_we = '1' then
                                rstk_ram(to_integer(rstkp_n)) <= rstk_data after delay;
                        end if;
                end if;
        end process;
 
        decode: process(insn, irq_addr_c, is_interrupt, stop_c, pc_c)
        begin
                if stop_c = '1' then -- assert a BRANCH instruction to current location on CPU halt
                        instruction <= "000" & pc_c after delay;
                elsif is_interrupt = '1' then -- assemble a CALL instruction on interrupt
                        instruction                   <= (others => '0') after delay;
                        instruction(15 downto 13)     <= "010" after delay;      -- turn into a CALL
                        instruction(irq_addr_c'range) <= irq_addr_c after delay; -- address to call
                else
                        instruction <= insn after delay;
                end if;
        end process;
 
        alu_select: process(instruction, is_instr)
        begin
                if is_instr.lit = '1' then
                        aluop <= "10101" after delay;
                elsif is_instr.branch0 = '1' then
                        aluop <= (0 => '1', others => '0') after delay;
                elsif is_instr.alu = '1' then
                        aluop <= instruction(12 downto 8) after delay;
                else
                        aluop <= (others => '0') after delay;
                end if;
        end process;
 
        alu_unit: process(
                tos_c, nos, rtos_c,
                din, instruction, aluop,
                io_din,
                vstkp_c, rstkp_c,
                compare,
                irq_en_c)
        begin
                io_re    <= '0'; -- hardware reads can have side effects
                tos_n    <= tos_c;
                irq_en_n <= irq_en_c;
                case aluop is
                -- Register Operations
                when "00000" => tos_n <= tos_c after delay;
                when "00001" => tos_n <= nos after delay;
                when "01011" => tos_n <= rtos_c after delay;
                when "10100" => tos_n <= cpu_id after delay;
                when "10101" => tos_n <= "0" & instruction(14 downto 0) after delay; -- undocumented, may be removed
                -- Logical Operations
                when "00011" => tos_n <= tos_c and nos after delay;
                when "00100" => tos_n <= tos_c or  nos after delay;
                when "00101" => tos_n <= tos_c xor nos after delay;
                when "00110" => tos_n <= not tos_c after delay;
                -- Comparison Operations
                when "00111" => tos_n <= (others => compare.equal) after delay;
                when "01000" => tos_n <= (others => compare.more) after delay;
                when "01111" => tos_n <= (others => compare.umore) after delay;
                when "10011" => tos_n <= (others => compare.zero) after delay;
                -- Arithmetic Operations
                when "01001" => tos_n <= word(unsigned(nos) srl to_integer(unsigned(tos_c(3 downto 0)))) after delay;
                when "01101" => tos_n <= word(unsigned(nos) sll to_integer(unsigned(tos_c(3 downto 0)))) after delay;
                when "00010" => tos_n <= word(unsigned(nos) + unsigned(tos_c)) after delay;
                when "01010" => tos_n <= word(unsigned(tos_c) - 1) after delay;
                -- Input (output is handled elsewhere)
                when "01100" => -- input: 0x4000 - 0x7FFF is external input
                        if tos_c(15 downto 14) /= "00" then
                                tos_n <= io_din after delay;
                                io_re <= '1' after delay;
                        else
                                tos_n <= din after delay;
                        end if;
                -- Stack Depth
                when "01110" => tos_n <= (others => '0') after delay;
                                tos_n(vstkp_c'range) <= std_ulogic_vector(vstkp_c) after delay;
                when "10010" => tos_n <= (others => '0') after delay;
                                tos_n(rstkp_c'range) <= std_ulogic_vector(rstkp_c) after delay;
                -- CPU Status Set/Get
                when "10001" => tos_n    <= (others => '0') after delay;
                                tos_n(0) <= irq_en_c after delay;
                when "10000" => tos_n    <= nos after delay;
                                irq_en_n <= tos_c(0) after delay;
                -- Default/Invalid instructions
                when others  => tos_n <= tos_c after delay;
                                report "Invalid ALU operation: " & integer'image(to_integer(unsigned(aluop))) severity error;
                end case;
        end process;
 
        stack_update: process(
                pc_c, instruction, tos_c,
                vstkp_c, dd,
                rstkp_c, rd,
                is_instr, pc_plus_one, is_interrupt)
        begin
                vstkp_n   <= vstkp_c;
                rstkp_n   <= rstkp_c;
                rstk_we   <= '0';
                rstk_data <= "00" & pc_plus_one & "0";
 
                if is_instr.lit = '1' then
                        assert to_integer(vstkp_c) + 1 < stack_size;
                        vstkp_n   <= vstkp_c + 1 after delay;
                end if;
                if is_instr.alu = '1' then
                        assert (not instruction(6) = '1') or ((to_integer(rstkp_c) + to_integer(signed(rd))) < stack_size);
                        assert ((to_integer(vstkp_c) + to_integer(signed(dd))) < stack_size);
                        rstk_we   <= instruction(6) after delay;
                        rstk_data <= tos_c after delay;
                        vstkp_n   <= vstkp_c + unsigned(dd) after delay;
                        rstkp_n   <= rstkp_c + unsigned(rd) after delay;
                end if;
                if is_instr.branch0 = '1' then
                        vstkp_n   <= (vstkp_c - 1) after delay;
                end if;
                if is_instr.call = '1' then
                        if is_interrupt = '1' then
                                rstk_data <= "00" & pc_c & "0" after delay;
                        end if;
                        rstkp_n   <= rstkp_c + 1 after delay;
                        rstk_we   <= '1' after delay;
                end if;
        end process;
 
        pc_update: process(
                instruction, rtos_c, pc_plus_one,
                is_instr,
                compare.zero)
        begin
                if is_instr.branch = '1' or (is_instr.branch0 = '1' and compare.zero = '1') or is_instr.call = '1' then
                        pc_n <=  instruction(12 downto 0) after delay;
                elsif is_instr.alu = '1' and instruction(4) = '1' then
                        pc_n <=  rtos_c(13 downto 1) after delay;
                else
                        pc_n <= pc_plus_one after delay;
                end if;
        end process;
end architecture;
 

Line No.	Rev	Author	Line
1	3	howe.r.j.8	`-------------------------------------------------------------------------------`
2			`--\| @file h2.vhd`
3			`--\| @brief The H2 Processor: J1 processor translation and extension.`
4			`--\| Moved bit 12 to bit 4 to allow for more ALU instructions.`
5			`--\|`
6			`--\| @author Richard James Howe.`
7	5	howe.r.j.8	`--\| @copyright Copyright 2017, 2019 Richard James Howe.`
8	3	howe.r.j.8	`--\| @license MIT`
9			`--\| @email howe.r.j.89@gmail.com`
10			`--\|`
11	5	howe.r.j.8	`--\| NB. It would be nice to be able to specify the CPU word length with a`
12			`--\| generic, so we could instantiate a 32-bit CPU if we wanted to.`
13	3	howe.r.j.8	`-------------------------------------------------------------------------------`
14
15			`library ieee,work,std;`
16			`use ieee.std_logic_1164.all;`
17			`use ieee.numeric_std.all;`
18
19			`package h2_pkg is`
20			`subtype word is std_ulogic_vector(15 downto 0);`
21			`subtype address is std_ulogic_vector(12 downto 0);`
22
23	5	howe.r.j.8	`constant hardware_cpu_id: word := X"0666";`
24			`constant simulation_cpu_id: word := X"1984";`
25	3	howe.r.j.8
26			`component h2 is`
27			`generic(`
28	5	howe.r.j.8	`asynchronous_reset: boolean := true; -- use asynchronous reset if true, synchronous if false`
29			`delay: time := 0 ns; -- simulation only, gate delay`
30
31	3	howe.r.j.8	`cpu_id: word := hardware_cpu_id; -- Value for the CPU ID instruction`
32			`interrupt_address_length: positive := 3; -- Log_2 of the number of interrupts`
33			`start_address: natural := 0; -- Initial program counter value`
34			`stack_size_log2: positive := 6; -- Log_2 of the Size of the stack`
35	5	howe.r.j.8	`use_interrupts: boolean := true -- Enable Interrupts in the H2 Core`
36			`);`
37	3	howe.r.j.8	`port(`
38			`clk: in std_ulogic;`
39	5	howe.r.j.8	`rst: in std_ulogic; -- active high reset, configurable async/sync`
40			`stop: in std_ulogic; -- Assert high to halt the H2 core`
41	3	howe.r.j.8
42			`-- IO interface`
43			`io_wr: out std_ulogic; -- Output Write Enable`
44			`io_re: out std_ulogic; -- Input Read Enable`
45	5	howe.r.j.8	`io_din: in word; -- Data Input from register`
46			`io_dout: out word; -- Data Output to register`
47			`io_daddr: out word; -- Data Address for I/O action`
48	3	howe.r.j.8
49			`irq: in std_ulogic; -- Interrupt Request`
50			`irq_addr: in std_ulogic_vector(interrupt_address_length - 1 downto 0); -- Address to jump to on Interrupt Request`
51
52			`-- RAM interface, Dual port`
53			`pc: out address; -- program counter`
54			`insn: in word; -- instruction`
55
56			`dwe: out std_ulogic; -- RAM data write enable`
57			`dre: out std_ulogic; -- RAM data read enable`
58			`din: in word; -- RAM data input`
59			`dout: out word; -- RAM data output`
60			`daddr: out address); -- RAM address`
61			`end component;`
62			`end;`
63
64			`library ieee,work,std;`
65			`use ieee.std_logic_1164.all;`
66			`use ieee.numeric_std.all;`
67			`use ieee.math_real.all; -- only needed for calculations relating to generics`
68			`use work.h2_pkg.all;`
69
70			`entity h2 is`
71			`generic(`
72	5	howe.r.j.8	`asynchronous_reset: boolean := true; -- use asynchronous reset if true, synchronous if false`
73			`delay: time := 0 ns; -- simulation only, gate delay`
74
75	3	howe.r.j.8	`cpu_id: word := hardware_cpu_id; -- Value for the CPU ID instruction`
76			`interrupt_address_length: positive := 3; -- Log_2 of the number of interrupts`
77			`start_address: natural := 0; -- Initial program counter value`
78			`stack_size_log2: positive := 6; -- Log_2 of the Size of the stack`
79			`use_interrupts: boolean := true); -- Enable Interrupts in the H2 Core`
80			`port(`
81			`clk: in std_ulogic;`
82			`rst: in std_ulogic;`
83
84			`-- IO interface`
85			`stop: in std_ulogic; -- Assert high to halt the H2 core`
86
87			`io_wr: out std_ulogic; -- Output Write Enable`
88			`io_re: out std_ulogic; -- Input Read Enable`
89			`io_din: in word; -- Data Input from register`
90			`io_dout: out word; -- Data Output to register`
91			`io_daddr: out word; -- Data Address for I/O action`
92
93			`irq: in std_ulogic; -- Interrupt Request`
94			`irq_addr: in std_ulogic_vector(interrupt_address_length - 1 downto 0); -- Address to jump to on Interrupt Request`
95
96			`-- RAM interface, Dual port`
97			`pc: out address; -- program counter`
98			`insn: in word; -- instruction`
99
100			`dwe: out std_ulogic; -- RAM data write enable`
101			`dre: out std_ulogic; -- RAM data read enable`
102			`din: in word; -- RAM data input`
103			`dout: out word; -- RAM data output`
104			`daddr: out address); -- RAM address`
105			`end;`
106
107			`architecture rtl of h2 is`
108			`signal pc_c: address := std_ulogic_vector(to_unsigned(start_address, address'length));`
109			`signal pc_n: address := (others => '0');`
110			`signal pc_plus_one: address := (others => '0');`
111
112			`constant stack_size: integer := 2 ** stack_size_log2;`
113			`type stack_type is array (stack_size - 1 downto 0) of word;`
114			`subtype depth is unsigned(stack_size_log2 - 1 downto 0);`
115
116			`signal vstkp_c, vstkp_n: depth := (others => '0'); -- variable stack pointer`
117			`signal vstk_ram: stack_type := (others => (others => '0')); -- variable stack`
118			`signal dstk_we: std_ulogic := '0'; -- variable stack write enable`
119			`signal dd: depth := (others => '0'); -- variable stack delta`
120
121			`signal rstkp_c, rstkp_n: depth := (others => '0'); -- return stack pointer`
122			`signal rstk_ram: stack_type := (others => (others => '0')); -- return stack`
123			`signal rstk_we: std_ulogic := '0'; -- return stack write enable`
124			`signal rd: depth := (others => '0'); -- return stack delta`
125
126			`type instruction_info_type is record`
127			`alu: std_ulogic;`
128			`lit: std_ulogic;`
129			`branch: std_ulogic;`
130			`branch0: std_ulogic;`
131			`call: std_ulogic;`
132			`end record;`
133
134			`signal is_instr: instruction_info_type := ('0', '0', '0', '0', '0');`
135			`signal is_interrupt: std_ulogic := '0';`
136			`signal is_ram_write: std_ulogic := '0';`
137
138			`type compare_type is record`
139	5	howe.r.j.8	`more: std_ulogic; -- signed greater than; T > N?`
140			`equal: std_ulogic; -- equality; N = T?`
141			`umore: std_ulogic; -- unsigned greater than; T > N?`
142			`zero: std_ulogic; -- zero test; T = 0?`
143	3	howe.r.j.8	`end record;`
144
145			`signal compare: compare_type := ('0', '0', '0', '0');`
146
147	5	howe.r.j.8	`signal stop_c: std_ulogic := '1'; -- processor wait state register (current)`
148			`signal stop_n: std_ulogic := '0'; -- processor wait state register (next)`
149	3	howe.r.j.8
150	5	howe.r.j.8	`signal irq_en_c, irq_en_n: std_ulogic := '0'; -- interrupt enable`
151			`signal irq_c, irq_n: std_ulogic := '0'; -- pending interrupt request`
152			`signal irq_addr_c, irq_addr_n: std_ulogic_vector(irq_addr'range) := (others => '0'); -- address of pending interrupt request vector`
153
154	3	howe.r.j.8	`signal tos_c, tos_n: word := (others => '0'); -- top of stack`
155			`signal nos: word := (others => '0'); -- next on stack`
156			`signal rtos_c: word := (others => '0'); -- top of return stack`
157			`signal rstk_data: word := (others => '0'); -- return stack input`
158			`signal aluop: std_ulogic_vector(4 downto 0) := (others => '0'); -- ALU operation`
159
160	5	howe.r.j.8	`signal instruction: word := (others => '0'); -- processed 'insn'`
161	3	howe.r.j.8	`begin`
162			`assert stack_size > 4 report "stack size too small: " & integer'image(stack_size) severity failure;`
163	5	howe.r.j.8	`-- assert dd /= "10" severity warning; -- valid, but odd (now used)`
164	3	howe.r.j.8
165	5	howe.r.j.8	`is_instr.branch <= '1' when instruction(15 downto 13) = "000" else '0' after delay;`
166			`is_instr.branch0 <= '1' when instruction(15 downto 13) = "001" else '0' after delay;`
167			`is_instr.call <= '1' when instruction(15 downto 13) = "010" else '0' after delay;`
168			`is_instr.alu <= '1' when instruction(15 downto 13) = "011" else '0' after delay;`
169			`is_instr.lit <= '1' when instruction(15) = '1' else '0' after delay;`
170			`is_ram_write <= '1' when is_instr.alu = '1' and instruction(5) = '1' else '0' after delay;`
171			`compare.more <= '1' when signed(tos_c) > signed(nos) else '0' after delay;`
172			`compare.umore <= '1' when unsigned(tos_c) > unsigned(nos) else '0' after delay;`
173			`compare.equal <= '1' when tos_c = nos else '0' after delay;`
174			`compare.zero <= '1' when unsigned(tos_c(15 downto 0)) = 0 else '0' after delay;`
175			`nos <= vstk_ram(to_integer(vstkp_c)) after delay;`
176			`rtos_c <= rstk_ram(to_integer(rstkp_c)) after delay;`
177			`pc <= pc_n after delay;`
178			`pc_plus_one <= std_ulogic_vector(unsigned(pc_c) + 1) after delay;`
179			`dout <= nos after delay;`
180			`daddr <= tos_c(13 downto 1) when is_ram_write = '1' else tos_n(13 downto 1) after delay;`
181			`dwe <= '1' when is_ram_write = '1' and tos_c(15 downto 14) = "00" else '0' after delay;`
182			`dre <= '1' when tos_n(15 downto 14) = "00" else '0' after delay;`
183			`io_dout <= nos after delay;`
184			`io_daddr <= tos_c after delay;`
185			`io_wr <= '1' when is_ram_write = '1' and tos_c(15 downto 14) /= "00" else '0' after delay;`
186			`is_interrupt <= '1' when irq_c = '1' and irq_en_c = '1' and use_interrupts else '0' after delay;`
187			`irq_n <= irq after delay;`
188			`irq_addr_n <= irq_addr after delay;`
189			`stop_n <= stop after delay;`
190			`dd(0) <= instruction(0) after delay;`
191			`rd(0) <= instruction(2) after delay;`
192			`dd(dd'high downto 1) <= (others => '1') when instruction(1) = '1' else (others => '0') after delay; -- sign extend`
193			`rd(rd'high downto 1) <= (others => '1') when instruction(3) = '1' else (others => '0') after delay; -- sign extend`
194			`dstk_we <= '1' when (is_instr.lit = '1' or (is_instr.alu = '1' and instruction(7) = '1')) else '0' after delay;`
195	3	howe.r.j.8
196			`next_state: process(clk, rst)`
197	5	howe.r.j.8	`procedure reset is`
198			`begin`
199			`pc_c <= std_ulogic_vector(to_unsigned(start_address, pc_c'length)) after delay;`
200			`stop_c <= '1' after delay; -- start in stopped state`
201			`vstkp_c <= (others => '0') after delay;`
202			`rstkp_c <= (others => '0') after delay;`
203			`tos_c <= (others => '0') after delay;`
204			`irq_addr_c <= (others => '0') after delay;`
205			`irq_en_c <= '0' after delay;`
206			`irq_c <= '0' after delay;`
207			`end reset;`
208	3	howe.r.j.8	`begin`
209	5	howe.r.j.8	`if rst = '1' and asynchronous_reset then`
210			`reset;`
211	3	howe.r.j.8	`elsif rising_edge(clk) then`
212	5	howe.r.j.8	`if rst = '1' and not asynchronous_reset then`
213			`reset;`
214			`else`
215			`assert stop_c = '0' or (stop_c = '1' and is_instr.branch = '1') severity failure;`
216			`assert (not rstk_we = '1') or (((is_instr.alu = '1' and instruction(6) = '1') or is_instr.call = '1')) severity failure;`
217			`assert (not dstk_we = '1') or (((is_instr.alu = '1' and instruction(7) = '1') or is_instr.lit = '1')) severity failure;`
218
219			`pc_c <= pc_n after delay;`
220			`stop_c <= stop_n after delay;`
221			`vstkp_c <= vstkp_n after delay;`
222			`rstkp_c <= rstkp_n after delay;`
223			`tos_c <= tos_n after delay;`
224			`irq_addr_c <= irq_addr_n after delay;`
225			`irq_en_c <= irq_en_n after delay;`
226			`irq_c <= irq_n after delay;`
227			`end if;`
228	3	howe.r.j.8	`end if;`
229			`end process;`
230
231			`stack_write: process(clk)`
232			`begin`
233			`if rising_edge(clk) then`
234			`if dstk_we = '1' then`
235	5	howe.r.j.8	`vstk_ram(to_integer(vstkp_n)) <= tos_c after delay;`
236	3	howe.r.j.8	`end if;`
237			`if rstk_we = '1' then`
238	5	howe.r.j.8	`rstk_ram(to_integer(rstkp_n)) <= rstk_data after delay;`
239	3	howe.r.j.8	`end if;`
240			`end if;`
241			`end process;`
242
243	5	howe.r.j.8	`decode: process(insn, irq_addr_c, is_interrupt, stop_c, pc_c)`
244	3	howe.r.j.8	`begin`
245	5	howe.r.j.8	`if stop_c = '1' then -- assert a BRANCH instruction to current location on CPU halt`
246			`instruction <= "000" & pc_c after delay;`
247			`elsif is_interrupt = '1' then -- assemble a CALL instruction on interrupt`
248			`instruction <= (others => '0') after delay;`
249			`instruction(15 downto 13) <= "010" after delay; -- turn into a CALL`
250			`instruction(irq_addr_c'range) <= irq_addr_c after delay; -- address to call`
251			`else`
252			`instruction <= insn after delay;`
253			`end if;`
254			`end process;`
255
256			`alu_select: process(instruction, is_instr)`
257			`begin`
258			`if is_instr.lit = '1' then`
259			`aluop <= "10101" after delay;`
260	3	howe.r.j.8	`elsif is_instr.branch0 = '1' then`
261	5	howe.r.j.8	`aluop <= (0 => '1', others => '0') after delay;`
262	3	howe.r.j.8	`elsif is_instr.alu = '1' then`
263	5	howe.r.j.8	`aluop <= instruction(12 downto 8) after delay;`
264	3	howe.r.j.8	`else`
265	5	howe.r.j.8	`aluop <= (others => '0') after delay;`
266	3	howe.r.j.8	`end if;`
267			`end process;`
268
269	5	howe.r.j.8	`alu_unit: process(`
270	3	howe.r.j.8	`tos_c, nos, rtos_c,`
271	5	howe.r.j.8	`din, instruction, aluop,`
272	3	howe.r.j.8	`io_din,`
273			`vstkp_c, rstkp_c,`
274			`compare,`
275	5	howe.r.j.8	`irq_en_c)`
276	3	howe.r.j.8	`begin`
277	5	howe.r.j.8	`io_re <= '0'; -- hardware reads can have side effects`
278			`tos_n <= tos_c;`
279			`irq_en_n <= irq_en_c;`
280	3	howe.r.j.8	`case aluop is`
281	5	howe.r.j.8	`-- Register Operations`
282			`when "00000" => tos_n <= tos_c after delay;`
283			`when "00001" => tos_n <= nos after delay;`
284			`when "01011" => tos_n <= rtos_c after delay;`
285			`when "10100" => tos_n <= cpu_id after delay;`
286			`when "10101" => tos_n <= "0" & instruction(14 downto 0) after delay; -- undocumented, may be removed`
287			`-- Logical Operations`
288			`when "00011" => tos_n <= tos_c and nos after delay;`
289			`when "00100" => tos_n <= tos_c or nos after delay;`
290			`when "00101" => tos_n <= tos_c xor nos after delay;`
291			`when "00110" => tos_n <= not tos_c after delay;`
292			`-- Comparison Operations`
293			`when "00111" => tos_n <= (others => compare.equal) after delay;`
294			`when "01000" => tos_n <= (others => compare.more) after delay;`
295			`when "01111" => tos_n <= (others => compare.umore) after delay;`
296			`when "10011" => tos_n <= (others => compare.zero) after delay;`
297			`-- Arithmetic Operations`
298			`when "01001" => tos_n <= word(unsigned(nos) srl to_integer(unsigned(tos_c(3 downto 0)))) after delay;`
299			`when "01101" => tos_n <= word(unsigned(nos) sll to_integer(unsigned(tos_c(3 downto 0)))) after delay;`
300			`when "00010" => tos_n <= word(unsigned(nos) + unsigned(tos_c)) after delay;`
301			`when "01010" => tos_n <= word(unsigned(tos_c) - 1) after delay;`
302			`-- Input (output is handled elsewhere)`
303			`when "01100" => -- input: 0x4000 - 0x7FFF is external input`
304	3	howe.r.j.8	`if tos_c(15 downto 14) /= "00" then`
305	5	howe.r.j.8	`tos_n <= io_din after delay;`
306			`io_re <= '1' after delay;`
307	3	howe.r.j.8	`else`
308	5	howe.r.j.8	`tos_n <= din after delay;`
309	3	howe.r.j.8	`end if;`
310	5	howe.r.j.8	`-- Stack Depth`
311			`when "01110" => tos_n <= (others => '0') after delay;`
312			`tos_n(vstkp_c'range) <= std_ulogic_vector(vstkp_c) after delay;`
313			`when "10010" => tos_n <= (others => '0') after delay;`
314			`tos_n(rstkp_c'range) <= std_ulogic_vector(rstkp_c) after delay;`
315			`-- CPU Status Set/Get`
316			`when "10001" => tos_n <= (others => '0') after delay;`
317			`tos_n(0) <= irq_en_c after delay;`
318			`when "10000" => tos_n <= nos after delay;`
319			`irq_en_n <= tos_c(0) after delay;`
320			`-- Default/Invalid instructions`
321			`when others => tos_n <= tos_c after delay;`
322	3	howe.r.j.8	`report "Invalid ALU operation: " & integer'image(to_integer(unsigned(aluop))) severity error;`
323			`end case;`
324			`end process;`
325
326			`stack_update: process(`
327	5	howe.r.j.8	`pc_c, instruction, tos_c,`
328	3	howe.r.j.8	`vstkp_c, dd,`
329			`rstkp_c, rd,`
330	5	howe.r.j.8	`is_instr, pc_plus_one, is_interrupt)`
331	3	howe.r.j.8	`begin`
332			`vstkp_n <= vstkp_c;`
333			`rstkp_n <= rstkp_c;`
334			`rstk_we <= '0';`
335			`rstk_data <= "00" & pc_plus_one & "0";`
336
337	5	howe.r.j.8	`if is_instr.lit = '1' then`
338	3	howe.r.j.8	`assert to_integer(vstkp_c) + 1 < stack_size;`
339	5	howe.r.j.8	`vstkp_n <= vstkp_c + 1 after delay;`
340	3	howe.r.j.8	`end if;`
341	5	howe.r.j.8	`if is_instr.alu = '1' then`
342			`assert (not instruction(6) = '1') or ((to_integer(rstkp_c) + to_integer(signed(rd))) < stack_size);`
343			`assert ((to_integer(vstkp_c) + to_integer(signed(dd))) < stack_size);`
344			`rstk_we <= instruction(6) after delay;`
345			`rstk_data <= tos_c after delay;`
346			`vstkp_n <= vstkp_c + unsigned(dd) after delay;`
347			`rstkp_n <= rstkp_c + unsigned(rd) after delay;`
348			`end if;`
349			`if is_instr.branch0 = '1' then`
350			`vstkp_n <= (vstkp_c - 1) after delay;`
351			`end if;`
352			`if is_instr.call = '1' then`
353			`if is_interrupt = '1' then`
354			`rstk_data <= "00" & pc_c & "0" after delay;`
355			`end if;`
356			`rstkp_n <= rstkp_c + 1 after delay;`
357			`rstk_we <= '1' after delay;`
358			`end if;`
359	3	howe.r.j.8	`end process;`
360
361			`pc_update: process(`
362	5	howe.r.j.8	`instruction, rtos_c, pc_plus_one,`
363	3	howe.r.j.8	`is_instr,`
364	5	howe.r.j.8	`compare.zero)`
365	3	howe.r.j.8	`begin`
366	5	howe.r.j.8	`if is_instr.branch = '1' or (is_instr.branch0 = '1' and compare.zero = '1') or is_instr.call = '1' then`
367			`pc_n <= instruction(12 downto 0) after delay;`
368			`elsif is_instr.alu = '1' and instruction(4) = '1' then`
369			`pc_n <= rtos_c(13 downto 1) after delay;`
370			`else`
371			`pc_n <= pc_plus_one after delay;`
372	3	howe.r.j.8	`end if;`
373			`end process;`
374			`end architecture;`
375

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