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howe.r.j.8 |
-------------------------------------------------------------------------------
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--| @file h2.vhd
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--| @brief The H2 Processor: J1 processor translation and extension.
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--| Moved bit 12 to bit 4 to allow for more ALU instructions.
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--|
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--| @author Richard James Howe.
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--| @copyright Copyright 2017 Richard James Howe.
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--| @license MIT
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--| @email howe.r.j.89@gmail.com
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--|
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-------------------------------------------------------------------------------
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library ieee,work,std;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package h2_pkg is
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subtype word is std_ulogic_vector(15 downto 0);
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subtype address is std_ulogic_vector(12 downto 0);
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constant hardware_cpu_id: word := X"CAFE";
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constant simulation_cpu_id: word := X"DEAD";
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component h2 is
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generic(
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cpu_id: word := hardware_cpu_id; -- Value for the CPU ID instruction
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interrupt_address_length: positive := 3; -- Log_2 of the number of interrupts
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start_address: natural := 0; -- Initial program counter value
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stack_size_log2: positive := 6; -- Log_2 of the Size of the stack
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use_interrupts: boolean := true); -- Enable Interrupts in the H2 Core
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port(
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clk: in std_ulogic;
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rst: in std_ulogic;
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-- IO interface
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stop: in std_ulogic; -- Assert high to halt the H2 core
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io_wr: out std_ulogic; -- Output Write Enable
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io_re: out std_ulogic; -- Input Read Enable
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io_din: in word; -- Data Input from register
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io_dout: out word; -- Data Output to register
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io_daddr: out word; -- Data Address for I/O action
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irq: in std_ulogic; -- Interrupt Request
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irq_addr: in std_ulogic_vector(interrupt_address_length - 1 downto 0); -- Address to jump to on Interrupt Request
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-- RAM interface, Dual port
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pc: out address; -- program counter
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insn: in word; -- instruction
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dwe: out std_ulogic; -- RAM data write enable
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dre: out std_ulogic; -- RAM data read enable
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din: in word; -- RAM data input
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dout: out word; -- RAM data output
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daddr: out address); -- RAM address
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end component;
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end;
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library ieee,work,std;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all; -- only needed for calculations relating to generics
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use work.h2_pkg.all;
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entity h2 is
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generic(
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cpu_id: word := hardware_cpu_id; -- Value for the CPU ID instruction
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interrupt_address_length: positive := 3; -- Log_2 of the number of interrupts
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start_address: natural := 0; -- Initial program counter value
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stack_size_log2: positive := 6; -- Log_2 of the Size of the stack
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use_interrupts: boolean := true); -- Enable Interrupts in the H2 Core
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port(
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clk: in std_ulogic;
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rst: in std_ulogic;
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-- IO interface
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stop: in std_ulogic; -- Assert high to halt the H2 core
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io_wr: out std_ulogic; -- Output Write Enable
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io_re: out std_ulogic; -- Input Read Enable
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io_din: in word; -- Data Input from register
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io_dout: out word; -- Data Output to register
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io_daddr: out word; -- Data Address for I/O action
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irq: in std_ulogic; -- Interrupt Request
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irq_addr: in std_ulogic_vector(interrupt_address_length - 1 downto 0); -- Address to jump to on Interrupt Request
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-- RAM interface, Dual port
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pc: out address; -- program counter
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insn: in word; -- instruction
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dwe: out std_ulogic; -- RAM data write enable
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dre: out std_ulogic; -- RAM data read enable
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din: in word; -- RAM data input
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dout: out word; -- RAM data output
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daddr: out address); -- RAM address
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end;
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architecture rtl of h2 is
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signal pc_c: address := std_ulogic_vector(to_unsigned(start_address, address'length));
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signal pc_n: address := (others => '0');
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signal pc_plus_one: address := (others => '0');
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constant stack_size: integer := 2 ** stack_size_log2;
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type stack_type is array (stack_size - 1 downto 0) of word;
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subtype depth is unsigned(stack_size_log2 - 1 downto 0);
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signal vstkp_c, vstkp_n: depth := (others => '0'); -- variable stack pointer
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signal vstk_ram: stack_type := (others => (others => '0')); -- variable stack
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signal dstk_we: std_ulogic := '0'; -- variable stack write enable
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signal dd: depth := (others => '0'); -- variable stack delta
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signal rstkp_c, rstkp_n: depth := (others => '0'); -- return stack pointer
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signal rstk_ram: stack_type := (others => (others => '0')); -- return stack
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signal rstk_we: std_ulogic := '0'; -- return stack write enable
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signal rd: depth := (others => '0'); -- return stack delta
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type instruction_info_type is record
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alu: std_ulogic;
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lit: std_ulogic;
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branch: std_ulogic;
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branch0: std_ulogic;
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call: std_ulogic;
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end record;
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signal is_instr: instruction_info_type := ('0', '0', '0', '0', '0');
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signal is_interrupt: std_ulogic := '0';
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signal is_ram_write: std_ulogic := '0';
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type compare_type is record
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more: std_ulogic;
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equal: std_ulogic;
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umore: std_ulogic;
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zero: std_ulogic;
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end record;
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signal compare: compare_type := ('0', '0', '0', '0');
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signal int_en_c, int_en_n: std_ulogic := '0'; -- interrupt enable
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signal irq_c, irq_n: std_ulogic := '0'; -- interrupt request
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signal irq_addr_c, irq_addr_n: std_ulogic_vector(irq_addr'range) := (others => '0');
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signal tos_c, tos_n: word := (others => '0'); -- top of stack
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signal nos: word := (others => '0'); -- next on stack
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signal rtos_c: word := (others => '0'); -- top of return stack
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signal rstk_data: word := (others => '0'); -- return stack input
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signal aluop: std_ulogic_vector(4 downto 0) := (others => '0'); -- ALU operation
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begin
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assert stack_size > 4 report "stack size too small: " & integer'image(stack_size) severity failure;
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is_instr.alu <= '1' when insn(15 downto 13) = "011" else '0';
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is_instr.lit <= '1' when insn(15) = '1' else '0';
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is_instr.branch <= '1' when insn(15 downto 13) = "000" else '0';
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is_instr.branch0 <= '1' when insn(15 downto 13) = "001" else '0';
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is_instr.call <= '1' when insn(15 downto 13) = "010" else '0';
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is_interrupt <= '1' when irq_c = '1' and int_en_c = '1' and use_interrupts else '0';
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is_ram_write <= '1' when is_interrupt = '0' and is_instr.alu = '1' and insn(5) = '1' else '0';
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compare.more <= '1' when signed(tos_c) > signed(nos) else '0';
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compare.umore <= '1' when unsigned(tos_c) > unsigned(nos) else '0';
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compare.equal <= '1' when tos_c = nos else '0';
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compare.zero <= '1' when unsigned(tos_c(15 downto 0)) = 0 else '0';
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nos <= vstk_ram(to_integer(vstkp_c));
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rtos_c <= rstk_ram(to_integer(rstkp_c));
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pc <= pc_n;
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pc_plus_one <= std_ulogic_vector(unsigned(pc_c) + 1);
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dout <= nos;
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daddr <= tos_c(13 downto 1) when is_ram_write = '1' else tos_n(13 downto 1);
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dwe <= '1' when is_ram_write = '1' and tos_c(15 downto 14) = "00" else '0';
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dre <= '1' when tos_n(15 downto 14) = "00" else '0';
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io_dout <= nos;
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io_daddr <= tos_c;
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io_wr <= '1' when is_ram_write = '1' and tos_c(15 downto 14) /= "00" else '0';
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dd <= (0 => insn(0), others => insn(1)); -- sign extend
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rd <= (0 => insn(2), others => insn(3)); -- sign extend
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dstk_we <= '1' when is_interrupt = '0' and (is_instr.lit = '1' or (is_instr.alu = '1' and insn(7) = '1')) else '0';
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next_state: process(clk, rst)
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begin
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if rst = '1' then
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vstkp_c <= (others => '0');
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rstkp_c <= (others => '0');
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pc_c <= std_ulogic_vector(to_unsigned(start_address, pc_c'length));
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tos_c <= (others => '0');
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int_en_c <= '0';
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irq_c <= '0';
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irq_addr_c <= (others => '0');
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elsif rising_edge(clk) then
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vstkp_c <= vstkp_n;
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rstkp_c <= rstkp_n;
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pc_c <= pc_n;
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tos_c <= tos_n;
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int_en_c <= int_en_n;
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irq_c <= irq_n;
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irq_addr_c <= irq_addr_n;
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end if;
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end process;
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stack_write: process(clk)
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begin
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if rising_edge(clk) then
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if dstk_we = '1' then
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vstk_ram(to_integer(vstkp_n)) <= tos_c;
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end if;
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if rstk_we = '1' then
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rstk_ram(to_integer(rstkp_n)) <= rstk_data;
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end if;
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end if;
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end process;
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alu_select: process(insn, is_instr, is_interrupt)
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begin
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if is_interrupt = '1' or is_instr.call = '1' or is_instr.branch = '1' then
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| 216 |
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aluop <= (others => '0');
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| 217 |
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elsif is_instr.branch0 = '1' then
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| 218 |
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aluop <= (0 => '1', others => '0');
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elsif is_instr.alu = '1' then
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aluop <= insn(12 downto 8);
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else
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aluop <= (others => '0');
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end if;
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end process;
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alu: process(
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is_instr.lit,
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tos_c, nos, rtos_c,
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din, insn, aluop,
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io_din,
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vstkp_c, rstkp_c,
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compare,
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int_en_c,
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stop)
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| 235 |
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begin
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| 236 |
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io_re <= '0'; -- hardware reads can have side effects
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| 237 |
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tos_n <= tos_c;
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| 238 |
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int_en_n <= int_en_c;
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| 239 |
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if stop = '1' then
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| 240 |
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null;
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| 241 |
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elsif is_instr.lit = '1' then
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| 242 |
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tos_n <= "0" & insn(14 downto 0);
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| 243 |
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else
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| 244 |
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case aluop is
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| 245 |
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when "00000" => tos_n <= tos_c;
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| 246 |
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when "00001" => tos_n <= nos;
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| 247 |
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when "01011" => tos_n <= rtos_c;
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| 248 |
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when "10100" => tos_n <= cpu_id;
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| 249 |
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| 250 |
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when "00011" => tos_n <= tos_c and nos;
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| 251 |
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when "00100" => tos_n <= tos_c or nos;
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| 252 |
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when "00101" => tos_n <= tos_c xor nos;
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| 253 |
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when "00110" => tos_n <= not tos_c;
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| 254 |
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| 255 |
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when "00111" => tos_n <= (others => compare.equal);
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| 256 |
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when "01000" => tos_n <= (others => compare.more);
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| 257 |
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when "01111" => tos_n <= (others => compare.umore);
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| 258 |
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when "10011" => tos_n <= (others => compare.zero);
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| 259 |
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| 260 |
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when "01001" => tos_n <= word(unsigned(nos) srl to_integer(unsigned(tos_c(3 downto 0))));
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| 261 |
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when "01101" => tos_n <= word(unsigned(nos) sll to_integer(unsigned(tos_c(3 downto 0))));
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| 262 |
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when "00010" => tos_n <= word(unsigned(nos) + unsigned(tos_c));
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| 263 |
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when "01010" => tos_n <= word(unsigned(tos_c) - 1);
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| 264 |
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| 265 |
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when "01100" =>
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| 266 |
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-- input: 0x4000 - 0x7FFF is external input
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| 267 |
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if tos_c(15 downto 14) /= "00" then
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| 268 |
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tos_n <= io_din;
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| 269 |
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io_re <= '1';
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| 270 |
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else
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| 271 |
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tos_n <= din;
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| 272 |
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end if;
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| 273 |
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when "01110" => tos_n <= (others => '0');
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| 274 |
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tos_n(vstkp_c'range) <= std_ulogic_vector(vstkp_c);
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| 275 |
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when "10010" => tos_n <= (others => '0');
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| 276 |
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tos_n(rstkp_c'range) <= std_ulogic_vector(rstkp_c);
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| 277 |
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| 278 |
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when "10001" => tos_n <= (others => int_en_c);
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| 279 |
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when "10000" => int_en_n <= tos_c(0);
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| 280 |
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| 281 |
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when others => tos_n <= tos_c;
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| 282 |
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report "Invalid ALU operation: " & integer'image(to_integer(unsigned(aluop))) severity error;
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| 283 |
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end case;
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| 284 |
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end if;
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| 285 |
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end process;
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| 286 |
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| 287 |
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stack_update: process(
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| 288 |
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pc_c, insn, tos_c,
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| 289 |
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vstkp_c, dd,
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| 290 |
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rstkp_c, rd,
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| 291 |
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is_instr, is_interrupt, pc_plus_one, stop)
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| 292 |
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begin
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| 293 |
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vstkp_n <= vstkp_c;
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| 294 |
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rstkp_n <= rstkp_c;
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| 295 |
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rstk_we <= '0';
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| 296 |
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rstk_data <= "00" & pc_plus_one & "0";
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| 297 |
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| 298 |
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if stop = '1' then -- Do nothing
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| 299 |
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null;
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| 300 |
|
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elsif is_interrupt = '1' then -- Interrupts are similar to a call
|
| 301 |
|
|
rstkp_n <= rstkp_c + 1;
|
| 302 |
|
|
rstk_we <= '1';
|
| 303 |
|
|
rstk_data <= "00" & pc_c & "0";
|
| 304 |
|
|
elsif is_instr.lit = '1' then
|
| 305 |
|
|
assert to_integer(vstkp_c) + 1 < stack_size;
|
| 306 |
|
|
vstkp_n <= vstkp_c + 1;
|
| 307 |
|
|
elsif is_instr.alu = '1' then
|
| 308 |
|
|
assert (not insn(6) = '1') or ((to_integer(rstkp_c) + to_integer(signed(rd))) < stack_size);
|
| 309 |
|
|
assert ((to_integer(vstkp_c) + to_integer(signed(dd))) < stack_size);
|
| 310 |
|
|
rstk_we <= insn(6);
|
| 311 |
|
|
rstk_data <= tos_c;
|
| 312 |
|
|
vstkp_n <= vstkp_c + unsigned(dd);
|
| 313 |
|
|
rstkp_n <= rstkp_c + unsigned(rd);
|
| 314 |
|
|
elsif is_instr.branch0 = '1' then
|
| 315 |
|
|
vstkp_n <= vstkp_c - 1;
|
| 316 |
|
|
elsif is_instr.call = '1' then
|
| 317 |
|
|
rstkp_n <= rstkp_c + 1;
|
| 318 |
|
|
rstk_we <= '1';
|
| 319 |
|
|
end if;
|
| 320 |
|
|
end process;
|
| 321 |
|
|
|
| 322 |
|
|
pc_update: process(
|
| 323 |
|
|
pc_c,insn, rtos_c, pc_plus_one,
|
| 324 |
|
|
is_instr,
|
| 325 |
|
|
is_interrupt, irq_c, irq_addr_c, irq_addr,irq,
|
| 326 |
|
|
compare.zero,
|
| 327 |
|
|
stop)
|
| 328 |
|
|
begin
|
| 329 |
|
|
pc_n <= pc_c;
|
| 330 |
|
|
irq_n <= irq_c;
|
| 331 |
|
|
irq_addr_n <= irq_addr_c;
|
| 332 |
|
|
irq_n <= irq;
|
| 333 |
|
|
|
| 334 |
|
|
if irq = '1' then irq_addr_n <= irq_addr; end if;
|
| 335 |
|
|
|
| 336 |
|
|
if stop = '1' then
|
| 337 |
|
|
null;
|
| 338 |
|
|
elsif is_interrupt = '1' then -- Update PC on interrupt
|
| 339 |
|
|
irq_n <= '0';
|
| 340 |
|
|
irq_addr_n <= (others => '0');
|
| 341 |
|
|
pc_n <= (others => '0');
|
| 342 |
|
|
pc_n(irq_addr'range) <= irq_addr_c;
|
| 343 |
|
|
else -- Update PC on normal operations
|
| 344 |
|
|
pc_n <= pc_plus_one;
|
| 345 |
|
|
if is_instr.branch = '1' or (is_instr.branch0 = '1' and compare.zero = '1') or is_instr.call = '1' then
|
| 346 |
|
|
pc_n <= insn(12 downto 0);
|
| 347 |
|
|
elsif is_instr.alu = '1' and insn(4) = '1' then
|
| 348 |
|
|
pc_n <= rtos_c(13 downto 1);
|
| 349 |
|
|
end if;
|
| 350 |
|
|
end if;
|
| 351 |
|
|
end process;
|
| 352 |
|
|
end architecture;
|
| 353 |
|
|
|
