OpenCores
URL https://opencores.org/ocsvn/forwardcom/forwardcom/trunk

Subversion Repositories forwardcom

[/] [forwardcom/] [manual/] [fwc_softcore.tex] - Blame information for rev 156

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 156 Agner
% chapter included in forwardcom.tex
2
\documentclass[forwardcom.tex]{subfiles}
3
\begin{document}
4
\RaggedRight
5
 
6
\chapter{Softcore}
7
A hardware implementation of ForwardCom as an FPGA softcore is available at \\
8
\href{https://github.com/ForwardCom/softcoreA}{github.com/ForwardCom/softcoreA}
9
\vv
10
 
11
\subsubsection{Features of softcore model A version 1.00}
12
\begin{itemize}
13
\item Runs on Nexys A7-100T FPGA board
14
\item Maximum clock frequency 50 - 70 MHz, depending on configuration
15
\item 32-bit or 64-bit registers
16
\item Can execute one instruction per clock cycle
17
\item Data memory 32 kB. Code memory 64 kB. Call stack 1023 entries.
18
\item Implements all integer instructions, except multiplication, division, push, pop
19
\item Implements all instruction formats and all addressing modes defined by the ForwardCom standard version 1.11.
20
\item No vector registers yet. No floating point instructions
21
\item No system calls, no memory protection. Useful for embedded designs
22
\item Memory reads and writes must be aligned
23
\item RS232 serial interface for standard input and output
24
\item On-chip loader (uses 2 kB code memory)
25
\item On-chip debug interface
26
\item On-chip event counter
27
\item Code examples and test suite provided
28
\end{itemize}
29
\vv
30
 
31
Please see the
32
\href{https://github.com/ForwardCom/softcoreA/raw/main/softcore_A.pdf}{manual for the softcore}
33
for details and documentation.
34
\vv
35
 
36
\end{document}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.