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[/] [forwardcom/] [trunk/] [code_memory.sv] - Blame information for rev 101

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1 14 Agner
//////////////////////////////////////////////////////////////////////////////////
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// Engineer: Agner Fog
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//
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// Create Date:       2020-05-05
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// Last modified:     2021-08-02
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// Module Name:       code_cache
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// Project Name:      ForwardCom soft core
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// Target Devices:    Artix 7
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// Tool Versions:     Vivado v. 2020.1
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// License:           CERN-OHL-W v. 2 or later
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// Description:       on-chip code memory or code cache
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//
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//////////////////////////////////////////////////////////////////////////////////
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`include "defines.vh"
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// It takes two clock cycles to fetch data from on-chip ram,
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// Attempts to fetch in one cycle, using negedge or latch failed for timing reasons
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// code memory, 1024*64 bits,
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module code_memory (
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    input clock,                                 // clock
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    input clock_enable,                          // clock enable. Used when single-stepping
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    input read_enable,                           // read enable when fetching code
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    input [7:0] write_enable,                    // write enable for each byte separately when writing code. must be 0x0F or 0xF0 or 0xFF
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    input [`COMMON_ADDR_WIDTH-1:0] write_addr_in,// Address lines when writing to code memory
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    input [63:0] write_data_in,                  // Data lines when writing to code memory
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    input [`CODE_ADDR_WIDTH-2:0] read_addr_in,   // Address for reading from code memory
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    output reg [`CODE_DATA_WIDTH-1:0] data_out,  // Data out
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    // outputs for debugger:
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    output reg [31:0] debug_out           // debug information
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);
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// code ram
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reg [`CODE_DATA_WIDTH-1:0] ram[0:(2**(`CODE_ADDR_WIDTH-1)-1)];
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// (attempt to split this into 32-bit lines failed to implement as ram block)
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logic [`COMMON_ADDR_WIDTH-4:0] write_address_hi;
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//logic [`DATA_ADDR_WIDTH-4:0] write_address_hi;
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//logic [2:0] address_lo; // not used
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logic write_address_valid;
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always_comb begin
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//    write_address_hi = write_addr_in[`COMMON_ADDR_WIDTH-1:3] - {1'b1,`CODE_ADDR_START'b0}; // index to 64-bit lines
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    write_address_hi = write_addr_in[`COMMON_ADDR_WIDTH-1:3] - {1'b1,{(`CODE_ADDR_START-3){1'b0}}}; // index to 64-bit lines
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    write_address_valid = write_addr_in[`COMMON_ADDR_WIDTH-1:`CODE_ADDR_START] != 0;       // code address space
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end
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/*
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Calculation of loader address:
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Code memory starts at address 2**CODE_ADDR_START = 32kB = 0x8000
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Code memory size = 2**(CODE_ADDR_WIDTH+2) = 64kB = 0x10000
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Code memory end = code memory start + code memory size = 0x18000
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Max loader size = 2kB = 0x800 bytes
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Loader start address = code memory end - max loader size
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Each line in code ram is CODE_DATA_WIDTH = 64 bits = 8 bytes
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Loader start line = (code memory size - max loader size) / line size
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*/
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parameter max_loader_size   = `MAX_LOADER_SIZE << 2;   // loader size in bytes
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parameter code_memory_start = 2**`CODE_ADDR_START;
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parameter code_memory_size  = 2**(`CODE_ADDR_WIDTH+2);
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parameter code_memory_end   = code_memory_start + code_memory_size;
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parameter loader_start_address = code_memory_end - max_loader_size;
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parameter loader_start_relative = code_memory_size - max_loader_size;
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parameter loader_start_line = loader_start_relative / (`CODE_DATA_WIDTH >> 3);
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generate if (`LOADER_FILE != "")
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    initial begin
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        // insert loader code
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        $readmemh(`LOADER_FILE, ram, loader_start_line);
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    end
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endgenerate
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// code ram read and write process
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always_ff @(posedge clock) if (clock_enable) begin
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    // Write data to code RAM when loading program code
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    if (write_address_valid) begin  // write address is in code section
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        if (write_enable[0]) begin
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            ram[write_address_hi][31:0] <= write_data_in[31:0];
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        end
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        if (write_enable[4]) begin
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            ram[write_address_hi][63:32] <= write_data_in[63:32];
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        end
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    end
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    // Read from code ram when executing
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    if (read_enable) begin
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        data_out <= ram[read_addr_in];
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    end
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    // Output for debugger
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    debug_out[23:0] <= write_address_hi;
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    debug_out[28] <= write_address_valid;
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end
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endmodule

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