OpenCores
URL https://opencores.org/ocsvn/forwardcom/forwardcom/trunk

Subversion Repositories forwardcom

[/] [forwardcom/] [trunk/] [data_memory.sv] - Blame information for rev 162

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 18 Agner
//////////////////////////////////////////////////////////////////////////////////
2
// Engineer: Agner Fog
3
//
4
// Create Date:    2020-06-03
5
// Last modified:  2021-08-02
6
// Module Name:    data_cache
7
// Project Name:   ForwardCom soft core
8
// Target Devices: Artix 7
9
// Tool Versions:  Vivado v. 2020.1
10
// License:        CERN-OHL-W v. 2 or later
11
// Description:    data memory or data cache for read/write data
12
//
13
//////////////////////////////////////////////////////////////////////////////////
14
`include "defines.vh"
15
 
16
 
17
// read/write data memory or cache, (2**`DATA_ADDR_WIDTH) bytes = 2**16 = 64kB
18
module data_memory (
19
    input clock,                                    // clock
20
    input clock_enable,                             // clock enable. Used when single-stepping
21
    input [`COMMON_ADDR_WIDTH-1:0] read_write_addr, // Address for reading and writing from/to ram
22
                                                    // The lower 3 bits of read_write_addr indicate a byte within an 8 bytes line
23
    input read_enable,                              // read enable
24
    input [1:0] read_data_size,                     // 8, 16, 32, or 64 bits read
25
    input [7:0] write_enable,                       // write enable for each byte separately
26
    input [63:0] write_data_in,                     // Data in. Always 64 bits. Any part of the write bus can be used when the data size is less than 64 bits
27
`ifdef DISTRIBUTED_RAM                              // Distributed RAM takes a lot of FPGA resources
28
    output reg   [`RB1:0] read_data_out             // Data out
29
`else                                               // Block RAM
30
    output logic [`RB1:0] read_data_out             // Data out
31
`endif
32
);
33
 
34
// read/write data ram
35
reg [63:0] dataram [0:(2**(`DATA_ADDR_WIDTH-3))-1]; // 64kB RAM
36
 
37
// split read/write address into double-word index, and byte index
38
logic [`DATA_ADDR_WIDTH-4:0] address_hi;
39
logic [2:0] address_lo;
40
logic address_valid;
41
 
42
always_comb begin
43
    address_hi = read_write_addr[`DATA_ADDR_WIDTH-1:3]; // index to 64-bit lines
44
    address_lo = read_write_addr[2:0];                  // index to byte within line
45
    address_valid = read_write_addr[`COMMON_ADDR_WIDTH-1:`DATA_ADDR_WIDTH] == 0; // exclude code addresses
46
end
47
 
48
 
49
// Data write:
50
always_ff @(posedge clock) if (clock_enable & address_valid) begin
51
    // write data to RAM. Each byte enabled separately
52
    if (write_enable[0]) dataram[address_hi][ 7: 0] <= write_data_in[ 7: 0];
53
    if (write_enable[1]) dataram[address_hi][15: 8] <= write_data_in[15: 8];
54
    if (write_enable[2]) dataram[address_hi][23:16] <= write_data_in[23:16];
55
    if (write_enable[3]) dataram[address_hi][31:24] <= write_data_in[31:24];
56
    if (write_enable[4]) dataram[address_hi][39:32] <= write_data_in[39:32];
57
    if (write_enable[5]) dataram[address_hi][47:40] <= write_data_in[47:40];
58
    if (write_enable[6]) dataram[address_hi][55:48] <= write_data_in[55:48];
59
    if (write_enable[7]) dataram[address_hi][63:56] <= write_data_in[63:56];
60
end
61
 
62
 
63
// data read. Must have natural alignment
64
 
65
`ifdef DISTRIBUTED_RAM
66
// The multiplexer comes before the register. This is only possible with distributed RAM.
67
// Distributed RAM takes a lot of FPGA resources but may allow a slightly higher clock frequency.
68
 
69
always_ff @(posedge clock) if (clock_enable & address_valid & read_enable) begin
70
 
71
    // Each 64-bit RAM line may be divided into
72
    // eight bytes, four 16-bit halfwords, two 32-bit words, or one 64-bit double word:
73
    case (address_lo)
74
    0: read_data_out[7:0] <= dataram[address_hi][ 7: 0];
75
    1: read_data_out[7:0] <= dataram[address_hi][15: 8];
76
    2: read_data_out[7:0] <= dataram[address_hi][23:16];
77
    3: read_data_out[7:0] <= dataram[address_hi][31:24];
78
    4: read_data_out[7:0] <= dataram[address_hi][39:32];
79
    5: read_data_out[7:0] <= dataram[address_hi][47:40];
80
    6: read_data_out[7:0] <= dataram[address_hi][55:48];
81
    7: read_data_out[7:0] <= dataram[address_hi][63:56];
82
    endcase
83
 
84
    case (address_lo[2:1])
85
    0: read_data_out[15:8] <= dataram[address_hi][15: 8];
86
    1: read_data_out[15:8] <= dataram[address_hi][31:24];
87
    2: read_data_out[15:8] <= dataram[address_hi][47:40];
88
    3: read_data_out[15:8] <= dataram[address_hi][63:56];
89
    endcase
90
 
91
    case (address_lo[2])
92
    0: read_data_out[31:16] <= dataram[address_hi][31:16];
93
    1: read_data_out[31:16] <= dataram[address_hi][63:48];
94
    endcase
95
 
96
    `ifdef SUPPORT_64BIT
97
        read_data_out[63:32] <= dataram[address_hi][63:32];
98
    `endif
99
end
100
 
101
`else
102
// block RAM. The multiplexer must come after the register
103
 
104
reg [63:0] read_data;                    // a whole line read from the RAM
105
reg [2:0]  address_lo2;                  // address_lo saved
106
 
107
 
108
always_ff @(posedge clock) if (clock_enable & address_valid & read_enable) begin
109
    read_data   <= dataram[address_hi];  // read a 64 bits line from ram
110
    address_lo2 <= address_lo;           // save low part of address
111
end
112
 
113
always_comb begin
114
    // Each 64-bit RAM line may be divided into eight bytes, four 16-bit halfwords,
115
    // two 32-bit words, or one 64-bit double word.
116
    // The speed of this multiplexer is very critical because it adds to the delay
117
    // in the execution unit. We are saving time by not setting unused parts of
118
    // read_data_out to zero.
119
    case (address_lo2)
120
    0: read_data_out[7:0] = read_data[ 7: 0];
121
    1: read_data_out[7:0] = read_data[15: 8];
122
    2: read_data_out[7:0] = read_data[23:16];
123
    3: read_data_out[7:0] = read_data[31:24];
124
    4: read_data_out[7:0] = read_data[39:32];
125
    5: read_data_out[7:0] = read_data[47:40];
126
    6: read_data_out[7:0] = read_data[55:48];
127
    7: read_data_out[7:0] = read_data[63:56];
128
    endcase
129
 
130
    case (address_lo2[2:1])
131
    0: read_data_out[15:8] = read_data[15: 8];
132
    1: read_data_out[15:8] = read_data[31:24];
133
    2: read_data_out[15:8] = read_data[47:40];
134
    3: read_data_out[15:8] = read_data[63:56];
135
    endcase
136
 
137
    case (address_lo2[2])
138
    0: read_data_out[31:16] = read_data[31:16];
139
    1: read_data_out[31:16] = read_data[63:48];
140
    endcase
141
 
142
    `ifdef SUPPORT_64BIT
143
        read_data_out[63:32] = read_data[63:32];
144
    `endif
145
end
146
 
147
`endif
148
 
149
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.