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1 21 Agner
//////////////////////////////////////////////////////////////////////////////////
2
// Engineer: Agner Fog
3
//
4
// Create date:    2020-06-29
5
// Last modified:  2021-07-01
6
// Module name:    debug_display
7
// Project name:   ForwardCom soft core
8
// Target device:  Artix 7 - Nexys A7-100T
9
// Tool versions:  Vivado 2020.1
10
// License:        CERN-OHL-W v. 2 or later
11
// Description:    showing each stage of the pipeline on LCD displays during debugging
12
//
13
//////////////////////////////////////////////////////////////////////////////////
14
`include "defines.vh"
15
 
16
module debug_display (
17
    input clock,  // system clock (100 MHz)
18
    input clock_enable, // clock enable. Used when single-stepping
19
    input reset_button_debounced,           // reset button
20
    // from fetch stage
21
    input [63:0] fetch_instruction,         // first words of instruction
22
    input [15:0] fetch_instruction_pointer, // point to current instruction
23
    input        fetch_valid,               // output from fetch is ready
24
    input        fetch_jump,                // jump instruction bypassing pipeline
25
    input        fetch_call_e,              // executing call instruction
26
    input        fetch_return_e,            // executing return instruction
27
    input        registerread_stall_predict,// address generation stalled next
28
    input        addrgen_stall_next,        // address generation stalled next
29
    input        dataread_stall_predict,    // alu stalled next
30
    input        alu_stall_next,            // alu stalled next
31
    input        muldiv_stall_next,         // muldiv stalled next
32
    input        inout_stall_next,          // in_out_ports stalled next
33
 
34
    // from decoder
35
    input [63:0] decoder_instruction,       // first words of instruction
36
    input [15:0] decoder_instruction_pointer,// address of current instruction
37
    input        decoder_valid,             // output from decoder is ready
38
 
39
    // from register_read
40
    input [63:0] registerread_instruction,  // first words of instruction
41
    input [15:0] registerread_instruction_pointer, // address of current instruction
42
    input        registerread_valid,        // output from decode_wait is ready
43
 
44
    // from address generator
45
    input [63:0] addrgen_instruction,       // first words of instruction
46
    input [15:0] addrgen_instruction_pointer,// address of current instruction
47
    input        addrgen_valid,             // output from addrgen is ready
48
 
49
    // from data read
50
    input [63:0]  dataread_instruction,     // first words of instruction
51
    input [15:0]  dataread_instruction_pointer, // address of current instruction
52
    input [6:0]   dataread_opx,             // operation ID in execution unit. This is mostly equal to op1 for multiformat instructions
53
    input         dataread_valid,           // output from addrwait is ready
54
    input [`RB:0] dataread_operand1,        // first register operand RD or RU
55
    input [`RB:0] dataread_operand2,        // second register operand RS
56
    input [`RB:0] dataread_operand3,        // last register operand RT
57
    input [`MASKSZ:0] dataread_mask_val,    // mask value
58
    input [15:0]  ram_data_in,             // memory operand from data ram
59
    input         dataread_opr2_from_ram,   // value of operand 2 comes from data ram
60
    input         dataread_opr3_from_ram,   // value of last operand comes from data ram
61
 
62
    // from ALU
63
    //input [6:0]  writea1,                 // register to write
64
    input [31:0] alu_result,                // result from ALU
65
    input [`TAG_WIDTH-1:0] write_tag1,      // instruction tag on result bus
66
    input        alu_valid,                 // output from alu is ready
67
    input        alu_jump,                  // jump instruction: jump taken
68
    //input        alu_nojump,              // jump instruction: jump not taken
69
    input [15:0] alu_jump_pointer,          // jump target address
70
 
71
    // from muldiv result buses
72
    input [31:0] writeport2,                // result bus 2 from muldiv etc.
73
    input        write_en2,
74
    input [`TAG_WIDTH-1:0] write_tag2,
75
 
76
    // output to LCD display driver
77
    output reg lcd_rs,                      // LCD RS pin
78
    output reg [1:0] lcd_e,                 // enable pins for two LCD displays
79
    output reg [3:0] lcd_data               // LCD data, 4 bit bus
80
);
81
 
82
// LCD display data
83
reg [3:0] row;                              // row number (0 = top, 7 = bottom, 8 = finished)
84
reg [4:0] column;                           // column number (0 = left)
85
reg [7:0] display_text[0:19];               // text for one line
86
reg [4:0] text_length;                      // length of text
87
reg       display_write;                    // write command for display
88
reg       eol;                              // pad with spaces until end of line
89
reg       display_ready;                    // display ready for next line
90
reg [1:0] state;        // 0: idle
91
                        // 1: set text. send display_write signal to LCD driver
92
                        // 2: wait for display ready
93
                        // 3: row++
94
reg [2:0]  delay;                           // delay for display_write signal
95
 
96
reg [63:0] alu_instruction;                 // first word of instruction currently in ALU
97
reg [15:0] alu_instruction_pointer;         // address of instruction currently in ALU
98
reg [6:0]  alu_opx;                         // operation ID in alu
99
reg [7:0]  instruction_name[0:5];           // name of instruction
100
reg [15:0] opr1_val;                        // first operand RD or RU
101
reg [15:0] opr2_val;                        // second operand RS
102
reg [15:0] opr3_val;                        // third operand RT, immediate, or memory
103
reg        mask_val;                        // mask register value, bit 0
104
 
105
 
106
// LCD display driver
107
lcd lcd_inst (
108
    .clock(clock),                          // system clock 100 MHz
109
    .reset(reset_button_debounced),         // reset and clear
110
    .x(column),                             // column number (0 = left)
111
    .y(row[2:0]),                           // row number (0 = top)
112
    .text(display_text),                    // text for one line
113
    .text_length(text_length),              // length of text
114
    .start(display_write),                  // start writing
115
    .eol(eol),                              // pad with spaces until end of line
116
    .lcd_rs(lcd_rs),                        // LCD RS pin
117
        .lcd_e(lcd_e),                            // enable pins for two LCD displays
118
        .lcd_data(lcd_data),                      // LCD data, 4 bit bus
119
        .ready(display_ready)                     // finished writing line on display. ready for next line
120
);
121
 
122
logic [63:0] instruction;                   // first word of instruction for selected pipeline stage
123
logic [15:0] instruction_pointer;           // address of instruction for selected pipeline stage
124
logic       valid;                          // valid output from current stage is ready
125
logic       stalled;                        // current stage is stalled
126
logic [1:0] il;                             // instruction length
127
logic [2:0] mode;                           // format mode
128
logic [5:0] op1;                            // instruction op1 code
129
logic [1:0] op2;                            // instruction op2 code
130
logic       M;                              // format M bit
131
logic [2:0] mode2;                          // format mode2
132
logic [2:0] mask;                           // mask register
133
logic [5:0] opj;                            // jump condition id
134
logic [6:0] opx;                            // instruction id
135
reg   [1:0] category;                       // 00: multiformat, 01: single format, 10: jump
136
reg   [6:0] opx2;                           // instruction id, calculated here
137
reg   [2:0] format;                         // 1 - 5 means A - E
138
reg         is_vector;                      // vector instruction
139
 
140
 
141
// convert 4-bit binary number to hexadecimal ascii code
142
function [7:0] nibble2ascii;
143
    input [3:0] inp;
144
    logic [7:0] a;
145
    if (inp < 10) a = inp + 8'H30;
146
    else a = inp + 8'H37;
147
    return a;
148
endfunction
149
 
150
 
151
// multiplexer to select data from one pipeline stage
152
always_comb begin
153
    case (row)
154
    0: begin  // fetch
155
        instruction = fetch_instruction;
156
        instruction_pointer = fetch_instruction_pointer;
157
        opx = opx2;
158
        valid = fetch_valid;
159
        stalled = registerread_stall_predict | addrgen_stall_next | dataread_stall_predict;
160
    end
161
    1: begin  // decoder
162
        instruction = decoder_instruction;
163
        instruction_pointer = decoder_instruction_pointer;
164
        opx = opx2;
165
        valid = decoder_valid;
166
        stalled = registerread_stall_predict | addrgen_stall_next | dataread_stall_predict;
167
    end
168
    2: begin  // register_read
169
        instruction = registerread_instruction;
170
        instruction_pointer = registerread_instruction_pointer;
171
        opx = opx2;
172
        valid = registerread_valid;
173
        stalled = registerread_stall_predict | addrgen_stall_next | dataread_stall_predict | alu_stall_next | inout_stall_next | muldiv_stall_next;
174
    end
175
    3: begin  // address generator
176
        instruction = addrgen_instruction;
177
        instruction_pointer = addrgen_instruction_pointer;
178
        opx = opx2;
179
        valid = addrgen_valid;
180
        stalled = dataread_stall_predict | alu_stall_next | muldiv_stall_next | inout_stall_next;
181
    end
182
    4: begin  // data read
183
        instruction = dataread_instruction;
184
        instruction_pointer = dataread_instruction_pointer;
185
        opx = dataread_opx;
186
        valid = dataread_valid;
187
        stalled = dataread_stall_predict | alu_stall_next | muldiv_stall_next | inout_stall_next;
188
    end
189
    default: begin // alu
190
        instruction = alu_instruction;
191
        instruction_pointer = alu_instruction_pointer;
192
        opx = alu_opx;
193
        valid = alu_valid;
194
        stalled = dataread_stall_predict;
195
    end
196
    endcase
197
 
198
    il = instruction[`IL];        // instruction length
199
    mode = instruction[`MODE];    // format mode
200
    mode2 = instruction[`MODE2];  // format mode2
201
    op1 = instruction[`OP1];      // instruction OP1
202
    op2 = instruction[`OP2];      // instruction OP2
203
    M   = instruction[`M];        // format M bit
204
    mask = instruction[`MASK];    // mask field
205
 
206
    // get opj. This code is copied from dataread.sv
207
    opj = 0;
208
    if (il == 1) begin
209
        opj = op1;
210
    end else if (op1 == 0) begin  // format 2.5.0A, 3.1.0A
211
        opj = instruction[61:56]; // opj in byte 7
212
    end else if (il == 2 && op1 == 7) begin // system call
213
        opj = `IJ_SYSCALL;
214
    end else if (op1 < 8) begin
215
        opj = instruction[5:0];
216
    end else begin
217
        opj = 56;                 // unknown
218
    end
219
 
220
end
221
 
222
// state machine for writing one line for each pipeline stage on LCD display
223
always_ff @(posedge clock) begin
224
    // state control
225
    if (state == 0) begin
226
        // state 0: idle
227
        display_write <= 0;
228
        row <= 0;
229
        if (clock_enable) begin
230
            delay <= 3;
231
            state <= 1;
232
        end
233
 
234
    end else if (state == 1) begin
235
        // state 1: set text. send display_write pulse
236
        if (delay < 2) display_write <= 1;
237
        else display_write <= 0;
238
        if (delay > 0) begin
239
            delay <= delay - 1;
240
        end else begin
241
            state <= 2;
242
            delay <= 3;
243
        end
244
 
245
    end else if (state == 2) begin
246
        // state 2: wait for display_ready
247
        if (delay > 0) begin
248
            delay <= delay - 1;
249
        end else begin
250
            if (display_ready) state <= 3;
251
        end
252
 
253
    end else begin
254
        // state 3: row++
255
        if (row < 7) begin
256
            row <= row + 1;
257
            state <= 1;
258
            delay <= 3;
259
        end else begin
260
            row <= 0;
261
            state <= 0;
262
        end
263
    end
264
 
265
    // compose text for current row
266
    if (state == 1 || state == 2) begin
267
 
268
        if (row < 6) begin
269
            // First 6 rows: fetch, decode, decodewait, addrgen, addrwait, alu
270
            case (row)  // Indicate pipeline stage
271
            0: display_text[0] <= "F";  // fetch
272
            1: display_text[0] <= "D";  // decode
273
            2: display_text[0] <= "R";  // register read
274
            3: display_text[0] <= "A";  // address
275
            4: display_text[0] <= "d";  // data read
276
            5: display_text[0] <= "X";  // alu (Execute)
277
            endcase
278
            display_text[1] <= " ";
279
            //if (1/*valid*/) begin
280
 
281
            // write lower 4 digits of instruction_pointer
282
            display_text[2] <= nibble2ascii(instruction_pointer[15:12]);
283
            display_text[3] <= nibble2ascii(instruction_pointer[11:8]);
284
            display_text[4] <= nibble2ascii(instruction_pointer[7:4]);
285
            display_text[5] <= nibble2ascii(instruction_pointer[3:0]);
286
            display_text[6] <= stalled ? "#" : " ";
287
 
288
            if (!valid) begin
289
                display_text[7] <= "-";
290
                text_length <= 8;
291
            end else begin
292
 
293
                // write il.mode.op1, Format, Operand type, instruction name
294
                display_text[7] <= nibble2ascii(il);
295
                display_text[8] <= ".";
296
                if (mode < 2 && M && (!il[0] || !mode[0])) begin
297
                    // format 0.8, 0.9, 1.8, 2.8, 2.9, 3.8 ½
298
                    display_text[9] <= nibble2ascii(mode | 4'b1000);
299
                end else begin
300
                    display_text[9] <= nibble2ascii(mode);
301
                end
302
                // write format letter
303
                display_text[10] <= {5'b01000,format}; // format letter A - E
304
                display_text[11] <= " ";
305
                // write oprand type: bhwdqFDQ
306
                if (opx == `II_NOP) begin
307
                    display_text[12] <= " ";
308
                end else if (is_vector) begin
309
                    case (instruction[`OT])
310
                    0: display_text[12] <= "b"; // byte (8 bit)
311
                    1: display_text[12] <= "h"; // half word (16 bit)
312
                    2: display_text[12] <= "w"; // word (32 bit)
313
                    3: display_text[12] <= "d"; // double word (64 bit)
314
                    4: display_text[12] <= "q"; // quad word (128 bit)
315
                    5: display_text[12] <= "F"; // float single precision (32 bit)
316
                    6: display_text[12] <= "D"; // double precision (64 bit)
317
                    7: display_text[12] <= "Q"; // quadruple precision (128 bit)
318
                    endcase
319
                end else begin
320
                    case (instruction[14:13])   // two bit operand type for non-vector instructions
321
                    0: display_text[12] <= "b"; // byte (8 bit)
322
                    1: display_text[12] <= "h"; // half word (16 bit)
323
                    2: display_text[12] <= "w"; // word (32 bit)
324
                    3: display_text[12] <= "d"; // double word (64 bit)
325
                    endcase
326
                end
327
                display_text[13] <= " ";
328
 
329
                // write name of instruction
330
                for (int i = 0; i < 6; i++) begin
331
                    display_text[i+14] <= instruction_name[i];
332
                end
333
                text_length <= 20;
334
            end
335
 
336
            if (row == 0 && fetch_jump) begin
337
                // jump, call or return bypassign pipeline
338
                if (fetch_call_e) begin
339
                    display_text[0] <= "C";
340
                    display_text[1] <= "a";
341
                    display_text[2] <= "l";
342
                    display_text[3] <= "l";
343
                    text_length <= 4;
344
                end else if (fetch_return_e) begin
345
                    display_text[0] <= "R";
346
                    display_text[1] <= "e";
347
                    display_text[2] <= "t";
348
                    display_text[3] <= "u";
349
                    display_text[4] <= "r";
350
                    display_text[5] <= "n";
351
                    text_length <= 6;
352
            end else begin
353
                    display_text[0] <= "J";
354
                    display_text[1] <= "u";
355
                    display_text[2] <= "m";
356
                    display_text[3] <= "p";
357
                    text_length <= 4;
358
                end
359
            end
360
 
361
            column <= 0;
362
            eol <= 1;
363
 
364
        end else if (row == 6) begin
365
            // row 6: operands
366
            display_text[0] <= ":";  // operands
367
            display_text[1] <= " ";
368
            display_text[2] <= nibble2ascii(opr1_val[15:12]);
369
            display_text[3] <= nibble2ascii(opr1_val[11:8]);
370
            display_text[4] <= nibble2ascii(opr1_val[7:4]);
371
            display_text[5] <= nibble2ascii(opr1_val[3:0]);
372
            display_text[6] <= " ";
373
            display_text[7] <= nibble2ascii(opr2_val[15:12]);
374
            display_text[8] <= nibble2ascii(opr2_val[11:8]);
375
            display_text[9] <= nibble2ascii(opr2_val[7:4]);
376
            display_text[10] <= nibble2ascii(opr2_val[3:0]);
377
            display_text[11] <= " ";
378
            display_text[12] <= nibble2ascii(opr3_val[15:12]);
379
            display_text[13] <= nibble2ascii(opr3_val[11:8]);
380
            display_text[14] <= nibble2ascii(opr3_val[7:4]);
381
            display_text[15] <= nibble2ascii(opr3_val[3:0]);
382
            display_text[16] <= " ";
383
            text_length <= 17;
384
            column <= 0;
385
            eol <= 1;
386
 
387
        end else if (row == 7 & valid) begin
388
            // row 7: result
389
            column <= 0;
390
            eol <= 1;
391
            display_text[0] <= "=";  // result
392
            display_text[1] <= " ";
393
 
394
            if (category == `CAT_JUMP) begin  // result of jump instruction
395
                display_text[2] <= nibble2ascii(alu_result[15:12]);
396
                display_text[3] <= nibble2ascii(alu_result[11:8]);
397
                display_text[4] <= nibble2ascii(alu_result[7:4]);
398
                display_text[5] <= nibble2ascii(alu_result[3:0]);
399
                display_text[6] <= " ";
400
                if (alu_jump) begin // jump taken
401
                    display_text[7]  <= "j";
402
                    display_text[8]  <= "u";
403
                    display_text[9]  <= "m";
404
                    display_text[10] <= "p";
405
                    display_text[11] <= " "; // write target address:
406
                    display_text[12] <= nibble2ascii(alu_jump_pointer[15:12]);
407
                    display_text[13] <= nibble2ascii(alu_jump_pointer[11:8]);
408
                    display_text[14] <= nibble2ascii(alu_jump_pointer[7:4]);
409
                    display_text[15] <= nibble2ascii(alu_jump_pointer[3:0]);
410
                    text_length <= 16;
411
                end else begin // jump not taken
412
                    display_text[7]  <= "n";
413
                    display_text[8]  <= "o";
414
                    display_text[9]  <= " ";
415
                    display_text[10] <= "j";
416
                    display_text[11] <= "u";
417
                    display_text[12] <= "m";
418
                    display_text[13] <= "p";
419
                    text_length <= 14;
420
                end
421
 
422
            end else if (write_en2) begin  // result from muldiv or other unit
423
                // to do: what to do if there are results from alu and muldiv simultaneously?
424
                display_text[0] <= "m";
425
                display_text[1] <= "u";
426
                display_text[2] <= "l";
427
                display_text[3] <= "d";
428
                display_text[4] <= "i";
429
                display_text[5] <= "v";
430
                display_text[6] <= "=";
431
                display_text[7]  <= nibble2ascii(writeport2[31:28]);
432
                display_text[8]  <= nibble2ascii(writeport2[27:24]);
433
                display_text[9]  <= nibble2ascii(writeport2[23:20]);
434
                display_text[10] <= nibble2ascii(writeport2[19:16]);
435
                display_text[11] <= nibble2ascii(writeport2[15:12]);
436
                display_text[12] <= nibble2ascii(writeport2[11:8]);
437
                display_text[13] <= nibble2ascii(writeport2[7:4]);
438
                display_text[14] <= nibble2ascii(writeport2[3:0]);
439
 
440
            end else begin  // 32 bit result of alu non-jump instruction
441
                display_text[2] <= nibble2ascii(alu_result[31:28]);
442
                display_text[3] <= nibble2ascii(alu_result[27:24]);
443
                display_text[4] <= nibble2ascii(alu_result[23:20]);
444
                display_text[5] <= nibble2ascii(alu_result[19:16]);
445
                display_text[6] <= nibble2ascii(alu_result[15:12]);
446
                display_text[7] <= nibble2ascii(alu_result[11:8]);
447
                display_text[8] <= nibble2ascii(alu_result[7:4]);
448
                display_text[9] <= nibble2ascii(alu_result[3:0]);
449
                if (instruction[`MASK] < 7) begin
450
                    // write bit 0 of mask
451
                    display_text[10]  <= " ";
452
                    display_text[11]  <= "m";
453
                    display_text[12]  <= "0" | mask_val;
454
                    text_length <= 13;
455
                end else begin // no mask
456
                    text_length <= 10;
457
                end
458
            end
459
        end else begin
460
            // row 7, not valid
461
            display_text[0]  <= "-";
462
            text_length <= 1;
463
            column <= 0;
464
            eol <= 1;
465
        end
466
    end
467
end
468
 
469
 
470
// parallel decoding if instruction is not completely decoded yet
471
// calculate opx if not available
472
always_ff @(posedge clock) begin
473
 
474
    // save inputs to alu stage for next clock cycle because they are not output from alu
475
    if (clock_enable) begin
476
        alu_instruction <= dataread_instruction;                // first word of instruction currently in ALU
477
        alu_instruction_pointer <= dataread_instruction_pointer;// address of instruction currently in ALU
478
        alu_opx  <= dataread_opx;                               // operation ID in alu
479
 
480
        // mirror operand catching in ALU stage
481
        if (dataread_operand1[`RB]) begin                       // value missing
482
            if (dataread_operand1[`TAG_WIDTH-1:0] == write_tag1) begin
483
                opr1_val <= alu_result;                         // got value from result bus 1
484
            end else if (write_en2 && dataread_operand1[`TAG_WIDTH-1:0] == write_tag2) begin
485
                opr1_val <= writeport2;                         // obtained from result bus 2
486
            end else begin
487
                opr1_val <= 0;
488
            end
489
        end else begin
490
            opr1_val <= dataread_operand1;
491
        end
492
 
493
        if (dataread_opr2_from_ram) begin
494
            opr2_val <= ram_data_in;
495
        end else if (dataread_operand2[`RB]) begin              // value missing
496
            if (dataread_operand2[`TAG_WIDTH-1:0] == write_tag1) begin
497
                opr2_val <= alu_result;                         // got value from result bus 1
498
            end else if (write_en2 && dataread_operand2[`TAG_WIDTH-1:0] == write_tag2) begin
499
                opr2_val <= writeport2;                         // obtained from result bus 2
500
            end else begin
501
                opr2_val <= 0;
502
            end
503
        end else begin
504
            opr2_val <= dataread_operand2;
505
        end
506
 
507
        if (dataread_opr3_from_ram) begin
508
            opr3_val <= ram_data_in;
509
        end else if (dataread_operand3[`RB]) begin              // value missing
510
            if (dataread_operand3[`TAG_WIDTH-1:0] == write_tag1) begin
511
                opr3_val <= alu_result;                         // got value from result bus 1
512
            end else if (write_en2 && dataread_operand3[`TAG_WIDTH-1:0] == write_tag2) begin
513
                opr3_val <= writeport2;                         // obtained from result bus 2
514
            end else begin
515
                opr3_val <= 0;
516
            end
517
        end else begin
518
            opr3_val <= dataread_operand3;
519
        end
520
 
521
        if (dataread_mask_val[`MASKSZ]) begin                   // value missing
522
            if (dataread_mask_val[`TAG_WIDTH-1:0] == write_tag1) begin
523
                mask_val <= alu_result;                         // got value from result bus 1
524
            end else if (write_en2 && dataread_mask_val[`TAG_WIDTH-1:0] == write_tag2) begin
525
                mask_val <= writeport2[31:0];                   // obtained from result bus 2
526
            end else begin
527
                mask_val <= 0;
528
            end
529
        end else begin // value available
530
            mask_val <= dataread_mask_val[`TAG_WIDTH-1:0];
531
        end
532
    end
533
 
534
    if (state == 1 || state == 2) begin
535
        // detect category, 00: multiformat, 01: single format, 10: jump
536
        // this code is copied from decoder.sv
537
        if (il == 0) begin // format 0.x
538
            category <= `CAT_MULTI;
539
 
540
        end else if (il == 1) begin                   // format 1.x
541
            if (mode == 6 || mode == 7) begin         // format 1.6 and 1.7
542
                category <= `CAT_JUMP;
543
            end else begin
544
                category <= `CAT_SINGLE;
545
            end
546
 
547
        end else if (il >= 2 && ((mode == 0 && !M) || mode == 2) && op2 != 0 && (mode2 != 5 || il == 3)) begin // format 2.0.x, 2.2.x, 3.0.x, 3.2.x, op2 > 0
548
            category <= `CAT_SINGLE;
549
 
550
        end else if (il == 2) begin                   // format 2.x
551
            if (mode == 1 && M) begin                 // format 2.9
552
                category <= `CAT_SINGLE;
553
            end else if (mode == 6 || mode == 7) begin// format 2.6 - 2.7
554
                category <= `CAT_SINGLE;
555
            end else if (mode == 5) begin             // format 2.5
556
                if (op1 < 8) begin
557
                    category <= `CAT_JUMP;
558
                end else begin
559
                    category <= `CAT_SINGLE;
560
                end
561
            end else begin
562
                category <= `CAT_MULTI;
563
            end
564
        end else begin                                // format 3.x
565
            if (mode == 1) begin                      // format 3.1
566
                if (op1 < 8) begin
567
                    category <= `CAT_JUMP;
568
                end else begin
569
                    category <= `CAT_SINGLE;
570
                end
571
            end else begin
572
                category <= `CAT_MULTI;
573
            end
574
        end
575
 
576
        // detect instruction format: A, B, C, D, or E indicated as 1 - 5
577
        if (il == 0) begin                            // format 0.x
578
            if (mode == 1 || mode == 3 || mode == 7) begin
579
                format <= 2;                          // B: 0.1, 0.3, 0.7, 0.9
580
            end else begin
581
                format <= 1;                          // A: 0.0, 0.2, 0.4, 0.5, 0.6, 0.8
582
            end
583
        end else if (il == 1) begin                   // format 1.x
584
            if (mode == 3 || (mode == 0 && M)) begin
585
                format <= 2;                          // B: 1.3, 1.8
586
            end else if (mode == 6) begin             // 1.6 jump instructions
587
                if (op1 == `II_RETURN) format = 3;    // C: return
588
                else if (op1 >= `II_JUMP_RELATIVE) begin
589
                    format <= 1;                      // A: relative jump, sys_call
590
                end else format <= 2;                 // B
591
            end else if (mode == 7) begin             // 1.7 jump instructions
592
                if (op1 < 16) format <= 4;            // 24-bit jump/call, format D
593
                else format <= 3;                     // other jumps, format C
594
            end else if (mode == 1 || mode == 4) begin
595
                format <= 3;                          // C: 1.1, 1.4, 1.7
596
            end else begin
597
                format <= 1;                          // A: 1.0, 1.2
598
            end
599
        end else if (il == 2) begin                   // format 2.x
600
            if ((mode == 0 && M == 0) || mode == 2) begin
601
                format <= 5;                          // E: 2.0.x, 2.2.x
602
            end else if (mode == 5) begin             // format 2.5 mixed
603
                if (op1 == 0) begin
604
                    format <= `FORMAT_A;
605
                end else if (op1 >= 4 && op1 <= 8) begin
606
                    format <= `FORMAT_C;              // 2.5 2-4 jump uses format C
607
                end else if (op1 >= `II_25_VECT) begin
608
                    format <= 1;                      // A: 2.5 32-63 vector instructions
609
                end else begin
610
                    format <= 2;                      // B: other jump and miscellaneous instructions
611
                end
612
            end else begin
613
                format <= 1;                          // A: other jump and miscellaneous instructions
614
            end
615
        end else begin                                // format 3.x
616
            if ((mode == 0 && M == 0) || mode == 2) begin
617
                format <= 5;                          // E: 3.0.x, 3.2.x
618
            end else if (mode == 1) begin             // 3.1 mixed
619
                if (op1 < 8) begin                    // jump instructions
620
                    format <= 2;                      // B
621
                end else begin
622
                    format <= 1;                      // A
623
                end
624
            end else begin
625
                format <= 1;                          // A
626
            end
627
        end
628
    end
629
 
630
    // is this a vector instruction?
631
    if (il == 2 && mode == 5) begin                   // 2.5 mixed
632
        is_vector <= op1 >= `II_25_VECT;
633
    end else if (il == 3 && mode == 1) begin          // 3.1 mixed
634
        is_vector <= op1 >= `II_31_VECT;
635
    end else if (category == `CAT_JUMP) begin
636
        if (il == 1 && mode == 7) is_vector <= 0;     // jump instructions format 1.7C
637
        is_vector <= M;                               // all other jump instructions
638
    end else if (mode < 2) begin
639
        is_vector <= 0;
640
    end else begin
641
        is_vector <= 1;
642
    end
643
 
644
    // calculate opx.
645
    // This code is copied from addresswait.sv
646
    if (state == 1 || state == 2) begin
647
        // convert op1 to opx: operation id in execution unit
648
        opx2 = `IX_UNDEF;                             // default is undefined
649
        if (category == `CAT_MULTI) begin
650
            opx2 = op1;                               // mostly same id for multiformat instructions
651
            if (op1 == `II_SUB_REV) opx2 = `II_SUB;   // operands have been swapped
652
            if (op1 == `II_DIV_REV) opx2 = `II_DIV;   // operands have been swapped
653
        end else if (il == 1 && mode == 1) begin
654
            // format 1.1 C. single format with 16 bit constant
655
            case (op1[5:1])
656
            `II_ADD11 >> 1:         opx2 = `II_ADD;
657
            `II_MUL11 >> 1:         opx2 = `II_MUL;
658
            `II_ADDSHIFT16_11 >> 1: opx2 = `II_ADD;
659
            `II_SHIFT_MOVE_11 >> 1: opx2 = `II_MOVE;
660
            `II_SHIFT_ADD_11 >> 1:  opx2 = `II_ADD;
661
            `II_SHIFT_AND_11 >> 1:  opx2 = `II_AND;
662
            `II_SHIFT_OR_11 >> 1:   opx2 = `II_OR;
663
            `II_SHIFT_XOR_11 >> 1:  opx2 = `II_XOR;
664
            default: opx2 = `IX_UNDEF;
665
            endcase
666
            if (op1 <= `II_MOVE11_LAST) opx2 = `II_MOVE; // five different move instructions
667
 
668
        end else if (il == 1 && mode == 0 && M) begin
669
            // format 1.8 B. single format with 8 bit constant
670
            case (op1)
671
            `II_SHIFT_ABS18:  opx2 = `IX_ABS;
672
            `II_BITSCAN_18:   opx2 = `IX_BIT_SCAN;
673
            `II_ROUNDP2_18:   opx2 = `IX_ROUNDP2;
674
            `II_POPCOUNT_18:  opx2 = `IX_POPCOUNT;
675
            `II_READ_SPEC18:  opx2 = `IX_READ_SPEC;
676
            `II_WRITE_SPEC18: opx2 = `IX_WRITE_SPEC;
677
            `II_READ_CAP18:   opx2 = `IX_READ_CAPABILITIES;
678
            `II_WRITE_CAP18:  opx2 = `IX_WRITE_CAPABILITIES;
679
            `II_READ_PERF18:  opx2 = `IX_READ_PERF;
680
            `II_READ_PERFS18: opx2 = `IX_READ_PERF;
681
            `II_READ_SYS18:   opx2 = `IX_READ_SYS;
682
            `II_WRITE_SYS18:  opx2 = `IX_WRITE_SYS;
683
            `II_INPUT_18:     opx2 = `IX_INPUT;
684
            `II_OUTPUT_18:    opx2 = `IX_OUTPUT;
685
            endcase
686
 
687
        end else if (il == 2 && (mode == 0 && !M || mode == 2) && mode2 == 6) begin
688
            // format 2.0.6 and 2.2.6
689
            if (op1 == `II_TRUTH_TAB3 && op2 == `II2_TRUTH_TAB3) opx2 = `IX_TRUTH_TAB3;
690
 
691
        end else if (il == 2 && mode == 0 && !M && mode2 == 7) begin
692
            // format 2.0.7E. single format
693
            if (op1 == `II_MOVE_BITS && op2 == `II2_MOVE_BITS) opx2 = `IX_MOVE_BITS1;
694
        end else if (il == 2 && mode == 1 && M) begin
695
            // format 2.9A. single format with 32 bit constant
696
            case (op1)
697
            `II_MOVE_HI_29: opx2 = `II_MOVE;  // shifted left by 32 here. just store result
698
            `II_INSERT_HI_29: opx2 = `IX_INSERT_HI;
699
            `II_ADDU_29: opx2 = `II_ADD;
700
            `II_SUBU_29: opx2 = `II_SUB;
701
            `II_ADD_HI_29: opx2 = `II_ADD;
702
            `II_AND_HI_29: opx2 = `II_SUB;
703
            `II_OR_HI_29: opx2 = `II_OR;
704
            `II_XOR_HI_29: opx2 = `II_XOR;
705
            `II_ADDRESS_29: opx2 = `IX_ADDRESS; // address instruction. resolved in this state. just store result
706
            endcase
707
        end
708
    end
709
 
710
    // get name of instruction
711
    if (state == 1 || state == 2) begin
712
        // default characters are space if not specified below
713
        instruction_name[0] <= " ";
714
        instruction_name[1] <= " ";
715
        instruction_name[2] <= " ";
716
        instruction_name[3] <= " ";
717
        instruction_name[4] <= " ";
718
        instruction_name[5] <= " ";
719
 
720
        if (format == 4) begin // format D. 24-bit jump or call
721
            if (op1 < 8) begin
722
                instruction_name[0] <= "J";
723
                instruction_name[1] <= "U";
724
                instruction_name[2] <= "M";
725
                instruction_name[3] <= "P";
726
            end else begin
727
                instruction_name[0] <= "C";
728
                instruction_name[1] <= "A";
729
                instruction_name[2] <= "L";
730
                instruction_name[3] <= "L";
731
            end
732
 
733
        end else if (category == `CAT_JUMP) begin
734
            case (opj)
735
            `IJ_SUB_JZ: begin
736
                instruction_name[0] <= "-";
737
                instruction_name[1] <= "J";
738
                instruction_name[2] <= "Z";
739
                end
740
            `IJ_SUB_JZ+1: begin
741
                instruction_name[0] <= "-";
742
                instruction_name[1] <= "J";
743
                instruction_name[2] <= "N";
744
                instruction_name[3] <= "Z";
745
                end
746
            `IJ_SUB_JNEG: begin
747
                instruction_name[0] <= "-";
748
                instruction_name[1] <= "J";
749
                instruction_name[2] <= "N";
750
                end
751
            `IJ_SUB_JNEG+1: begin
752
                instruction_name[0] <= "-";
753
                instruction_name[1] <= "J";
754
                instruction_name[2] <= "N";
755
                instruction_name[3] <= "N";
756
                end
757
            `IJ_SUB_JPOS: begin
758
                instruction_name[0] <= "-";
759
                instruction_name[1] <= "J";
760
                instruction_name[2] <= "P";
761
                end
762
            `IJ_SUB_JPOS+1: begin
763
                instruction_name[0] <= "-";
764
                instruction_name[1] <= "J";
765
                instruction_name[2] <= "N";
766
                instruction_name[3] <= "P";
767
                end
768
            `IJ_SUB_JOVFLW: begin
769
                instruction_name[0] <= "-";
770
                instruction_name[1] <= "J";
771
                instruction_name[2] <= "O";
772
                end
773
            `IJ_SUB_JOVFLW+1: begin
774
                instruction_name[0] <= "-";
775
                instruction_name[1] <= "J";
776
                instruction_name[2] <= "N";
777
                instruction_name[3] <= "O";
778
                end
779
            `IJ_SUB_JBORROW: begin
780
                instruction_name[0] <= "-";
781
                instruction_name[1] <= "J";
782
                instruction_name[2] <= "C";
783
                end
784
            `IJ_SUB_JBORROW+1: begin
785
                instruction_name[0] <= "-";
786
                instruction_name[1] <= "J";
787
                instruction_name[2] <= "N";
788
                instruction_name[3] <= "C";
789
                end
790
            `IJ_ADD_JZ: begin
791
                instruction_name[0] <= "+";
792
                instruction_name[1] <= "J";
793
                instruction_name[2] <= "Z";
794
                end
795
            `IJ_ADD_JZ+1: begin
796
                instruction_name[0] <= "+";
797
                instruction_name[1] <= "J";
798
                instruction_name[2] <= "N";
799
                instruction_name[3] <= "Z";
800
                end
801
            `IJ_ADD_JNEG: begin
802
                instruction_name[0] <= "+";
803
                instruction_name[1] <= "J";
804
                instruction_name[2] <= "N";
805
                end
806
            `IJ_ADD_JNEG+1: begin
807
                instruction_name[0] <= "+";
808
                instruction_name[1] <= "J";
809
                instruction_name[2] <= "N";
810
                instruction_name[3] <= "N";
811
                end
812
            `IJ_ADD_JPOS: begin
813
                instruction_name[0] <= "+";
814
                instruction_name[1] <= "J";
815
                instruction_name[2] <= "P";
816
                end
817
            `IJ_ADD_JPOS+1: begin
818
                instruction_name[0] <= "+";
819
                instruction_name[1] <= "J";
820
                instruction_name[2] <= "N";
821
                instruction_name[3] <= "P";
822
                end
823
            `IJ_ADD_JOVFLW: begin
824
                instruction_name[0] <= "+";
825
                instruction_name[1] <= "J";
826
                instruction_name[2] <= "O";
827
                end
828
            `IJ_ADD_JOVFLW+1: begin
829
                instruction_name[0] <= "+";
830
                instruction_name[1] <= "J";
831
                instruction_name[2] <= "N";
832
                instruction_name[3] <= "O";
833
                end
834
            `IJ_ADD_JCARRY: begin
835
                instruction_name[0] <= "+";
836
                instruction_name[1] <= "J";
837
                instruction_name[2] <= "C";
838
                end
839
            `IJ_ADD_JCARRY+1: begin
840
                instruction_name[0] <= "+";
841
                instruction_name[1] <= "J";
842
                instruction_name[2] <= "N";
843
                instruction_name[3] <= "C";
844
                end
845
            `IJ_AND_JZ: begin
846
                instruction_name[0] <= "&";
847
                instruction_name[1] <= "J";
848
                instruction_name[2] <= "Z";
849
                end
850
            `IJ_AND_JZ+1: begin
851
                instruction_name[0] <= "&";
852
                instruction_name[1] <= "J";
853
                instruction_name[2] <= "N";
854
                instruction_name[3] <= "Z";
855
                end
856
            `IJ_OR_JZ: begin
857
                instruction_name[0] <= "|";
858
                instruction_name[1] <= "J";
859
                instruction_name[2] <= "Z";
860
                end
861
            `IJ_OR_JZ+1: begin
862
                instruction_name[0] <= "|";
863
                instruction_name[1] <= "J";
864
                instruction_name[2] <= "N";
865
                instruction_name[3] <= "Z";
866
                end
867
            `IJ_XOR_JZ: begin
868
                instruction_name[0] <= "^";
869
                instruction_name[1] <= "J";
870
                instruction_name[2] <= "Z";
871
                end
872
            `IJ_XOR_JZ+1: begin
873
                instruction_name[0] <= "^";
874
                instruction_name[1] <= "J";
875
                instruction_name[2] <= "N";
876
                instruction_name[3] <= "Z";
877
                end
878
            `IJ_COMPARE_JEQ: begin
879
                instruction_name[0] <= "J";
880
                instruction_name[1] <= "=";
881
                instruction_name[2] <= "=";
882
                end
883
            `IJ_COMPARE_JEQ+1: begin
884
                instruction_name[0] <= "J";
885
                instruction_name[1] <= "!";
886
                instruction_name[2] <= "=";
887
                end
888
            `IJ_COMPARE_JSB: begin
889
                instruction_name[0] <= "J";
890
                instruction_name[1] <= "s";
891
                instruction_name[2] <= "<";
892
                end
893
            `IJ_COMPARE_JSB+1: begin
894
                instruction_name[0] <= "J";
895
                instruction_name[1] <= "s";
896
                instruction_name[2] <= ">";
897
                instruction_name[3] <= "=";
898
                end
899
            `IJ_COMPARE_JSA: begin
900
                instruction_name[0] <= "J";
901
                instruction_name[1] <= "s";
902
                instruction_name[2] <= ">";
903
                end
904
            `IJ_COMPARE_JSA+1: begin
905
                instruction_name[0] <= "J";
906
                instruction_name[1] <= "s";
907
                instruction_name[2] <= "<";
908
                instruction_name[3] <= "=";
909
                end
910
            `IJ_COMPARE_JUB: begin
911
                instruction_name[0] <= "J";
912
                instruction_name[1] <= "u";
913
                instruction_name[2] <= "<";
914
                end
915
            `IJ_COMPARE_JUB+1: begin
916
                instruction_name[0] <= "J";
917
                instruction_name[1] <= "u";
918
                instruction_name[2] <= ">";
919
                instruction_name[3] <= "=";
920
                end
921
            `IJ_COMPARE_JUA: begin
922
                instruction_name[0] <= "J";
923
                instruction_name[1] <= "u";
924
                instruction_name[2] <= ">";
925
                end
926
            `IJ_COMPARE_JUA+1: begin
927
                instruction_name[0] <= "J";
928
                instruction_name[1] <= "u";
929
                instruction_name[2] <= "<";
930
                instruction_name[3] <= "=";
931
                end
932
            `IJ_TEST_BIT_JTRUE: begin
933
                instruction_name[0] <= "T";
934
                instruction_name[1] <= "B";
935
                instruction_name[2] <= "I";
936
                instruction_name[3] <= "T";
937
                instruction_name[4] <= "1";
938
                end
939
            `IJ_TEST_BIT_JTRUE+1: begin
940
                instruction_name[0] <= "T";
941
                instruction_name[1] <= "B";
942
                instruction_name[2] <= "I";
943
                instruction_name[3] <= "T";
944
                instruction_name[4] <= "0";
945
                end
946
            `IJ_TEST_BITS_AND: begin
947
                instruction_name[0] <= "T";
948
                instruction_name[1] <= "B";
949
                instruction_name[2] <= "I";
950
                instruction_name[3] <= "T";
951
                instruction_name[4] <= "&";
952
                end
953
            `IJ_TEST_BITS_AND+1: begin
954
                instruction_name[0] <= "T";
955
                instruction_name[1] <= "B";
956
                instruction_name[2] <= "I";
957
                instruction_name[3] <= "T";
958
                instruction_name[4] <= "N";
959
                instruction_name[5] <= "&";
960
                end
961
            `IJ_TEST_BITS_OR: begin
962
                instruction_name[0] <= "T";
963
                instruction_name[1] <= "B";
964
                instruction_name[2] <= "I";
965
                instruction_name[3] <= "T";
966
                instruction_name[4] <= "|";
967
                end
968
            `IJ_TEST_BITS_OR+1: begin
969
                instruction_name[0] <= "T";
970
                instruction_name[1] <= "B";
971
                instruction_name[2] <= "I";
972
                instruction_name[3] <= "T";
973
                instruction_name[4] <= "N";
974
                instruction_name[5] <= "|";
975
                end
976
            `IJ_INC_COMP_JBELOW: begin
977
                instruction_name[0] <= "I";
978
                instruction_name[1] <= "N";
979
                instruction_name[2] <= "C";
980
                instruction_name[3] <= "J";
981
                instruction_name[4] <= "<";
982
                end
983
            `IJ_INC_COMP_JBELOW+1: begin
984
                instruction_name[0] <= "I";
985
                instruction_name[1] <= "N";
986
                instruction_name[2] <= "C";
987
                instruction_name[3] <= "J";
988
                instruction_name[4] <= ">";
989
                instruction_name[5] <= "=";
990
                end
991
            `IJ_INC_COMP_JABOVE: begin
992
                instruction_name[0] <= "I";
993
                instruction_name[1] <= "N";
994
                instruction_name[2] <= "C";
995
                instruction_name[3] <= "J";
996
                instruction_name[4] <= ">";
997
                end
998
            `IJ_INC_COMP_JABOVE+1: begin
999
                instruction_name[0] <= "I";
1000
                instruction_name[1] <= "N";
1001
                instruction_name[2] <= "C";
1002
                instruction_name[3] <= "J";
1003
                instruction_name[4] <= "<";
1004
                instruction_name[5] <= "=";
1005
                end
1006
            `IJ_SUB_MAXLEN_JPOS: begin
1007
                instruction_name[0] <= "L";
1008
                instruction_name[1] <= "O";
1009
                instruction_name[2] <= "O";
1010
                instruction_name[3] <= "P";
1011
                instruction_name[4] <= "-";
1012
                end
1013
            `IJ_SUB_MAXLEN_JPOS+1: begin
1014
                instruction_name[0] <= "L";
1015
                instruction_name[1] <= "O";
1016
                instruction_name[2] <= "O";
1017
                instruction_name[3] <= "P";
1018
                instruction_name[4] <= "+";
1019
                end
1020
            `IJ_RETURN: begin // also sys_return
1021
                instruction_name[0] <= "R";
1022
                instruction_name[1] <= "E";
1023
                instruction_name[2] <= "T";
1024
                instruction_name[3] <= "U";
1025
                instruction_name[4] <= "R";
1026
                instruction_name[5] <= "N";
1027
                end
1028
            `IJ_SYSCALL: begin // also trap
1029
                if (mode == 7) begin // trap
1030
                    instruction_name[0] <= "T";
1031
                    instruction_name[1] <= "R";
1032
                    instruction_name[2] <= "A";
1033
                    instruction_name[3] <= "P";
1034
                end else begin// sys_call
1035
                    instruction_name[0] <= "S";
1036
                    instruction_name[1] <= "Y";
1037
                    instruction_name[2] <= "S";
1038
                    instruction_name[3] <= "C";
1039
                    instruction_name[4] <= "A";
1040
                    instruction_name[5] <= "L";
1041
                    end
1042
                end
1043
            default:
1044
                if (opj >= `IJ_JUMP_INDIRECT_MEM) begin
1045
                    if (opj[0]) begin // indirect call
1046
                        instruction_name[0] <= "C";
1047
                        instruction_name[1] <= "A";
1048
                        instruction_name[2] <= "L";
1049
                        instruction_name[3] <= "L";
1050
                        instruction_name[4] <= "i";
1051
                    end else begin // indirect jump
1052
                        instruction_name[0] <= "J";
1053
                        instruction_name[1] <= "U";
1054
                        instruction_name[2] <= "M";
1055
                        instruction_name[3] <= "P";
1056
                        instruction_name[4] <= "i";
1057
                    end
1058
                end else begin
1059
                    // unknown jump instruction
1060
                    instruction_name[0] <= "J";
1061
                    instruction_name[1] <= "U";
1062
                    instruction_name[2] <= "M";
1063
                    instruction_name[3] <= "P";
1064
                    instruction_name[4] <= "?";
1065
                end
1066
            endcase
1067
        end else begin
1068
            // all other instructions than jump
1069
            case (opx)
1070
            `II_NOP: begin
1071
                instruction_name[0] <= "N";
1072
                instruction_name[1] <= "O";
1073
                instruction_name[2] <= "P";
1074
                end
1075
            `II_MOVE: begin
1076
                instruction_name[0] <= "M";
1077
                instruction_name[1] <= "O";
1078
                instruction_name[2] <= "V";
1079
                instruction_name[3] <= "E";
1080
                end
1081
            `II_STORE: begin
1082
                instruction_name[0] <= "S";
1083
                instruction_name[1] <= "T";
1084
                instruction_name[2] <= "O";
1085
                instruction_name[3] <= "R";
1086
                instruction_name[4] <= "E";
1087
                end
1088
            `II_SIGN_EXTEND: begin
1089
                instruction_name[0] <= "S";
1090
                instruction_name[1] <= "I";
1091
                instruction_name[2] <= "G";
1092
                instruction_name[3] <= "H";
1093
                instruction_name[4] <= "E";
1094
                end
1095
            `II_SIGN_EXTEND_ADD: begin
1096
                instruction_name[0] <= "S";
1097
                instruction_name[1] <= "I";
1098
                instruction_name[2] <= "G";
1099
                instruction_name[3] <= "N";
1100
                instruction_name[4] <= "E";
1101
                instruction_name[5] <= "+";
1102
                end
1103
            `II_COMPARE: begin
1104
                instruction_name[0] <= "C";
1105
                instruction_name[1] <= "O";
1106
                instruction_name[2] <= "M";
1107
                instruction_name[3] <= "P";
1108
                end
1109
            `II_ADD: begin
1110
                instruction_name[0] <= "A";
1111
                instruction_name[1] <= "D";
1112
                instruction_name[2] <= "D";
1113
                end
1114
            `II_SUB: begin
1115
                instruction_name[0] <= "S";
1116
                instruction_name[1] <= "U";
1117
                instruction_name[2] <= "B";
1118
                end
1119
            `II_MUL, `II_MUL_HI, `II_MUL_HI_U: // II_MUL_EX, II_MUL_EX_U
1120
                begin
1121
                instruction_name[0] <= "M";
1122
                instruction_name[1] <= "U";
1123
                instruction_name[2] <= "L";
1124
                end
1125
            `II_DIV, `II_DIV_U: begin
1126
                instruction_name[0] <= "D";
1127
                instruction_name[1] <= "I";
1128
                instruction_name[2] <= "V";
1129
                end
1130
            `II_REM, `II_REM_U: begin
1131
                instruction_name[0] <= "R";
1132
                instruction_name[1] <= "E";
1133
                instruction_name[2] <= "M";
1134
                end
1135
            `II_MIN, `II_MIN_U: begin
1136
                instruction_name[0] <= "M";
1137
                instruction_name[1] <= "I";
1138
                instruction_name[2] <= "N";
1139
                end
1140
            `II_MAX, `II_MAX_U: begin
1141
                instruction_name[0] <= "M";
1142
                instruction_name[1] <= "A";
1143
                instruction_name[2] <= "X";
1144
                end
1145
            `II_AND: begin
1146
                instruction_name[0] <= "A";
1147
                instruction_name[1] <= "N";
1148
                instruction_name[2] <= "D";
1149
                end
1150
            `II_OR: begin
1151
                instruction_name[0] <= "O";
1152
                instruction_name[1] <= "R";
1153
                end
1154
            `II_XOR: begin
1155
                instruction_name[0] <= "X";
1156
                instruction_name[1] <= "O";
1157
                instruction_name[2] <= "R";
1158
                end
1159
            `II_SHIFT_LEFT: begin // also mul_2pow
1160
                instruction_name[0] <= "S";
1161
                instruction_name[1] <= "H";
1162
                instruction_name[2] <= "L";
1163
                end
1164
            `II_ROTATE: begin
1165
                instruction_name[0] <= "R";
1166
                instruction_name[1] <= "O";
1167
                instruction_name[2] <= "T";
1168
                end
1169
            `II_SHIFT_RIGHT_S, `II_SHIFT_RIGHT_U: begin
1170
                instruction_name[0] <= "S";
1171
                instruction_name[1] <= "H";
1172
                instruction_name[2] <= "R";
1173
                end
1174
            `II_SET_BIT: begin
1175
                instruction_name[0] <= "S";
1176
                instruction_name[1] <= "E";
1177
                instruction_name[2] <= "T";
1178
                instruction_name[3] <= "b";
1179
                end
1180
            `II_CLEAR_BIT: begin
1181
                instruction_name[0] <= "C";
1182
                instruction_name[1] <= "L";
1183
                instruction_name[2] <= "E";
1184
                instruction_name[3] <= "A";
1185
                instruction_name[4] <= "R";
1186
                instruction_name[5] <= "b";
1187
                end
1188
            `II_TOGGLE_BIT: begin
1189
                instruction_name[0] <= "T";
1190
                instruction_name[1] <= "O";
1191
                instruction_name[2] <= "G";
1192
                instruction_name[3] <= "G";
1193
                instruction_name[4] <= "L";
1194
                instruction_name[5] <= "b";
1195
                end
1196
            `II_TEST_BIT: begin
1197
                instruction_name[0] <= "T";
1198
                instruction_name[1] <= "E";
1199
                instruction_name[2] <= "S";
1200
                instruction_name[3] <= "T";
1201
                instruction_name[4] <= "b";
1202
                end
1203
            `II_TEST_BITS_AND: begin
1204
                instruction_name[0] <= "T";
1205
                instruction_name[1] <= "E";
1206
                instruction_name[2] <= "S";
1207
                instruction_name[3] <= "T";
1208
                instruction_name[4] <= "b";
1209
                instruction_name[5] <= "&";
1210
                end
1211
            `II_TEST_BITS_OR: begin
1212
                instruction_name[0] <= "T";
1213
                instruction_name[1] <= "E";
1214
                instruction_name[2] <= "S";
1215
                instruction_name[3] <= "T";
1216
                instruction_name[4] <= "b";
1217
                instruction_name[5] <= "|";
1218
                end
1219
            `II_ADD_FLOAT16: begin
1220
                instruction_name[0] <= "A";
1221
                instruction_name[1] <= "D";
1222
                instruction_name[2] <= "D";
1223
                instruction_name[3] <= "h";
1224
                end
1225
            `II_SUB_FLOAT16: begin
1226
                instruction_name[0] <= "S";
1227
                instruction_name[1] <= "U";
1228
                instruction_name[2] <= "B";
1229
                instruction_name[3] <= "h";
1230
                end
1231
            `II_MUL_FLOAT16: begin
1232
                instruction_name[0] <= "M";
1233
                instruction_name[1] <= "U";
1234
                instruction_name[2] <= "L";
1235
                instruction_name[3] <= "h";
1236
                end
1237
            `II_MUL_ADD_FLOAT16: begin
1238
                instruction_name[0] <= "M";
1239
                instruction_name[1] <= "U";
1240
                instruction_name[2] <= "L";
1241
                instruction_name[3] <= "A";
1242
                instruction_name[4] <= "h";
1243
                end
1244
            `II_MUL_ADD, `II_MUL_ADD2: begin
1245
                instruction_name[0] <= "M";
1246
                instruction_name[1] <= "U";
1247
                instruction_name[2] <= "L";
1248
                instruction_name[3] <= "A";
1249
                end
1250
            `II_ADD_ADD: begin
1251
                instruction_name[0] <= "A";
1252
                instruction_name[1] <= "D";
1253
                instruction_name[2] <= "D";
1254
                instruction_name[3] <= "A";
1255
                instruction_name[4] <= "D";
1256
                instruction_name[5] <= "D";
1257
                end
1258
            `II_SELECT_BITS: begin
1259
                instruction_name[0] <= "S";
1260
                instruction_name[1] <= "E";
1261
                instruction_name[2] <= "L";
1262
                instruction_name[3] <= "E";
1263
                instruction_name[4] <= "C";
1264
                instruction_name[5] <= "T";
1265
                end
1266
            `II_FUNNEL_SHIFT: begin
1267
                instruction_name[0] <= "F";
1268
                instruction_name[1] <= "U";
1269
                instruction_name[2] <= "N";
1270
                instruction_name[3] <= "N";
1271
                instruction_name[4] <= "E";
1272
                instruction_name[5] <= "L";
1273
                end
1274
            `IX_ABS: begin
1275
                instruction_name[0] <= "A";
1276
                instruction_name[1] <= "B";
1277
                instruction_name[2] <= "S";
1278
                end
1279
            `IX_BIT_SCAN: begin
1280
                instruction_name[0] <= "B";
1281
                instruction_name[1] <= "S";
1282
                instruction_name[2] <= "C";
1283
                instruction_name[3] <= "A";
1284
                instruction_name[4] <= "N";
1285
                end
1286
            `IX_ROUNDP2: begin
1287
                instruction_name[0] <= "R";
1288
                instruction_name[1] <= "N";
1289
                instruction_name[2] <= "D";
1290
                instruction_name[3] <= "P";
1291
                instruction_name[4] <= "2";
1292
                end
1293
            `IX_POPCOUNT: begin
1294
                instruction_name[0] <= "P";
1295
                instruction_name[1] <= "O";
1296
                instruction_name[2] <= "P";
1297
                instruction_name[3] <= "C";
1298
                instruction_name[4] <= "N";
1299
                instruction_name[5] <= "T";
1300
                end
1301
            `IX_READ_SPEC: begin
1302
                instruction_name[0] <= "R";
1303
                instruction_name[1] <= "D";
1304
                instruction_name[2] <= " ";
1305
                instruction_name[3] <= "S";
1306
                instruction_name[4] <= "P";
1307
                instruction_name[5] <= "C";
1308
                end
1309
            `IX_WRITE_SPEC: begin
1310
                instruction_name[0] <= "W";
1311
                instruction_name[1] <= "R";
1312
                instruction_name[2] <= " ";
1313
                instruction_name[3] <= "S";
1314
                instruction_name[4] <= "P";
1315
                instruction_name[5] <= "C";
1316
                end
1317
            `IX_READ_CAPABILITIES: begin
1318
                instruction_name[0] <= "R";
1319
                instruction_name[1] <= "D";
1320
                instruction_name[2] <= " ";
1321
                instruction_name[3] <= "C";
1322
                instruction_name[4] <= "A";
1323
                instruction_name[5] <= "P";
1324
                end
1325
            `IX_WRITE_CAPABILITIES: begin
1326
                instruction_name[0] <= "W";
1327
                instruction_name[1] <= "R";
1328
                instruction_name[2] <= " ";
1329
                instruction_name[3] <= "C";
1330
                instruction_name[4] <= "A";
1331
                instruction_name[5] <= "P";
1332
                end
1333
            `IX_READ_PERF, `IX_READ_PERFS: begin
1334
                instruction_name[0] <= "R";
1335
                instruction_name[1] <= "D";
1336
                instruction_name[2] <= " ";
1337
                instruction_name[3] <= "P";
1338
                instruction_name[4] <= "E";
1339
                instruction_name[5] <= "R";
1340
                end
1341
            `IX_READ_SYS: begin
1342
                instruction_name[0] <= "R";
1343
                instruction_name[1] <= "D";
1344
                instruction_name[2] <= " ";
1345
                instruction_name[3] <= "S";
1346
                instruction_name[4] <= "Y";
1347
                instruction_name[5] <= "S";
1348
                end
1349
            `IX_WRITE_SYS: begin
1350
                instruction_name[0] <= "W";
1351
                instruction_name[1] <= "R";
1352
                instruction_name[2] <= " ";
1353
                instruction_name[3] <= "S";
1354
                instruction_name[4] <= "Y";
1355
                instruction_name[5] <= "S";
1356
                end
1357
            `IX_MOVE_BITS1, `IX_MOVE_BITS2: begin
1358
                instruction_name[0] <= "M";
1359
                instruction_name[1] <= "O";
1360
                instruction_name[2] <= "V";
1361
                instruction_name[3] <= "b";
1362
                end
1363
            `IX_SHIFT32: begin
1364
                instruction_name[0] <= "<";
1365
                instruction_name[1] <= "<";
1366
                instruction_name[2] <= "3";
1367
                instruction_name[3] <= "2";
1368
                end
1369
            `IX_INSERT_HI: begin
1370
                instruction_name[0] <= "I";
1371
                instruction_name[1] <= "N";
1372
                instruction_name[2] <= "S";
1373
                instruction_name[3] <= "h";
1374
                instruction_name[4] <= "i";
1375
                end
1376
            `IX_ADDRESS: begin
1377
                instruction_name[0] <= "A";
1378
                instruction_name[1] <= "D";
1379
                instruction_name[2] <= "D";
1380
                instruction_name[3] <= "R";
1381
                end
1382
            `IX_TRUTH_TAB3: begin
1383
                instruction_name[0] <= "T";
1384
                instruction_name[1] <= "T";
1385
                instruction_name[2] <= "A";
1386
                instruction_name[3] <= "B";
1387
                instruction_name[4] <= "3";
1388
                end
1389
            `IX_INPUT: begin
1390
                instruction_name[0] <= "I";
1391
                instruction_name[1] <= "N";
1392
                instruction_name[2] <= "P";
1393
                instruction_name[3] <= "U";
1394
                instruction_name[4] <= "T";
1395
                end
1396
            `IX_OUTPUT: begin
1397
                instruction_name[0] <= "O";
1398
                instruction_name[1] <= "U";
1399
                instruction_name[2] <= "T";
1400
                instruction_name[3] <= "P";
1401
                instruction_name[4] <= "U";
1402
                instruction_name[5] <= "T";
1403
                end
1404
 
1405
            default: begin
1406
                // unknown instruction
1407
                instruction_name[0] <= "?";
1408
                instruction_name[1] <= "?";
1409
                instruction_name[2] <= "?";
1410
                end
1411
            endcase
1412
        end
1413
    end
1414
end
1415
 
1416
endmodule

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