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[/] [forwardcom/] [trunk/] [seg7.sv] - Blame information for rev 129

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1 8 Agner
//////////////////////////////////////////////////////////////////////////////////
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// Engineer: Agner Fog
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//
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// Create Date:    2020-05-01
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// Last modified:  2021-04-30
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// Module Name:    seg7
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// Project Name:   ForwardCom soft core
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// Target Devices: Artix 7
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// Tool Versions:  Vivado v. 2020.1
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// License:        CERN-OHL-W v. 2 or later
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// Description:    Decoder and driver for 8 digit 7 segment display
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//////////////////////////////////////////////////////////////////////////////////
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// Driver for 8 digit, 7 segment multiplexed display
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module seg7 (
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    input clock,                       // system clock 100 MHz
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    input [31:0] dispin,               // input, hexadecimal or BCD
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    input [7:0] enable,                // enable each digit
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    output reg [7:0] segment7seg,      // segment output, active low
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    output reg [7:0] digit7seg         // digit select output, active low
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);
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reg [14:0]  count = 0;
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logic [2:0] index;
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logic [3:0] digit;
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logic [7:0] segment;
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always_comb begin
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    index[2:0] = count[13:11];         // digit index
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    digit[3:0] = dispin >> (index*4);  // digit value
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    case(digit)    //   pgfedcba  7-segment bit pattern lookup
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        0: segment = 8'b00111111;
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        1: segment = 8'b00000110;
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        2: segment = 8'b01011011;
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        3: segment = 8'b01001111;
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        4: segment = 8'b01100110;
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        5: segment = 8'b01101101;
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        6: segment = 8'b01111101;
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        7: segment = 8'b00000111;
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        8: segment = 8'b01111111;
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        9: segment = 8'b01101111;
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     4'hA: segment = 8'b01110111;
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     4'hB: segment = 8'b01111100;
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     4'hC: segment = 8'b00111001;
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     4'hD: segment = 8'b01011110;
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     4'hE: segment = 8'b01111001;
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     4'hF: segment = 8'b01110001;
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    endcase
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end
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always_ff @(posedge clock) begin
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    count <= count + 1;               // clock divider
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    if (count[10:0] == 0) begin   // scan rate = clock / 2**11
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        segment7seg <= ~segment;  // active low output
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        /*
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        if (enable[index])
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            digit7seg <= ~(8'b1 << index);  // enable one digit at index
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        else
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            digit7seg <= 8'b11111111;       // disabled digit
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        */
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        digit7seg <= ~((8'b1 << index) & enable);  // enable one digit at index
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    end;
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end
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endmodule

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