OpenCores
URL https://opencores.org/ocsvn/forwardcom/forwardcom/trunk

Subversion Repositories forwardcom

[/] [forwardcom/] [trunk/] [seg7.sv] - Blame information for rev 52

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 8 Agner
//////////////////////////////////////////////////////////////////////////////////
2
// Engineer: Agner Fog
3
//
4
// Create Date:    2020-05-01
5
// Last modified:  2021-04-30
6
// Module Name:    seg7
7
// Project Name:   ForwardCom soft core
8
// Target Devices: Artix 7
9
// Tool Versions:  Vivado v. 2020.1
10
// License:        CERN-OHL-W v. 2 or later
11
// Description:    Decoder and driver for 8 digit 7 segment display
12
//////////////////////////////////////////////////////////////////////////////////
13
 
14
 
15
// Driver for 8 digit, 7 segment multiplexed display
16
module seg7 (
17
    input clock,                       // system clock 100 MHz
18
    input [31:0] dispin,               // input, hexadecimal or BCD
19
    input [7:0] enable,                // enable each digit
20
    output reg [7:0] segment7seg,      // segment output, active low
21
    output reg [7:0] digit7seg         // digit select output, active low
22
);
23
reg [14:0]  count = 0;
24
logic [2:0] index;
25
logic [3:0] digit;
26
logic [7:0] segment;
27
 
28
always_comb begin
29
    index[2:0] = count[13:11];         // digit index
30
    digit[3:0] = dispin >> (index*4);  // digit value
31
    case(digit)    //   pgfedcba  7-segment bit pattern lookup
32
        0: segment = 8'b00111111;
33
        1: segment = 8'b00000110;
34
        2: segment = 8'b01011011;
35
        3: segment = 8'b01001111;
36
        4: segment = 8'b01100110;
37
        5: segment = 8'b01101101;
38
        6: segment = 8'b01111101;
39
        7: segment = 8'b00000111;
40
        8: segment = 8'b01111111;
41
        9: segment = 8'b01101111;
42
     4'hA: segment = 8'b01110111;
43
     4'hB: segment = 8'b01111100;
44
     4'hC: segment = 8'b00111001;
45
     4'hD: segment = 8'b01011110;
46
     4'hE: segment = 8'b01111001;
47
     4'hF: segment = 8'b01110001;
48
    endcase
49
end
50
 
51
always_ff @(posedge clock) begin
52
    count <= count + 1;               // clock divider
53
 
54
    if (count[10:0] == 0) begin   // scan rate = clock / 2**11
55
        segment7seg <= ~segment;  // active low output
56
        /*
57
        if (enable[index])
58
            digit7seg <= ~(8'b1 << index);  // enable one digit at index
59
        else
60
            digit7seg <= 8'b11111111;       // disabled digit
61
        */
62
        digit7seg <= ~((8'b1 << index) & enable);  // enable one digit at index
63
 
64
    end;
65
 
66
end
67
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.