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1 11 Agner
//////////////////////////////////////////////////////////////////////////////////
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// Engineer: Agner Fog
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//
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// Create date:    2020-11-01
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// Last modified:  2021-07-02
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// Module name:    uart_and_fifo
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// Project name:   ForwardCom soft core
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// Tool versions:  Vivado 2020.1
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// License:        CERN-OHL-W v. 2 or later
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// Description:    UART: RS232 serial interface
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// 8 data bits, 1 stop bit, no parity
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// Description:    fifo_buffer: First-in-first-out byte queue.
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//
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//////////////////////////////////////////////////////////////////////////////////
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// CLOCK_FREQUENCY and BAUD_RATE defined in defines.vh:
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`include "defines.vh"
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// UART receiver
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module UART_RX (
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    input            reset,                      // clear buffer, reset everything
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    input            clock,                      // clock at `CLOCK_RATE
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    input            rx_in,                      // RX input
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    output reg       receive_complete_out,       // byte received. Will be high for 1 clock cycle after the middle of the stop bit
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    output reg       error_out,                  // transmission error. Remains high until reset in case of error
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    output reg [7:0] byte_out                    // byte output
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);
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// clock count per bit
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localparam CLKS_PER_BIT = `CLOCK_FREQUENCY / `BAUD_RATE;
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// state names
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localparam STATE_IDLE      = 4'b0000;            // wait for start bit
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localparam STATE_START_BIT = 4'b0001;            // start bit detected
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localparam STATE_DATA_0    = 4'b1000;            // read first data bit
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localparam STATE_DATA_7    = 4'b1111;            // read last data bit
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localparam STATE_STOP_BIT  = 4'b0010;            // read stop bit
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reg [$clog2(CLKS_PER_BIT)-1:0] clock_counter;    // clock counter for length of one bit
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reg [3:0] state;  // state
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// state machine for UART receiver
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always_ff @(posedge clock) begin
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    if (reset) begin
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        // reset everything
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        state <= STATE_IDLE;
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        receive_complete_out <= 0;
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        error_out <= 0;
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        clock_counter <= 0;
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        byte_out <= 0;
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    end else if (state == STATE_IDLE) begin
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        // wait for start bit
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        receive_complete_out <= 0;
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        clock_counter <= 0;
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        if (rx_in == 0) begin                    // Start bit detected
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            state <= STATE_START_BIT;
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        end
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    end else if (state == STATE_START_BIT) begin
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        // start bit detected. wait until middle of start bit
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        if (clock_counter == CLKS_PER_BIT / 2) begin // middle of start bit
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            if (rx_in == 0) begin
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                clock_counter <= 0;              // reset counter to the middle of the start bit
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                state     <= STATE_DATA_0;
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            end else begin
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                error_out <= 1;                  // error. start bit shorter than a half period. possibly wrong BAUD rate
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                state <= STATE_IDLE;
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            end
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        end else begin
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            clock_counter <= clock_counter + 1;  // count time until next bit
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        end
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    end else if (state[3]) begin                 // this covers STATE_DATA_0 ... STATE_DATA_7
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        // read eight data bits
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        if (clock_counter < CLKS_PER_BIT-1) begin
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            clock_counter <= clock_counter + 1;  // count time until next bit
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        end else begin                           // middle of data bit. sample bit and go to next state
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            clock_counter        <= 0;
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            byte_out[state[2:0]] <= rx_in;       // save data bit
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            if (state == STATE_DATA_7) state <= STATE_STOP_BIT; // next state is stop bit
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            else state <= state + 1;                            // next data bit
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        end
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    end else if (state == STATE_STOP_BIT) begin
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        // expecting stop bit
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        if (clock_counter < CLKS_PER_BIT-1) begin
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            clock_counter <= clock_counter + 1;  // count time until stop bit
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        end else begin                           // middle of stop bit
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            if (rx_in == 0) begin                // error: stop bit missing
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                error_out <= 1;
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                state <= STATE_IDLE;
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            end else begin
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                receive_complete_out <= 1;       // byte received successfully
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                clock_counter <= 0;
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                // We are in the middle of the stop bit.
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                // Go to state IDLE while waiting for a possible next start bit.
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                // This is expected to last a half period
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                state <= STATE_IDLE;
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            end
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        end
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    end else begin
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        // Error. undefined state
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        error_out <= 1;
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        state <= STATE_IDLE;
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    end
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end
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endmodule // UART_RX
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// UART transmitter
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module UART_TX (
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   input       reset,                            // reset
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   input       clock,                            // clock at `CLOCK_RATE
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   input       start_in,                         // command to send one byte
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   input [7:0] byte_in,                          // byte input
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   output reg  active_out,                       // is busy
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   output reg  tx_out,                           // TX output
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   output reg  done_out                          // will be high for one clock cycle shortly before the end of the stop bit
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   );                                            // You may use done_out as a signal to prepare the next byte
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// clock count per bit
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localparam CLKS_PER_BIT = `CLOCK_FREQUENCY / `BAUD_RATE;
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// state names
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localparam STATE_IDLE      = 4'b0000;            // wait for start bit
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localparam STATE_START_BIT = 4'b0001;            // start bit detected
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localparam STATE_DATA_0    = 4'b1000;            // read first data bit
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localparam STATE_DATA_7    = 4'b1111;            // read last data bit
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localparam STATE_STOP_BIT  = 4'b0010;            // read stop bit
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reg [3:0] state;                                 // state
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reg [$clog2(CLKS_PER_BIT)-1:0] clock_counter;    // clock counter for length of one bit
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reg [7:0] byte_data;                             // copy of byte to transmit
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// state machine
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always_ff @(posedge clock) begin
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    if (reset) begin
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        // reset everything
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        state <= STATE_IDLE;
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        clock_counter <= 0;
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        active_out    <= 0;
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        done_out      <= 0;
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        tx_out        <= 1;                      // output must be high when idle
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    end else if (state == STATE_IDLE) begin
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        clock_counter <= 0;
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        done_out      <= 0;
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        tx_out        <= 1;                      // output must be high when idle
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        if (start_in) begin                      // start sending a byte
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            active_out <= 1;
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            byte_data  <= byte_in;               // copy input byte
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            state <= STATE_START_BIT;
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        end
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160
    end else if (state == STATE_START_BIT) begin
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        // start bit must be 0
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        tx_out <= 0;
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        // Wait for start bit to finish
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        if (clock_counter < CLKS_PER_BIT-1) begin
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            clock_counter <= clock_counter + 1;
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        end else begin
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            clock_counter <= 0;
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            state <= STATE_DATA_0;               // go to first data bit
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        end
171
 
172
    end else if (state[3]) begin                 // this covers STATE_DATA_0 ... STATE_DATA_7
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        // write eight data bits
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        tx_out <= byte_data[state[2:0]];         // send one data bit
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        // Wait for data bit to finish
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        if (clock_counter < CLKS_PER_BIT-1) begin
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            clock_counter <= clock_counter + 1;
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        end else begin
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            clock_counter <= 0;
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            if (state == STATE_DATA_7) state <= STATE_STOP_BIT; // next bit is stop bit
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            else state <= state + 1;                            // next bit is data bit
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        end
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    end else if (state == STATE_STOP_BIT) begin
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        // send stop bit
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        tx_out <= 1;                             // stop bit must be 1
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        // send request for next byte shortly before finished with this byte
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        if (clock_counter == CLKS_PER_BIT-4) begin
191
            done_out <= 1;                       // set done_out high for one clock cycle to request next byte from buffer
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        end else begin
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            done_out <= 0;
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        end
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        // Wait for stop bit to finish
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        if (clock_counter < CLKS_PER_BIT-1) begin
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            clock_counter <= clock_counter + 1;
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        end else begin
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            clock_counter <= 0;
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            begin
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                active_out <= 0;
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                state      <= STATE_IDLE;        // wait at least one clock for next start_in signal
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            end
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        end
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    end else begin
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        // illegal state. reset
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        state <= STATE_IDLE;
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        clock_counter <= 0;
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        active_out <= 0;
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        done_out <= 0;
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        tx_out   <= 1;
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    end
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end
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endmodule
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/******************************************************************************
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* First-in-first-out byte queue.
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*
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* This queue is implemented as a circular buffer.
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* The size can be any power of 2.
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* It may be implemented as distributed RAM or block RAM if the size is large.
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* (Vivado does this automatically)
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* It is possible to read and write simultaneously as long as the queue is not
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* empty. It is not possible to pass a byte directly from input to output without
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* a delay of two clocks if the buffer is empty.
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* The input, byte_in, is placed at the tail of the queue at the rising edge of clock.
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* The output, byte_out, is prefetched so that it is ready to read before the
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* clock edge. The read_next input signal will remove one byte from the head of
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* the queue and put the next byte into byte_out.
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* The data_ready_out output tells if it is possible to read a byte
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******************************************************************************/
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module fifo_buffer
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#(parameter size_log2 = 10)                      // buffer size = 2**size_log2 bytes
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(
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    input            reset,                      // clear buffer and reset error condition
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    input            reset_error,                // reset error condition
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    input            clock,                      // clock at `CLOCK_RATE
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    input            read_next,                  // read next byte from buffer
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    input            write,                      // write one byte to buffer
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    input  [7:0]     byte_in,                    // serial byte input
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    output reg [7:0] byte_out,                   // serial byte output prefetched
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    output reg       data_ready_out,             // the buffer contains at least one byte
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    output reg       overflow,                   // attempt to write to full buffer
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    output reg       underflow,                  // attempt to read from empty buffer
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    output reg [size_log2-1:0] num               // number of bytes currently in buffer
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);
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reg [7:0] buffer[0 : (2**size_log2)-1];          // circular buffer
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reg [size_log2-1:0] head;                        // pointer to head position where bytes are extracted
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reg [size_log2-1:0] tail;                        // pointer to tail position where bytes are inserted
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258
logic [size_log2-1:0] head_plus_1;               // (head + 1) modulo 2**(size_log2)
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260
 
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always_ff @(posedge clock) begin
262
 
263
    if (reset) begin
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        // clear buffer, reset everything
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        head <= 0;
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        tail <= 0;
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        byte_out <= 0;
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        num <= 0;
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        data_ready_out <= 0;
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        overflow <= 0;
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        underflow <= 0;
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    end else if (reset_error) begin
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        // reset error flags
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        overflow <= 0;
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        underflow <= 0;
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    end else begin
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        if (write) begin
278
            // insert a byte in buffer
279
            if (&num) begin
280
                // buffer is full
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                overflow <= 1;
282
            end else begin
283
                // buffer is not full
284
                buffer[tail] <= byte_in;         // insert at tail position
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                // advance tail
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                tail <= tail + 1;                // this will wrap around because size is a power of 2
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                // count bytes in buffer
289
                if (!read_next) begin
290
                    num <= num + 1;
291
                end
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            end
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        end
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        // make output ready
296
        if (num == 0 || read_next && num == 1) begin
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            byte_out <= 0;
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            data_ready_out <= 0;
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        end else if (read_next) begin
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            byte_out <= buffer[head_plus_1];     // read byte and make next byte ready from head position
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            data_ready_out <= 1;
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        end else begin
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            byte_out <= buffer[head];            // make byte read ready from head position
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            data_ready_out <= 1;
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        end
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307
        if (read_next) begin
308
            // read a byte from buffer
309
            if (~data_ready_out) begin           // reading from empty buffer
310
                underflow <= 1;
311
            end else begin
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                // advance head
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                head <= head_plus_1;             // this will wrap around because size is a power of 2
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                // count bytes in buffer
315
                if (!write) begin
316
                    num <= num - 1;
317
                end
318
            end
319
        end
320
    end
321
end
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324
always_comb begin
325
    head_plus_1 = head + 1;                      // (head + 1) with size_log2 bits
326
end
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endmodule

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