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--
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-- Title : Project structure
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-- Design : fp24fftk
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-- Author : Kapitanov
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-- Company :
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--
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-- (c) Copyright 2015
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-- Kapitanov.
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-- All rights reserved.
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---- The hierarchy of folders ----
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-- FFT : FFT and IFFT top logic
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-- fp24_delay : delay lines package (short, medium, long)
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-- fp24_init : logic for Twiddle extraction
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-- fp24_dpram_inbuf : input buffer for FFT logic (1k-64k points)
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-- fp24_dpram_ofbuf : support function buffer (for example in "Pulse compression" processing)
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-- fp24_op : floating point arithmetic (add, sub, mult, fix2fp, fp2fix)
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-- sp24_op : some useful logic (full-adder, extended multipliers)
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-- fp24_twiddle : butterflies DIT/DIF, coefficients extraction
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-- fp24_core_v6 : xilinx corelibs shift registers*
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---- * Xilinx CoreGEN files will be replaced by own logic in the next versions
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---- * Xilinx CoreGEN files don't inlude in the project
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---- Software for testing**: ----
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-- Aldec Active-HDL 9.3: https://www.aldec.com/
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-- Xilinx ISE 14.7: http://www.xilinx.com/
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-- Visual studio 2012 : https://www.visualstudio.com/
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-- MathCAD 13: http://www.ptc.com/product/mathcad
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---- Aldec Active-HDL used to testing all fp24fftk project.
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---- Xilinx ISE used for synthesis and implementation.
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---- Visual studio used to generate some test signals and to comapare an output RTL data with the "golden data".
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---- MathCAD used to visualize signals representation (in the time and frequency domains).
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---- Addition information:
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-- This project also contains some files to self-testing.
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-- tb: testbench file
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-- log: 3 files for writing/reading in/out testbench
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