1 |
2 |
NikosAl |
--------------------------------------------------------------------------------
|
2 |
|
|
-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
|
3 |
|
|
--------------------------------------------------------------------------------
|
4 |
|
|
-- ____ ____
|
5 |
|
|
-- / /\/ /
|
6 |
|
|
-- /___/ \ / Vendor: Xilinx
|
7 |
|
|
-- \ \ \/ Version: K.39
|
8 |
|
|
-- \ \ Application: netgen
|
9 |
|
|
-- / / Filename: mant_lut_MEM.vhd
|
10 |
|
|
-- /___/ /\ Timestamp: Fri Jul 24 15:10:43 2009
|
11 |
|
|
-- \ \ / \
|
12 |
|
|
-- \___\/\___\
|
13 |
|
|
--
|
14 |
|
|
-- Command : -intstyle ise -w -sim -ofmt vhdl "C:\Documents and Settings\Administrator\Desktop\Felsenstein Coprocessor\Logarithm LUT based\HW Implementation\Coregen\tmp\_cg\mant_lut_MEM.ngc" "C:\Documents and Settings\Administrator\Desktop\Felsenstein Coprocessor\Logarithm LUT based\HW Implementation\Coregen\tmp\_cg\mant_lut_MEM.vhd"
|
15 |
|
|
-- Device : 5vsx95tff1136-1
|
16 |
|
|
-- Input file : C:/Documents and Settings/Administrator/Desktop/Felsenstein Coprocessor/Logarithm LUT based/HW Implementation/Coregen/tmp/_cg/mant_lut_MEM.ngc
|
17 |
|
|
-- Output file : C:/Documents and Settings/Administrator/Desktop/Felsenstein Coprocessor/Logarithm LUT based/HW Implementation/Coregen/tmp/_cg/mant_lut_MEM.vhd
|
18 |
|
|
-- # of Entities : 1
|
19 |
|
|
-- Design Name : mant_lut_MEM
|
20 |
|
|
-- Xilinx : C:\Xilinx\10.1\ISE
|
21 |
|
|
--
|
22 |
|
|
-- Purpose:
|
23 |
|
|
-- This VHDL netlist is a verification model and uses simulation
|
24 |
|
|
-- primitives which may not represent the true implementation of the
|
25 |
|
|
-- device, however the netlist is functionally correct and should not
|
26 |
|
|
-- be modified. This file cannot be synthesized and should only be used
|
27 |
|
|
-- with supported simulation tools.
|
28 |
|
|
--
|
29 |
|
|
-- Reference:
|
30 |
|
|
-- Development System Reference Guide, Chapter 23
|
31 |
|
|
-- Synthesis and Simulation Design Guide, Chapter 6
|
32 |
|
|
--
|
33 |
|
|
--------------------------------------------------------------------------------
|
34 |
|
|
|
35 |
|
|
|
36 |
|
|
-- synthesis translate_off
|
37 |
|
|
library IEEE;
|
38 |
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
39 |
|
|
library UNISIM;
|
40 |
|
|
use UNISIM.VCOMPONENTS.ALL;
|
41 |
|
|
use UNISIM.VPKG.ALL;
|
42 |
|
|
|
43 |
|
|
entity mant_lut_MEM is
|
44 |
|
|
port (
|
45 |
|
|
clka : in STD_LOGIC := 'X';
|
46 |
|
|
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
|
47 |
|
|
douta : out STD_LOGIC_VECTOR ( 26 downto 0 )
|
48 |
|
|
);
|
49 |
|
|
end mant_lut_MEM;
|
50 |
|
|
|
51 |
|
|
architecture STRUCTURE of mant_lut_MEM is
|
52 |
|
|
signal BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_0_cmp_eq0000 : STD_LOGIC;
|
53 |
|
|
signal BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_1_cmp_eq0000 : STD_LOGIC;
|
54 |
|
|
signal BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_2_cmp_eq0000 : STD_LOGIC;
|
55 |
|
|
signal BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_3_cmp_eq0000 : STD_LOGIC;
|
56 |
|
|
signal BU2_N1 : STD_LOGIC;
|
57 |
|
|
signal NLW_VCC_P_UNCONNECTED : STD_LOGIC;
|
58 |
|
|
signal NLW_GND_G_UNCONNECTED : STD_LOGIC;
|
59 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATA_UNCONNECTED : STD_LOGIC;
|
60 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATB_UNCONNECTED : STD_LOGIC;
|
61 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGA_UNCONNECTED : STD_LOGIC;
|
62 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGB_UNCONNECTED : STD_LOGIC;
|
63 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_7_UNCONNECTED : STD_LOGIC;
|
64 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_6_UNCONNECTED : STD_LOGIC;
|
65 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_5_UNCONNECTED : STD_LOGIC;
|
66 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_4_UNCONNECTED : STD_LOGIC;
|
67 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_7_UNCONNECTED : STD_LOGIC;
|
68 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_6_UNCONNECTED : STD_LOGIC;
|
69 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_5_UNCONNECTED : STD_LOGIC;
|
70 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_4_UNCONNECTED : STD_LOGIC;
|
71 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_31_UNCONNECTED : STD_LOGIC;
|
72 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_30_UNCONNECTED : STD_LOGIC;
|
73 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_29_UNCONNECTED : STD_LOGIC;
|
74 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_28_UNCONNECTED : STD_LOGIC;
|
75 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_27_UNCONNECTED : STD_LOGIC;
|
76 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_26_UNCONNECTED : STD_LOGIC;
|
77 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_25_UNCONNECTED : STD_LOGIC;
|
78 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_24_UNCONNECTED : STD_LOGIC;
|
79 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_23_UNCONNECTED : STD_LOGIC;
|
80 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_22_UNCONNECTED : STD_LOGIC;
|
81 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_21_UNCONNECTED : STD_LOGIC;
|
82 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_20_UNCONNECTED : STD_LOGIC;
|
83 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_19_UNCONNECTED : STD_LOGIC;
|
84 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_18_UNCONNECTED : STD_LOGIC;
|
85 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_17_UNCONNECTED : STD_LOGIC;
|
86 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_16_UNCONNECTED : STD_LOGIC;
|
87 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_15_UNCONNECTED : STD_LOGIC;
|
88 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_14_UNCONNECTED : STD_LOGIC;
|
89 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_13_UNCONNECTED : STD_LOGIC;
|
90 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_12_UNCONNECTED : STD_LOGIC;
|
91 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_11_UNCONNECTED : STD_LOGIC;
|
92 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_10_UNCONNECTED : STD_LOGIC;
|
93 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_9_UNCONNECTED : STD_LOGIC;
|
94 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_8_UNCONNECTED : STD_LOGIC;
|
95 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_3_UNCONNECTED : STD_LOGIC;
|
96 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_2_UNCONNECTED : STD_LOGIC;
|
97 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_1_UNCONNECTED : STD_LOGIC;
|
98 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_31_UNCONNECTED : STD_LOGIC;
|
99 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_30_UNCONNECTED : STD_LOGIC;
|
100 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_29_UNCONNECTED : STD_LOGIC;
|
101 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_28_UNCONNECTED : STD_LOGIC;
|
102 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_27_UNCONNECTED : STD_LOGIC;
|
103 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_26_UNCONNECTED : STD_LOGIC;
|
104 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_25_UNCONNECTED : STD_LOGIC;
|
105 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_24_UNCONNECTED : STD_LOGIC;
|
106 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_23_UNCONNECTED : STD_LOGIC;
|
107 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_22_UNCONNECTED : STD_LOGIC;
|
108 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_21_UNCONNECTED : STD_LOGIC;
|
109 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_20_UNCONNECTED : STD_LOGIC;
|
110 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_19_UNCONNECTED : STD_LOGIC;
|
111 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_18_UNCONNECTED : STD_LOGIC;
|
112 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_17_UNCONNECTED : STD_LOGIC;
|
113 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_16_UNCONNECTED : STD_LOGIC;
|
114 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_15_UNCONNECTED : STD_LOGIC;
|
115 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_14_UNCONNECTED : STD_LOGIC;
|
116 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_13_UNCONNECTED : STD_LOGIC;
|
117 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_12_UNCONNECTED : STD_LOGIC;
|
118 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_11_UNCONNECTED : STD_LOGIC;
|
119 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_10_UNCONNECTED : STD_LOGIC;
|
120 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_9_UNCONNECTED : STD_LOGIC;
|
121 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_8_UNCONNECTED : STD_LOGIC;
|
122 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_7_UNCONNECTED : STD_LOGIC;
|
123 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_6_UNCONNECTED : STD_LOGIC;
|
124 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_5_UNCONNECTED : STD_LOGIC;
|
125 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_4_UNCONNECTED : STD_LOGIC;
|
126 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_3_UNCONNECTED : STD_LOGIC;
|
127 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_2_UNCONNECTED : STD_LOGIC;
|
128 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_1_UNCONNECTED : STD_LOGIC;
|
129 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_0_UNCONNECTED : STD_LOGIC;
|
130 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_3_UNCONNECTED : STD_LOGIC;
|
131 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_2_UNCONNECTED : STD_LOGIC;
|
132 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_1_UNCONNECTED : STD_LOGIC;
|
133 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_0_UNCONNECTED : STD_LOGIC;
|
134 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATA_UNCONNECTED : STD_LOGIC;
|
135 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATB_UNCONNECTED : STD_LOGIC;
|
136 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGA_UNCONNECTED : STD_LOGIC;
|
137 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGB_UNCONNECTED : STD_LOGIC;
|
138 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_7_UNCONNECTED : STD_LOGIC;
|
139 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_6_UNCONNECTED : STD_LOGIC;
|
140 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_5_UNCONNECTED : STD_LOGIC;
|
141 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_4_UNCONNECTED : STD_LOGIC;
|
142 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_7_UNCONNECTED : STD_LOGIC;
|
143 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_6_UNCONNECTED : STD_LOGIC;
|
144 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_5_UNCONNECTED : STD_LOGIC;
|
145 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_4_UNCONNECTED : STD_LOGIC;
|
146 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_31_UNCONNECTED : STD_LOGIC;
|
147 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_30_UNCONNECTED : STD_LOGIC;
|
148 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_29_UNCONNECTED : STD_LOGIC;
|
149 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_28_UNCONNECTED : STD_LOGIC;
|
150 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_27_UNCONNECTED : STD_LOGIC;
|
151 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_26_UNCONNECTED : STD_LOGIC;
|
152 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_25_UNCONNECTED : STD_LOGIC;
|
153 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_24_UNCONNECTED : STD_LOGIC;
|
154 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_23_UNCONNECTED : STD_LOGIC;
|
155 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_22_UNCONNECTED : STD_LOGIC;
|
156 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_21_UNCONNECTED : STD_LOGIC;
|
157 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_20_UNCONNECTED : STD_LOGIC;
|
158 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_19_UNCONNECTED : STD_LOGIC;
|
159 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_18_UNCONNECTED : STD_LOGIC;
|
160 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_17_UNCONNECTED : STD_LOGIC;
|
161 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_16_UNCONNECTED : STD_LOGIC;
|
162 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_15_UNCONNECTED : STD_LOGIC;
|
163 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_14_UNCONNECTED : STD_LOGIC;
|
164 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_13_UNCONNECTED : STD_LOGIC;
|
165 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_12_UNCONNECTED : STD_LOGIC;
|
166 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_11_UNCONNECTED : STD_LOGIC;
|
167 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_10_UNCONNECTED : STD_LOGIC;
|
168 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_9_UNCONNECTED : STD_LOGIC;
|
169 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_8_UNCONNECTED : STD_LOGIC;
|
170 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_3_UNCONNECTED : STD_LOGIC;
|
171 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_2_UNCONNECTED : STD_LOGIC;
|
172 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_1_UNCONNECTED : STD_LOGIC;
|
173 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_31_UNCONNECTED : STD_LOGIC;
|
174 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_30_UNCONNECTED : STD_LOGIC;
|
175 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_29_UNCONNECTED : STD_LOGIC;
|
176 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_28_UNCONNECTED : STD_LOGIC;
|
177 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_27_UNCONNECTED : STD_LOGIC;
|
178 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_26_UNCONNECTED : STD_LOGIC;
|
179 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_25_UNCONNECTED : STD_LOGIC;
|
180 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_24_UNCONNECTED : STD_LOGIC;
|
181 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_23_UNCONNECTED : STD_LOGIC;
|
182 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_22_UNCONNECTED : STD_LOGIC;
|
183 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_21_UNCONNECTED : STD_LOGIC;
|
184 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_20_UNCONNECTED : STD_LOGIC;
|
185 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_19_UNCONNECTED : STD_LOGIC;
|
186 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_18_UNCONNECTED : STD_LOGIC;
|
187 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_17_UNCONNECTED : STD_LOGIC;
|
188 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_16_UNCONNECTED : STD_LOGIC;
|
189 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_15_UNCONNECTED : STD_LOGIC;
|
190 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_14_UNCONNECTED : STD_LOGIC;
|
191 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_13_UNCONNECTED : STD_LOGIC;
|
192 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_12_UNCONNECTED : STD_LOGIC;
|
193 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_11_UNCONNECTED : STD_LOGIC;
|
194 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_10_UNCONNECTED : STD_LOGIC;
|
195 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_9_UNCONNECTED : STD_LOGIC;
|
196 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_8_UNCONNECTED : STD_LOGIC;
|
197 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_7_UNCONNECTED : STD_LOGIC;
|
198 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_6_UNCONNECTED : STD_LOGIC;
|
199 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_5_UNCONNECTED : STD_LOGIC;
|
200 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_4_UNCONNECTED : STD_LOGIC;
|
201 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_3_UNCONNECTED : STD_LOGIC;
|
202 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_2_UNCONNECTED : STD_LOGIC;
|
203 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_1_UNCONNECTED : STD_LOGIC;
|
204 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_0_UNCONNECTED : STD_LOGIC;
|
205 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_3_UNCONNECTED : STD_LOGIC;
|
206 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_2_UNCONNECTED : STD_LOGIC;
|
207 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_1_UNCONNECTED : STD_LOGIC;
|
208 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_0_UNCONNECTED : STD_LOGIC;
|
209 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATA_UNCONNECTED : STD_LOGIC;
|
210 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATB_UNCONNECTED : STD_LOGIC;
|
211 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGA_UNCONNECTED : STD_LOGIC;
|
212 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGB_UNCONNECTED : STD_LOGIC;
|
213 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_7_UNCONNECTED : STD_LOGIC;
|
214 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_6_UNCONNECTED : STD_LOGIC;
|
215 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_5_UNCONNECTED : STD_LOGIC;
|
216 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_4_UNCONNECTED : STD_LOGIC;
|
217 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_7_UNCONNECTED : STD_LOGIC;
|
218 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_6_UNCONNECTED : STD_LOGIC;
|
219 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_5_UNCONNECTED : STD_LOGIC;
|
220 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_4_UNCONNECTED : STD_LOGIC;
|
221 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_31_UNCONNECTED : STD_LOGIC;
|
222 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_30_UNCONNECTED : STD_LOGIC;
|
223 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_29_UNCONNECTED : STD_LOGIC;
|
224 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_28_UNCONNECTED : STD_LOGIC;
|
225 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_27_UNCONNECTED : STD_LOGIC;
|
226 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_26_UNCONNECTED : STD_LOGIC;
|
227 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_25_UNCONNECTED : STD_LOGIC;
|
228 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_24_UNCONNECTED : STD_LOGIC;
|
229 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_23_UNCONNECTED : STD_LOGIC;
|
230 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_22_UNCONNECTED : STD_LOGIC;
|
231 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_21_UNCONNECTED : STD_LOGIC;
|
232 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_20_UNCONNECTED : STD_LOGIC;
|
233 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_19_UNCONNECTED : STD_LOGIC;
|
234 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_18_UNCONNECTED : STD_LOGIC;
|
235 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_17_UNCONNECTED : STD_LOGIC;
|
236 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_16_UNCONNECTED : STD_LOGIC;
|
237 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_15_UNCONNECTED : STD_LOGIC;
|
238 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_14_UNCONNECTED : STD_LOGIC;
|
239 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_13_UNCONNECTED : STD_LOGIC;
|
240 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_12_UNCONNECTED : STD_LOGIC;
|
241 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_11_UNCONNECTED : STD_LOGIC;
|
242 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_10_UNCONNECTED : STD_LOGIC;
|
243 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_9_UNCONNECTED : STD_LOGIC;
|
244 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_8_UNCONNECTED : STD_LOGIC;
|
245 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_3_UNCONNECTED : STD_LOGIC;
|
246 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_2_UNCONNECTED : STD_LOGIC;
|
247 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_1_UNCONNECTED : STD_LOGIC;
|
248 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_31_UNCONNECTED : STD_LOGIC;
|
249 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_30_UNCONNECTED : STD_LOGIC;
|
250 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_29_UNCONNECTED : STD_LOGIC;
|
251 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_28_UNCONNECTED : STD_LOGIC;
|
252 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_27_UNCONNECTED : STD_LOGIC;
|
253 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_26_UNCONNECTED : STD_LOGIC;
|
254 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_25_UNCONNECTED : STD_LOGIC;
|
255 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_24_UNCONNECTED : STD_LOGIC;
|
256 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_23_UNCONNECTED : STD_LOGIC;
|
257 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_22_UNCONNECTED : STD_LOGIC;
|
258 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_21_UNCONNECTED : STD_LOGIC;
|
259 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_20_UNCONNECTED : STD_LOGIC;
|
260 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_19_UNCONNECTED : STD_LOGIC;
|
261 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_18_UNCONNECTED : STD_LOGIC;
|
262 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_17_UNCONNECTED : STD_LOGIC;
|
263 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_16_UNCONNECTED : STD_LOGIC;
|
264 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_15_UNCONNECTED : STD_LOGIC;
|
265 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_14_UNCONNECTED : STD_LOGIC;
|
266 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_13_UNCONNECTED : STD_LOGIC;
|
267 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_12_UNCONNECTED : STD_LOGIC;
|
268 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_11_UNCONNECTED : STD_LOGIC;
|
269 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_10_UNCONNECTED : STD_LOGIC;
|
270 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_9_UNCONNECTED : STD_LOGIC;
|
271 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_8_UNCONNECTED : STD_LOGIC;
|
272 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_7_UNCONNECTED : STD_LOGIC;
|
273 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_6_UNCONNECTED : STD_LOGIC;
|
274 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_5_UNCONNECTED : STD_LOGIC;
|
275 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_4_UNCONNECTED : STD_LOGIC;
|
276 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_3_UNCONNECTED : STD_LOGIC;
|
277 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_2_UNCONNECTED : STD_LOGIC;
|
278 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_1_UNCONNECTED : STD_LOGIC;
|
279 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_0_UNCONNECTED : STD_LOGIC;
|
280 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_3_UNCONNECTED : STD_LOGIC;
|
281 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_2_UNCONNECTED : STD_LOGIC;
|
282 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_1_UNCONNECTED : STD_LOGIC;
|
283 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_0_UNCONNECTED : STD_LOGIC;
|
284 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATA_UNCONNECTED : STD_LOGIC;
|
285 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATB_UNCONNECTED : STD_LOGIC;
|
286 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGA_UNCONNECTED : STD_LOGIC;
|
287 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGB_UNCONNECTED : STD_LOGIC;
|
288 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_7_UNCONNECTED : STD_LOGIC;
|
289 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_6_UNCONNECTED : STD_LOGIC;
|
290 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_5_UNCONNECTED : STD_LOGIC;
|
291 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_4_UNCONNECTED : STD_LOGIC;
|
292 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_7_UNCONNECTED : STD_LOGIC;
|
293 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_6_UNCONNECTED : STD_LOGIC;
|
294 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_5_UNCONNECTED : STD_LOGIC;
|
295 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_4_UNCONNECTED : STD_LOGIC;
|
296 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_31_UNCONNECTED : STD_LOGIC;
|
297 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_30_UNCONNECTED : STD_LOGIC;
|
298 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_29_UNCONNECTED : STD_LOGIC;
|
299 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_28_UNCONNECTED : STD_LOGIC;
|
300 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_27_UNCONNECTED : STD_LOGIC;
|
301 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_26_UNCONNECTED : STD_LOGIC;
|
302 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_25_UNCONNECTED : STD_LOGIC;
|
303 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_24_UNCONNECTED : STD_LOGIC;
|
304 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_23_UNCONNECTED : STD_LOGIC;
|
305 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_22_UNCONNECTED : STD_LOGIC;
|
306 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_21_UNCONNECTED : STD_LOGIC;
|
307 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_20_UNCONNECTED : STD_LOGIC;
|
308 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_19_UNCONNECTED : STD_LOGIC;
|
309 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_18_UNCONNECTED : STD_LOGIC;
|
310 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_17_UNCONNECTED : STD_LOGIC;
|
311 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_16_UNCONNECTED : STD_LOGIC;
|
312 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_15_UNCONNECTED : STD_LOGIC;
|
313 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_14_UNCONNECTED : STD_LOGIC;
|
314 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_13_UNCONNECTED : STD_LOGIC;
|
315 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_12_UNCONNECTED : STD_LOGIC;
|
316 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_11_UNCONNECTED : STD_LOGIC;
|
317 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_10_UNCONNECTED : STD_LOGIC;
|
318 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_9_UNCONNECTED : STD_LOGIC;
|
319 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_8_UNCONNECTED : STD_LOGIC;
|
320 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_3_UNCONNECTED : STD_LOGIC;
|
321 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_2_UNCONNECTED : STD_LOGIC;
|
322 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_1_UNCONNECTED : STD_LOGIC;
|
323 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_31_UNCONNECTED : STD_LOGIC;
|
324 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_30_UNCONNECTED : STD_LOGIC;
|
325 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_29_UNCONNECTED : STD_LOGIC;
|
326 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_28_UNCONNECTED : STD_LOGIC;
|
327 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_27_UNCONNECTED : STD_LOGIC;
|
328 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_26_UNCONNECTED : STD_LOGIC;
|
329 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_25_UNCONNECTED : STD_LOGIC;
|
330 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_24_UNCONNECTED : STD_LOGIC;
|
331 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_23_UNCONNECTED : STD_LOGIC;
|
332 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_22_UNCONNECTED : STD_LOGIC;
|
333 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_21_UNCONNECTED : STD_LOGIC;
|
334 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_20_UNCONNECTED : STD_LOGIC;
|
335 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_19_UNCONNECTED : STD_LOGIC;
|
336 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_18_UNCONNECTED : STD_LOGIC;
|
337 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_17_UNCONNECTED : STD_LOGIC;
|
338 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_16_UNCONNECTED : STD_LOGIC;
|
339 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_15_UNCONNECTED : STD_LOGIC;
|
340 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_14_UNCONNECTED : STD_LOGIC;
|
341 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_13_UNCONNECTED : STD_LOGIC;
|
342 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_12_UNCONNECTED : STD_LOGIC;
|
343 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_11_UNCONNECTED : STD_LOGIC;
|
344 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_10_UNCONNECTED : STD_LOGIC;
|
345 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_9_UNCONNECTED : STD_LOGIC;
|
346 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_8_UNCONNECTED : STD_LOGIC;
|
347 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_7_UNCONNECTED : STD_LOGIC;
|
348 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_6_UNCONNECTED : STD_LOGIC;
|
349 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_5_UNCONNECTED : STD_LOGIC;
|
350 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_4_UNCONNECTED : STD_LOGIC;
|
351 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_3_UNCONNECTED : STD_LOGIC;
|
352 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_2_UNCONNECTED : STD_LOGIC;
|
353 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_1_UNCONNECTED : STD_LOGIC;
|
354 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_0_UNCONNECTED : STD_LOGIC;
|
355 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_3_UNCONNECTED : STD_LOGIC;
|
356 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_2_UNCONNECTED : STD_LOGIC;
|
357 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_1_UNCONNECTED : STD_LOGIC;
|
358 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_0_UNCONNECTED : STD_LOGIC;
|
359 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATA_UNCONNECTED : STD_LOGIC;
|
360 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATB_UNCONNECTED : STD_LOGIC;
|
361 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGA_UNCONNECTED : STD_LOGIC;
|
362 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGB_UNCONNECTED : STD_LOGIC;
|
363 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_7_UNCONNECTED : STD_LOGIC;
|
364 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_6_UNCONNECTED : STD_LOGIC;
|
365 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_5_UNCONNECTED : STD_LOGIC;
|
366 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_4_UNCONNECTED : STD_LOGIC;
|
367 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_7_UNCONNECTED : STD_LOGIC;
|
368 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_6_UNCONNECTED : STD_LOGIC;
|
369 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_5_UNCONNECTED : STD_LOGIC;
|
370 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_4_UNCONNECTED : STD_LOGIC;
|
371 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_31_UNCONNECTED : STD_LOGIC;
|
372 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_30_UNCONNECTED : STD_LOGIC;
|
373 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_29_UNCONNECTED : STD_LOGIC;
|
374 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_28_UNCONNECTED : STD_LOGIC;
|
375 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_27_UNCONNECTED : STD_LOGIC;
|
376 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_26_UNCONNECTED : STD_LOGIC;
|
377 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_25_UNCONNECTED : STD_LOGIC;
|
378 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_24_UNCONNECTED : STD_LOGIC;
|
379 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_23_UNCONNECTED : STD_LOGIC;
|
380 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_22_UNCONNECTED : STD_LOGIC;
|
381 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_21_UNCONNECTED : STD_LOGIC;
|
382 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_20_UNCONNECTED : STD_LOGIC;
|
383 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_19_UNCONNECTED : STD_LOGIC;
|
384 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_18_UNCONNECTED : STD_LOGIC;
|
385 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_17_UNCONNECTED : STD_LOGIC;
|
386 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_16_UNCONNECTED : STD_LOGIC;
|
387 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_15_UNCONNECTED : STD_LOGIC;
|
388 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_14_UNCONNECTED : STD_LOGIC;
|
389 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_13_UNCONNECTED : STD_LOGIC;
|
390 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_12_UNCONNECTED : STD_LOGIC;
|
391 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_11_UNCONNECTED : STD_LOGIC;
|
392 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_10_UNCONNECTED : STD_LOGIC;
|
393 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_9_UNCONNECTED : STD_LOGIC;
|
394 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_8_UNCONNECTED : STD_LOGIC;
|
395 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_3_UNCONNECTED : STD_LOGIC;
|
396 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_2_UNCONNECTED : STD_LOGIC;
|
397 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_1_UNCONNECTED : STD_LOGIC;
|
398 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_31_UNCONNECTED : STD_LOGIC;
|
399 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_30_UNCONNECTED : STD_LOGIC;
|
400 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_29_UNCONNECTED : STD_LOGIC;
|
401 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_28_UNCONNECTED : STD_LOGIC;
|
402 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_27_UNCONNECTED : STD_LOGIC;
|
403 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_26_UNCONNECTED : STD_LOGIC;
|
404 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_25_UNCONNECTED : STD_LOGIC;
|
405 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_24_UNCONNECTED : STD_LOGIC;
|
406 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_23_UNCONNECTED : STD_LOGIC;
|
407 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_22_UNCONNECTED : STD_LOGIC;
|
408 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_21_UNCONNECTED : STD_LOGIC;
|
409 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_20_UNCONNECTED : STD_LOGIC;
|
410 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_19_UNCONNECTED : STD_LOGIC;
|
411 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_18_UNCONNECTED : STD_LOGIC;
|
412 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_17_UNCONNECTED : STD_LOGIC;
|
413 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_16_UNCONNECTED : STD_LOGIC;
|
414 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_15_UNCONNECTED : STD_LOGIC;
|
415 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_14_UNCONNECTED : STD_LOGIC;
|
416 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_13_UNCONNECTED : STD_LOGIC;
|
417 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_12_UNCONNECTED : STD_LOGIC;
|
418 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_11_UNCONNECTED : STD_LOGIC;
|
419 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_10_UNCONNECTED : STD_LOGIC;
|
420 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_9_UNCONNECTED : STD_LOGIC;
|
421 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_8_UNCONNECTED : STD_LOGIC;
|
422 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_7_UNCONNECTED : STD_LOGIC;
|
423 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_6_UNCONNECTED : STD_LOGIC;
|
424 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_5_UNCONNECTED : STD_LOGIC;
|
425 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_4_UNCONNECTED : STD_LOGIC;
|
426 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_3_UNCONNECTED : STD_LOGIC;
|
427 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_2_UNCONNECTED : STD_LOGIC;
|
428 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_1_UNCONNECTED : STD_LOGIC;
|
429 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_0_UNCONNECTED : STD_LOGIC;
|
430 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_3_UNCONNECTED : STD_LOGIC;
|
431 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_2_UNCONNECTED : STD_LOGIC;
|
432 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_1_UNCONNECTED : STD_LOGIC;
|
433 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_0_UNCONNECTED : STD_LOGIC;
|
434 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATA_UNCONNECTED : STD_LOGIC;
|
435 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATB_UNCONNECTED : STD_LOGIC;
|
436 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGA_UNCONNECTED : STD_LOGIC;
|
437 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGB_UNCONNECTED : STD_LOGIC;
|
438 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_7_UNCONNECTED : STD_LOGIC;
|
439 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_6_UNCONNECTED : STD_LOGIC;
|
440 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_5_UNCONNECTED : STD_LOGIC;
|
441 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_4_UNCONNECTED : STD_LOGIC;
|
442 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_7_UNCONNECTED : STD_LOGIC;
|
443 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_6_UNCONNECTED : STD_LOGIC;
|
444 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_5_UNCONNECTED : STD_LOGIC;
|
445 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_4_UNCONNECTED : STD_LOGIC;
|
446 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_31_UNCONNECTED : STD_LOGIC;
|
447 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_30_UNCONNECTED : STD_LOGIC;
|
448 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_29_UNCONNECTED : STD_LOGIC;
|
449 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_28_UNCONNECTED : STD_LOGIC;
|
450 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_27_UNCONNECTED : STD_LOGIC;
|
451 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_26_UNCONNECTED : STD_LOGIC;
|
452 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_25_UNCONNECTED : STD_LOGIC;
|
453 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_24_UNCONNECTED : STD_LOGIC;
|
454 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_23_UNCONNECTED : STD_LOGIC;
|
455 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_22_UNCONNECTED : STD_LOGIC;
|
456 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_21_UNCONNECTED : STD_LOGIC;
|
457 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_20_UNCONNECTED : STD_LOGIC;
|
458 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_19_UNCONNECTED : STD_LOGIC;
|
459 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_18_UNCONNECTED : STD_LOGIC;
|
460 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_17_UNCONNECTED : STD_LOGIC;
|
461 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_16_UNCONNECTED : STD_LOGIC;
|
462 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_15_UNCONNECTED : STD_LOGIC;
|
463 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_14_UNCONNECTED : STD_LOGIC;
|
464 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_13_UNCONNECTED : STD_LOGIC;
|
465 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_12_UNCONNECTED : STD_LOGIC;
|
466 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_11_UNCONNECTED : STD_LOGIC;
|
467 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_10_UNCONNECTED : STD_LOGIC;
|
468 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_9_UNCONNECTED : STD_LOGIC;
|
469 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_8_UNCONNECTED : STD_LOGIC;
|
470 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_3_UNCONNECTED : STD_LOGIC;
|
471 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_2_UNCONNECTED : STD_LOGIC;
|
472 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_1_UNCONNECTED : STD_LOGIC;
|
473 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_31_UNCONNECTED : STD_LOGIC;
|
474 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_30_UNCONNECTED : STD_LOGIC;
|
475 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_29_UNCONNECTED : STD_LOGIC;
|
476 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_28_UNCONNECTED : STD_LOGIC;
|
477 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_27_UNCONNECTED : STD_LOGIC;
|
478 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_26_UNCONNECTED : STD_LOGIC;
|
479 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_25_UNCONNECTED : STD_LOGIC;
|
480 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_24_UNCONNECTED : STD_LOGIC;
|
481 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_23_UNCONNECTED : STD_LOGIC;
|
482 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_22_UNCONNECTED : STD_LOGIC;
|
483 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_21_UNCONNECTED : STD_LOGIC;
|
484 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_20_UNCONNECTED : STD_LOGIC;
|
485 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_19_UNCONNECTED : STD_LOGIC;
|
486 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_18_UNCONNECTED : STD_LOGIC;
|
487 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_17_UNCONNECTED : STD_LOGIC;
|
488 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_16_UNCONNECTED : STD_LOGIC;
|
489 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_15_UNCONNECTED : STD_LOGIC;
|
490 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_14_UNCONNECTED : STD_LOGIC;
|
491 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_13_UNCONNECTED : STD_LOGIC;
|
492 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_12_UNCONNECTED : STD_LOGIC;
|
493 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_11_UNCONNECTED : STD_LOGIC;
|
494 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_10_UNCONNECTED : STD_LOGIC;
|
495 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_9_UNCONNECTED : STD_LOGIC;
|
496 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_8_UNCONNECTED : STD_LOGIC;
|
497 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_7_UNCONNECTED : STD_LOGIC;
|
498 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_6_UNCONNECTED : STD_LOGIC;
|
499 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_5_UNCONNECTED : STD_LOGIC;
|
500 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_4_UNCONNECTED : STD_LOGIC;
|
501 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_3_UNCONNECTED : STD_LOGIC;
|
502 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_2_UNCONNECTED : STD_LOGIC;
|
503 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_1_UNCONNECTED : STD_LOGIC;
|
504 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_0_UNCONNECTED : STD_LOGIC;
|
505 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_3_UNCONNECTED : STD_LOGIC;
|
506 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_2_UNCONNECTED : STD_LOGIC;
|
507 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_1_UNCONNECTED : STD_LOGIC;
|
508 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_0_UNCONNECTED : STD_LOGIC;
|
509 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATA_UNCONNECTED : STD_LOGIC;
|
510 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATB_UNCONNECTED : STD_LOGIC;
|
511 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGA_UNCONNECTED : STD_LOGIC;
|
512 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGB_UNCONNECTED : STD_LOGIC;
|
513 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_7_UNCONNECTED : STD_LOGIC;
|
514 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_6_UNCONNECTED : STD_LOGIC;
|
515 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_5_UNCONNECTED : STD_LOGIC;
|
516 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_4_UNCONNECTED : STD_LOGIC;
|
517 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_7_UNCONNECTED : STD_LOGIC;
|
518 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_6_UNCONNECTED : STD_LOGIC;
|
519 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_5_UNCONNECTED : STD_LOGIC;
|
520 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_4_UNCONNECTED : STD_LOGIC;
|
521 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_31_UNCONNECTED : STD_LOGIC;
|
522 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_30_UNCONNECTED : STD_LOGIC;
|
523 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_29_UNCONNECTED : STD_LOGIC;
|
524 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_28_UNCONNECTED : STD_LOGIC;
|
525 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_27_UNCONNECTED : STD_LOGIC;
|
526 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_26_UNCONNECTED : STD_LOGIC;
|
527 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_25_UNCONNECTED : STD_LOGIC;
|
528 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_24_UNCONNECTED : STD_LOGIC;
|
529 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_23_UNCONNECTED : STD_LOGIC;
|
530 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_22_UNCONNECTED : STD_LOGIC;
|
531 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_21_UNCONNECTED : STD_LOGIC;
|
532 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_20_UNCONNECTED : STD_LOGIC;
|
533 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_19_UNCONNECTED : STD_LOGIC;
|
534 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_18_UNCONNECTED : STD_LOGIC;
|
535 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_17_UNCONNECTED : STD_LOGIC;
|
536 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_16_UNCONNECTED : STD_LOGIC;
|
537 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_15_UNCONNECTED : STD_LOGIC;
|
538 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_14_UNCONNECTED : STD_LOGIC;
|
539 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_13_UNCONNECTED : STD_LOGIC;
|
540 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_12_UNCONNECTED : STD_LOGIC;
|
541 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_11_UNCONNECTED : STD_LOGIC;
|
542 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_10_UNCONNECTED : STD_LOGIC;
|
543 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_9_UNCONNECTED : STD_LOGIC;
|
544 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_8_UNCONNECTED : STD_LOGIC;
|
545 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_3_UNCONNECTED : STD_LOGIC;
|
546 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_2_UNCONNECTED : STD_LOGIC;
|
547 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_1_UNCONNECTED : STD_LOGIC;
|
548 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_31_UNCONNECTED : STD_LOGIC;
|
549 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_30_UNCONNECTED : STD_LOGIC;
|
550 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_29_UNCONNECTED : STD_LOGIC;
|
551 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_28_UNCONNECTED : STD_LOGIC;
|
552 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_27_UNCONNECTED : STD_LOGIC;
|
553 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_26_UNCONNECTED : STD_LOGIC;
|
554 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_25_UNCONNECTED : STD_LOGIC;
|
555 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_24_UNCONNECTED : STD_LOGIC;
|
556 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_23_UNCONNECTED : STD_LOGIC;
|
557 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_22_UNCONNECTED : STD_LOGIC;
|
558 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_21_UNCONNECTED : STD_LOGIC;
|
559 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_20_UNCONNECTED : STD_LOGIC;
|
560 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_19_UNCONNECTED : STD_LOGIC;
|
561 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_18_UNCONNECTED : STD_LOGIC;
|
562 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_17_UNCONNECTED : STD_LOGIC;
|
563 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_16_UNCONNECTED : STD_LOGIC;
|
564 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_15_UNCONNECTED : STD_LOGIC;
|
565 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_14_UNCONNECTED : STD_LOGIC;
|
566 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_13_UNCONNECTED : STD_LOGIC;
|
567 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_12_UNCONNECTED : STD_LOGIC;
|
568 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_11_UNCONNECTED : STD_LOGIC;
|
569 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_10_UNCONNECTED : STD_LOGIC;
|
570 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_9_UNCONNECTED : STD_LOGIC;
|
571 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_8_UNCONNECTED : STD_LOGIC;
|
572 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_7_UNCONNECTED : STD_LOGIC;
|
573 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_6_UNCONNECTED : STD_LOGIC;
|
574 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_5_UNCONNECTED : STD_LOGIC;
|
575 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_4_UNCONNECTED : STD_LOGIC;
|
576 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_3_UNCONNECTED : STD_LOGIC;
|
577 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_2_UNCONNECTED : STD_LOGIC;
|
578 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_1_UNCONNECTED : STD_LOGIC;
|
579 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_0_UNCONNECTED : STD_LOGIC;
|
580 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_3_UNCONNECTED : STD_LOGIC;
|
581 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_2_UNCONNECTED : STD_LOGIC;
|
582 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_1_UNCONNECTED : STD_LOGIC;
|
583 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_0_UNCONNECTED : STD_LOGIC;
|
584 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATA_UNCONNECTED : STD_LOGIC;
|
585 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATB_UNCONNECTED : STD_LOGIC;
|
586 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGA_UNCONNECTED : STD_LOGIC;
|
587 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGB_UNCONNECTED : STD_LOGIC;
|
588 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_7_UNCONNECTED : STD_LOGIC;
|
589 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_6_UNCONNECTED : STD_LOGIC;
|
590 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_5_UNCONNECTED : STD_LOGIC;
|
591 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_4_UNCONNECTED : STD_LOGIC;
|
592 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_7_UNCONNECTED : STD_LOGIC;
|
593 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_6_UNCONNECTED : STD_LOGIC;
|
594 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_5_UNCONNECTED : STD_LOGIC;
|
595 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_4_UNCONNECTED : STD_LOGIC;
|
596 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_31_UNCONNECTED : STD_LOGIC;
|
597 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_30_UNCONNECTED : STD_LOGIC;
|
598 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_29_UNCONNECTED : STD_LOGIC;
|
599 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_28_UNCONNECTED : STD_LOGIC;
|
600 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_27_UNCONNECTED : STD_LOGIC;
|
601 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_26_UNCONNECTED : STD_LOGIC;
|
602 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_25_UNCONNECTED : STD_LOGIC;
|
603 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_24_UNCONNECTED : STD_LOGIC;
|
604 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_23_UNCONNECTED : STD_LOGIC;
|
605 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_22_UNCONNECTED : STD_LOGIC;
|
606 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_21_UNCONNECTED : STD_LOGIC;
|
607 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_20_UNCONNECTED : STD_LOGIC;
|
608 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_19_UNCONNECTED : STD_LOGIC;
|
609 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_18_UNCONNECTED : STD_LOGIC;
|
610 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_17_UNCONNECTED : STD_LOGIC;
|
611 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_16_UNCONNECTED : STD_LOGIC;
|
612 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_15_UNCONNECTED : STD_LOGIC;
|
613 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_14_UNCONNECTED : STD_LOGIC;
|
614 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_13_UNCONNECTED : STD_LOGIC;
|
615 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_12_UNCONNECTED : STD_LOGIC;
|
616 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_11_UNCONNECTED : STD_LOGIC;
|
617 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_10_UNCONNECTED : STD_LOGIC;
|
618 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_9_UNCONNECTED : STD_LOGIC;
|
619 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_8_UNCONNECTED : STD_LOGIC;
|
620 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_3_UNCONNECTED : STD_LOGIC;
|
621 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_2_UNCONNECTED : STD_LOGIC;
|
622 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_1_UNCONNECTED : STD_LOGIC;
|
623 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_31_UNCONNECTED : STD_LOGIC;
|
624 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_30_UNCONNECTED : STD_LOGIC;
|
625 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_29_UNCONNECTED : STD_LOGIC;
|
626 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_28_UNCONNECTED : STD_LOGIC;
|
627 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_27_UNCONNECTED : STD_LOGIC;
|
628 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_26_UNCONNECTED : STD_LOGIC;
|
629 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_25_UNCONNECTED : STD_LOGIC;
|
630 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_24_UNCONNECTED : STD_LOGIC;
|
631 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_23_UNCONNECTED : STD_LOGIC;
|
632 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_22_UNCONNECTED : STD_LOGIC;
|
633 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_21_UNCONNECTED : STD_LOGIC;
|
634 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_20_UNCONNECTED : STD_LOGIC;
|
635 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_19_UNCONNECTED : STD_LOGIC;
|
636 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_18_UNCONNECTED : STD_LOGIC;
|
637 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_17_UNCONNECTED : STD_LOGIC;
|
638 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_16_UNCONNECTED : STD_LOGIC;
|
639 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_15_UNCONNECTED : STD_LOGIC;
|
640 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_14_UNCONNECTED : STD_LOGIC;
|
641 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_13_UNCONNECTED : STD_LOGIC;
|
642 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_12_UNCONNECTED : STD_LOGIC;
|
643 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_11_UNCONNECTED : STD_LOGIC;
|
644 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_10_UNCONNECTED : STD_LOGIC;
|
645 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_9_UNCONNECTED : STD_LOGIC;
|
646 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_8_UNCONNECTED : STD_LOGIC;
|
647 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_7_UNCONNECTED : STD_LOGIC;
|
648 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_6_UNCONNECTED : STD_LOGIC;
|
649 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_5_UNCONNECTED : STD_LOGIC;
|
650 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_4_UNCONNECTED : STD_LOGIC;
|
651 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_3_UNCONNECTED : STD_LOGIC;
|
652 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_2_UNCONNECTED : STD_LOGIC;
|
653 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_1_UNCONNECTED : STD_LOGIC;
|
654 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_0_UNCONNECTED : STD_LOGIC;
|
655 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_3_UNCONNECTED : STD_LOGIC;
|
656 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_2_UNCONNECTED : STD_LOGIC;
|
657 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_1_UNCONNECTED : STD_LOGIC;
|
658 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_0_UNCONNECTED : STD_LOGIC;
|
659 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATA_UNCONNECTED : STD_LOGIC;
|
660 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATB_UNCONNECTED : STD_LOGIC;
|
661 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGA_UNCONNECTED : STD_LOGIC;
|
662 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGB_UNCONNECTED : STD_LOGIC;
|
663 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_7_UNCONNECTED : STD_LOGIC;
|
664 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_6_UNCONNECTED : STD_LOGIC;
|
665 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_5_UNCONNECTED : STD_LOGIC;
|
666 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_4_UNCONNECTED : STD_LOGIC;
|
667 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_7_UNCONNECTED : STD_LOGIC;
|
668 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_6_UNCONNECTED : STD_LOGIC;
|
669 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_5_UNCONNECTED : STD_LOGIC;
|
670 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_4_UNCONNECTED : STD_LOGIC;
|
671 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_31_UNCONNECTED : STD_LOGIC;
|
672 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_30_UNCONNECTED : STD_LOGIC;
|
673 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_29_UNCONNECTED : STD_LOGIC;
|
674 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_28_UNCONNECTED : STD_LOGIC;
|
675 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_27_UNCONNECTED : STD_LOGIC;
|
676 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_26_UNCONNECTED : STD_LOGIC;
|
677 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_25_UNCONNECTED : STD_LOGIC;
|
678 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_24_UNCONNECTED : STD_LOGIC;
|
679 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_23_UNCONNECTED : STD_LOGIC;
|
680 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_22_UNCONNECTED : STD_LOGIC;
|
681 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_21_UNCONNECTED : STD_LOGIC;
|
682 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_20_UNCONNECTED : STD_LOGIC;
|
683 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_19_UNCONNECTED : STD_LOGIC;
|
684 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_18_UNCONNECTED : STD_LOGIC;
|
685 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_17_UNCONNECTED : STD_LOGIC;
|
686 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_16_UNCONNECTED : STD_LOGIC;
|
687 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_15_UNCONNECTED : STD_LOGIC;
|
688 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_14_UNCONNECTED : STD_LOGIC;
|
689 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_13_UNCONNECTED : STD_LOGIC;
|
690 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_12_UNCONNECTED : STD_LOGIC;
|
691 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_11_UNCONNECTED : STD_LOGIC;
|
692 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_10_UNCONNECTED : STD_LOGIC;
|
693 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_9_UNCONNECTED : STD_LOGIC;
|
694 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_8_UNCONNECTED : STD_LOGIC;
|
695 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_3_UNCONNECTED : STD_LOGIC;
|
696 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_2_UNCONNECTED : STD_LOGIC;
|
697 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_1_UNCONNECTED : STD_LOGIC;
|
698 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_31_UNCONNECTED : STD_LOGIC;
|
699 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_30_UNCONNECTED : STD_LOGIC;
|
700 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_29_UNCONNECTED : STD_LOGIC;
|
701 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_28_UNCONNECTED : STD_LOGIC;
|
702 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_27_UNCONNECTED : STD_LOGIC;
|
703 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_26_UNCONNECTED : STD_LOGIC;
|
704 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_25_UNCONNECTED : STD_LOGIC;
|
705 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_24_UNCONNECTED : STD_LOGIC;
|
706 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_23_UNCONNECTED : STD_LOGIC;
|
707 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_22_UNCONNECTED : STD_LOGIC;
|
708 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_21_UNCONNECTED : STD_LOGIC;
|
709 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_20_UNCONNECTED : STD_LOGIC;
|
710 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_19_UNCONNECTED : STD_LOGIC;
|
711 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_18_UNCONNECTED : STD_LOGIC;
|
712 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_17_UNCONNECTED : STD_LOGIC;
|
713 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_16_UNCONNECTED : STD_LOGIC;
|
714 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_15_UNCONNECTED : STD_LOGIC;
|
715 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_14_UNCONNECTED : STD_LOGIC;
|
716 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_13_UNCONNECTED : STD_LOGIC;
|
717 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_12_UNCONNECTED : STD_LOGIC;
|
718 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_11_UNCONNECTED : STD_LOGIC;
|
719 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_10_UNCONNECTED : STD_LOGIC;
|
720 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_9_UNCONNECTED : STD_LOGIC;
|
721 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_8_UNCONNECTED : STD_LOGIC;
|
722 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_7_UNCONNECTED : STD_LOGIC;
|
723 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_6_UNCONNECTED : STD_LOGIC;
|
724 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_5_UNCONNECTED : STD_LOGIC;
|
725 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_4_UNCONNECTED : STD_LOGIC;
|
726 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_3_UNCONNECTED : STD_LOGIC;
|
727 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_2_UNCONNECTED : STD_LOGIC;
|
728 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_1_UNCONNECTED : STD_LOGIC;
|
729 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_0_UNCONNECTED : STD_LOGIC;
|
730 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_3_UNCONNECTED : STD_LOGIC;
|
731 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_2_UNCONNECTED : STD_LOGIC;
|
732 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_1_UNCONNECTED : STD_LOGIC;
|
733 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_0_UNCONNECTED : STD_LOGIC;
|
734 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATA_UNCONNECTED : STD_LOGIC;
|
735 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATB_UNCONNECTED : STD_LOGIC;
|
736 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGA_UNCONNECTED : STD_LOGIC;
|
737 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGB_UNCONNECTED : STD_LOGIC;
|
738 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_7_UNCONNECTED : STD_LOGIC;
|
739 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_6_UNCONNECTED : STD_LOGIC;
|
740 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_5_UNCONNECTED : STD_LOGIC;
|
741 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_4_UNCONNECTED : STD_LOGIC;
|
742 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_7_UNCONNECTED : STD_LOGIC;
|
743 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_6_UNCONNECTED : STD_LOGIC;
|
744 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_5_UNCONNECTED : STD_LOGIC;
|
745 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_4_UNCONNECTED : STD_LOGIC;
|
746 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_31_UNCONNECTED : STD_LOGIC;
|
747 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_30_UNCONNECTED : STD_LOGIC;
|
748 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_29_UNCONNECTED : STD_LOGIC;
|
749 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_28_UNCONNECTED : STD_LOGIC;
|
750 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_27_UNCONNECTED : STD_LOGIC;
|
751 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_26_UNCONNECTED : STD_LOGIC;
|
752 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_25_UNCONNECTED : STD_LOGIC;
|
753 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_24_UNCONNECTED : STD_LOGIC;
|
754 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_23_UNCONNECTED : STD_LOGIC;
|
755 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_22_UNCONNECTED : STD_LOGIC;
|
756 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_21_UNCONNECTED : STD_LOGIC;
|
757 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_20_UNCONNECTED : STD_LOGIC;
|
758 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_19_UNCONNECTED : STD_LOGIC;
|
759 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_18_UNCONNECTED : STD_LOGIC;
|
760 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_17_UNCONNECTED : STD_LOGIC;
|
761 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_16_UNCONNECTED : STD_LOGIC;
|
762 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_15_UNCONNECTED : STD_LOGIC;
|
763 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_14_UNCONNECTED : STD_LOGIC;
|
764 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_13_UNCONNECTED : STD_LOGIC;
|
765 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_12_UNCONNECTED : STD_LOGIC;
|
766 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_11_UNCONNECTED : STD_LOGIC;
|
767 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_10_UNCONNECTED : STD_LOGIC;
|
768 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_9_UNCONNECTED : STD_LOGIC;
|
769 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_8_UNCONNECTED : STD_LOGIC;
|
770 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_3_UNCONNECTED : STD_LOGIC;
|
771 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_2_UNCONNECTED : STD_LOGIC;
|
772 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_1_UNCONNECTED : STD_LOGIC;
|
773 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_31_UNCONNECTED : STD_LOGIC;
|
774 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_30_UNCONNECTED : STD_LOGIC;
|
775 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_29_UNCONNECTED : STD_LOGIC;
|
776 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_28_UNCONNECTED : STD_LOGIC;
|
777 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_27_UNCONNECTED : STD_LOGIC;
|
778 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_26_UNCONNECTED : STD_LOGIC;
|
779 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_25_UNCONNECTED : STD_LOGIC;
|
780 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_24_UNCONNECTED : STD_LOGIC;
|
781 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_23_UNCONNECTED : STD_LOGIC;
|
782 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_22_UNCONNECTED : STD_LOGIC;
|
783 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_21_UNCONNECTED : STD_LOGIC;
|
784 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_20_UNCONNECTED : STD_LOGIC;
|
785 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_19_UNCONNECTED : STD_LOGIC;
|
786 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_18_UNCONNECTED : STD_LOGIC;
|
787 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_17_UNCONNECTED : STD_LOGIC;
|
788 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_16_UNCONNECTED : STD_LOGIC;
|
789 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_15_UNCONNECTED : STD_LOGIC;
|
790 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_14_UNCONNECTED : STD_LOGIC;
|
791 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_13_UNCONNECTED : STD_LOGIC;
|
792 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_12_UNCONNECTED : STD_LOGIC;
|
793 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_11_UNCONNECTED : STD_LOGIC;
|
794 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_10_UNCONNECTED : STD_LOGIC;
|
795 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_9_UNCONNECTED : STD_LOGIC;
|
796 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_8_UNCONNECTED : STD_LOGIC;
|
797 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_7_UNCONNECTED : STD_LOGIC;
|
798 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_6_UNCONNECTED : STD_LOGIC;
|
799 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_5_UNCONNECTED : STD_LOGIC;
|
800 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_4_UNCONNECTED : STD_LOGIC;
|
801 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_3_UNCONNECTED : STD_LOGIC;
|
802 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_2_UNCONNECTED : STD_LOGIC;
|
803 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_1_UNCONNECTED : STD_LOGIC;
|
804 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_0_UNCONNECTED : STD_LOGIC;
|
805 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_3_UNCONNECTED : STD_LOGIC;
|
806 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_2_UNCONNECTED : STD_LOGIC;
|
807 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_1_UNCONNECTED : STD_LOGIC;
|
808 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_0_UNCONNECTED : STD_LOGIC;
|
809 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATA_UNCONNECTED : STD_LOGIC;
|
810 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATB_UNCONNECTED : STD_LOGIC;
|
811 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGA_UNCONNECTED : STD_LOGIC;
|
812 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGB_UNCONNECTED : STD_LOGIC;
|
813 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_7_UNCONNECTED : STD_LOGIC;
|
814 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_6_UNCONNECTED : STD_LOGIC;
|
815 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_5_UNCONNECTED : STD_LOGIC;
|
816 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_4_UNCONNECTED : STD_LOGIC;
|
817 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_7_UNCONNECTED : STD_LOGIC;
|
818 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_6_UNCONNECTED : STD_LOGIC;
|
819 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_5_UNCONNECTED : STD_LOGIC;
|
820 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_4_UNCONNECTED : STD_LOGIC;
|
821 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_31_UNCONNECTED : STD_LOGIC;
|
822 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_30_UNCONNECTED : STD_LOGIC;
|
823 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_29_UNCONNECTED : STD_LOGIC;
|
824 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_28_UNCONNECTED : STD_LOGIC;
|
825 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_27_UNCONNECTED : STD_LOGIC;
|
826 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_26_UNCONNECTED : STD_LOGIC;
|
827 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_25_UNCONNECTED : STD_LOGIC;
|
828 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_24_UNCONNECTED : STD_LOGIC;
|
829 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_23_UNCONNECTED : STD_LOGIC;
|
830 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_22_UNCONNECTED : STD_LOGIC;
|
831 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_21_UNCONNECTED : STD_LOGIC;
|
832 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_20_UNCONNECTED : STD_LOGIC;
|
833 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_19_UNCONNECTED : STD_LOGIC;
|
834 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_18_UNCONNECTED : STD_LOGIC;
|
835 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_17_UNCONNECTED : STD_LOGIC;
|
836 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_16_UNCONNECTED : STD_LOGIC;
|
837 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_15_UNCONNECTED : STD_LOGIC;
|
838 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_14_UNCONNECTED : STD_LOGIC;
|
839 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_13_UNCONNECTED : STD_LOGIC;
|
840 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_12_UNCONNECTED : STD_LOGIC;
|
841 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_11_UNCONNECTED : STD_LOGIC;
|
842 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_10_UNCONNECTED : STD_LOGIC;
|
843 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_9_UNCONNECTED : STD_LOGIC;
|
844 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_8_UNCONNECTED : STD_LOGIC;
|
845 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_3_UNCONNECTED : STD_LOGIC;
|
846 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_2_UNCONNECTED : STD_LOGIC;
|
847 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_1_UNCONNECTED : STD_LOGIC;
|
848 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_31_UNCONNECTED : STD_LOGIC;
|
849 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_30_UNCONNECTED : STD_LOGIC;
|
850 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_29_UNCONNECTED : STD_LOGIC;
|
851 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_28_UNCONNECTED : STD_LOGIC;
|
852 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_27_UNCONNECTED : STD_LOGIC;
|
853 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_26_UNCONNECTED : STD_LOGIC;
|
854 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_25_UNCONNECTED : STD_LOGIC;
|
855 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_24_UNCONNECTED : STD_LOGIC;
|
856 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_23_UNCONNECTED : STD_LOGIC;
|
857 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_22_UNCONNECTED : STD_LOGIC;
|
858 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_21_UNCONNECTED : STD_LOGIC;
|
859 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_20_UNCONNECTED : STD_LOGIC;
|
860 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_19_UNCONNECTED : STD_LOGIC;
|
861 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_18_UNCONNECTED : STD_LOGIC;
|
862 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_17_UNCONNECTED : STD_LOGIC;
|
863 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_16_UNCONNECTED : STD_LOGIC;
|
864 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_15_UNCONNECTED : STD_LOGIC;
|
865 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_14_UNCONNECTED : STD_LOGIC;
|
866 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_13_UNCONNECTED : STD_LOGIC;
|
867 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_12_UNCONNECTED : STD_LOGIC;
|
868 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_11_UNCONNECTED : STD_LOGIC;
|
869 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_10_UNCONNECTED : STD_LOGIC;
|
870 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_9_UNCONNECTED : STD_LOGIC;
|
871 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_8_UNCONNECTED : STD_LOGIC;
|
872 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_7_UNCONNECTED : STD_LOGIC;
|
873 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_6_UNCONNECTED : STD_LOGIC;
|
874 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_5_UNCONNECTED : STD_LOGIC;
|
875 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_4_UNCONNECTED : STD_LOGIC;
|
876 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_3_UNCONNECTED : STD_LOGIC;
|
877 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_2_UNCONNECTED : STD_LOGIC;
|
878 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_1_UNCONNECTED : STD_LOGIC;
|
879 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_0_UNCONNECTED : STD_LOGIC;
|
880 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_3_UNCONNECTED : STD_LOGIC;
|
881 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_2_UNCONNECTED : STD_LOGIC;
|
882 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_1_UNCONNECTED : STD_LOGIC;
|
883 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_0_UNCONNECTED : STD_LOGIC;
|
884 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATA_UNCONNECTED : STD_LOGIC;
|
885 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATB_UNCONNECTED : STD_LOGIC;
|
886 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGA_UNCONNECTED : STD_LOGIC;
|
887 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGB_UNCONNECTED : STD_LOGIC;
|
888 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_7_UNCONNECTED : STD_LOGIC;
|
889 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_6_UNCONNECTED : STD_LOGIC;
|
890 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_5_UNCONNECTED : STD_LOGIC;
|
891 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_4_UNCONNECTED : STD_LOGIC;
|
892 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_7_UNCONNECTED : STD_LOGIC;
|
893 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_6_UNCONNECTED : STD_LOGIC;
|
894 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_5_UNCONNECTED : STD_LOGIC;
|
895 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_4_UNCONNECTED : STD_LOGIC;
|
896 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_31_UNCONNECTED : STD_LOGIC;
|
897 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_30_UNCONNECTED : STD_LOGIC;
|
898 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_29_UNCONNECTED : STD_LOGIC;
|
899 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_28_UNCONNECTED : STD_LOGIC;
|
900 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_27_UNCONNECTED : STD_LOGIC;
|
901 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_26_UNCONNECTED : STD_LOGIC;
|
902 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_25_UNCONNECTED : STD_LOGIC;
|
903 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_24_UNCONNECTED : STD_LOGIC;
|
904 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_23_UNCONNECTED : STD_LOGIC;
|
905 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_22_UNCONNECTED : STD_LOGIC;
|
906 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_21_UNCONNECTED : STD_LOGIC;
|
907 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_20_UNCONNECTED : STD_LOGIC;
|
908 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_19_UNCONNECTED : STD_LOGIC;
|
909 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_18_UNCONNECTED : STD_LOGIC;
|
910 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_17_UNCONNECTED : STD_LOGIC;
|
911 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_16_UNCONNECTED : STD_LOGIC;
|
912 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_15_UNCONNECTED : STD_LOGIC;
|
913 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_14_UNCONNECTED : STD_LOGIC;
|
914 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_13_UNCONNECTED : STD_LOGIC;
|
915 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_12_UNCONNECTED : STD_LOGIC;
|
916 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_11_UNCONNECTED : STD_LOGIC;
|
917 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_10_UNCONNECTED : STD_LOGIC;
|
918 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_9_UNCONNECTED : STD_LOGIC;
|
919 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_8_UNCONNECTED : STD_LOGIC;
|
920 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_3_UNCONNECTED : STD_LOGIC;
|
921 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_2_UNCONNECTED : STD_LOGIC;
|
922 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_1_UNCONNECTED : STD_LOGIC;
|
923 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_31_UNCONNECTED : STD_LOGIC;
|
924 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_30_UNCONNECTED : STD_LOGIC;
|
925 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_29_UNCONNECTED : STD_LOGIC;
|
926 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_28_UNCONNECTED : STD_LOGIC;
|
927 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_27_UNCONNECTED : STD_LOGIC;
|
928 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_26_UNCONNECTED : STD_LOGIC;
|
929 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_25_UNCONNECTED : STD_LOGIC;
|
930 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_24_UNCONNECTED : STD_LOGIC;
|
931 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_23_UNCONNECTED : STD_LOGIC;
|
932 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_22_UNCONNECTED : STD_LOGIC;
|
933 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_21_UNCONNECTED : STD_LOGIC;
|
934 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_20_UNCONNECTED : STD_LOGIC;
|
935 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_19_UNCONNECTED : STD_LOGIC;
|
936 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_18_UNCONNECTED : STD_LOGIC;
|
937 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_17_UNCONNECTED : STD_LOGIC;
|
938 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_16_UNCONNECTED : STD_LOGIC;
|
939 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_15_UNCONNECTED : STD_LOGIC;
|
940 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_14_UNCONNECTED : STD_LOGIC;
|
941 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_13_UNCONNECTED : STD_LOGIC;
|
942 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_12_UNCONNECTED : STD_LOGIC;
|
943 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_11_UNCONNECTED : STD_LOGIC;
|
944 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_10_UNCONNECTED : STD_LOGIC;
|
945 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_9_UNCONNECTED : STD_LOGIC;
|
946 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_8_UNCONNECTED : STD_LOGIC;
|
947 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_7_UNCONNECTED : STD_LOGIC;
|
948 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_6_UNCONNECTED : STD_LOGIC;
|
949 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_5_UNCONNECTED : STD_LOGIC;
|
950 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_4_UNCONNECTED : STD_LOGIC;
|
951 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_3_UNCONNECTED : STD_LOGIC;
|
952 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_2_UNCONNECTED : STD_LOGIC;
|
953 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_1_UNCONNECTED : STD_LOGIC;
|
954 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_0_UNCONNECTED : STD_LOGIC;
|
955 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_3_UNCONNECTED : STD_LOGIC;
|
956 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_2_UNCONNECTED : STD_LOGIC;
|
957 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_1_UNCONNECTED : STD_LOGIC;
|
958 |
|
|
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_0_UNCONNECTED : STD_LOGIC;
|
959 |
|
|
signal addra_2 : STD_LOGIC_VECTOR ( 13 downto 0 );
|
960 |
|
|
signal douta_3 : STD_LOGIC_VECTOR ( 26 downto 0 );
|
961 |
|
|
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta4 : STD_LOGIC_VECTOR ( 8 downto 0 );
|
962 |
|
|
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta3 : STD_LOGIC_VECTOR ( 8 downto 0 );
|
963 |
|
|
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta5 : STD_LOGIC_VECTOR ( 8 downto 0 );
|
964 |
|
|
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta6 : STD_LOGIC_VECTOR ( 8 downto 0 );
|
965 |
|
|
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta8 : STD_LOGIC_VECTOR ( 8 downto 0 );
|
966 |
|
|
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta7 : STD_LOGIC_VECTOR ( 8 downto 0 );
|
967 |
|
|
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta9 : STD_LOGIC_VECTOR ( 8 downto 0 );
|
968 |
|
|
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta10 : STD_LOGIC_VECTOR ( 8 downto 0 );
|
969 |
|
|
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta1 : STD_LOGIC_VECTOR ( 8 downto 0 );
|
970 |
|
|
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta : STD_LOGIC_VECTOR ( 8 downto 0 );
|
971 |
|
|
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta0 : STD_LOGIC_VECTOR ( 8 downto 0 );
|
972 |
|
|
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta2 : STD_LOGIC_VECTOR ( 8 downto 0 );
|
973 |
|
|
signal BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
|
974 |
|
|
signal BU2_doutb : STD_LOGIC_VECTOR ( 0 downto 0 );
|
975 |
|
|
begin
|
976 |
|
|
addra_2(13) <= addra(13);
|
977 |
|
|
addra_2(12) <= addra(12);
|
978 |
|
|
addra_2(11) <= addra(11);
|
979 |
|
|
addra_2(10) <= addra(10);
|
980 |
|
|
addra_2(9) <= addra(9);
|
981 |
|
|
addra_2(8) <= addra(8);
|
982 |
|
|
addra_2(7) <= addra(7);
|
983 |
|
|
addra_2(6) <= addra(6);
|
984 |
|
|
addra_2(5) <= addra(5);
|
985 |
|
|
addra_2(4) <= addra(4);
|
986 |
|
|
addra_2(3) <= addra(3);
|
987 |
|
|
addra_2(2) <= addra(2);
|
988 |
|
|
addra_2(1) <= addra(1);
|
989 |
|
|
addra_2(0) <= addra(0);
|
990 |
|
|
douta(26) <= douta_3(26);
|
991 |
|
|
douta(25) <= douta_3(25);
|
992 |
|
|
douta(24) <= douta_3(24);
|
993 |
|
|
douta(23) <= douta_3(23);
|
994 |
|
|
douta(22) <= douta_3(22);
|
995 |
|
|
douta(21) <= douta_3(21);
|
996 |
|
|
douta(20) <= douta_3(20);
|
997 |
|
|
douta(19) <= douta_3(19);
|
998 |
|
|
douta(18) <= douta_3(18);
|
999 |
|
|
douta(17) <= douta_3(17);
|
1000 |
|
|
douta(16) <= douta_3(16);
|
1001 |
|
|
douta(15) <= douta_3(15);
|
1002 |
|
|
douta(14) <= douta_3(14);
|
1003 |
|
|
douta(13) <= douta_3(13);
|
1004 |
|
|
douta(12) <= douta_3(12);
|
1005 |
|
|
douta(11) <= douta_3(11);
|
1006 |
|
|
douta(10) <= douta_3(10);
|
1007 |
|
|
douta(9) <= douta_3(9);
|
1008 |
|
|
douta(8) <= douta_3(8);
|
1009 |
|
|
douta(7) <= douta_3(7);
|
1010 |
|
|
douta(6) <= douta_3(6);
|
1011 |
|
|
douta(5) <= douta_3(5);
|
1012 |
|
|
douta(4) <= douta_3(4);
|
1013 |
|
|
douta(3) <= douta_3(3);
|
1014 |
|
|
douta(2) <= douta_3(2);
|
1015 |
|
|
douta(1) <= douta_3(1);
|
1016 |
|
|
douta(0) <= douta_3(0);
|
1017 |
|
|
VCC_0 : VCC
|
1018 |
|
|
port map (
|
1019 |
|
|
P => NLW_VCC_P_UNCONNECTED
|
1020 |
|
|
);
|
1021 |
|
|
GND_1 : GND
|
1022 |
|
|
port map (
|
1023 |
|
|
G => NLW_GND_G_UNCONNECTED
|
1024 |
|
|
);
|
1025 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP : RAMB36_EXP
|
1026 |
|
|
generic map(
|
1027 |
|
|
DOA_REG => 0,
|
1028 |
|
|
DOB_REG => 0,
|
1029 |
|
|
INIT_7E => X"6A98C5F3204E7BA8D4012E5A86B2DE0A35608CB6E10C37618BB5DF09325C85AE",
|
1030 |
|
|
INIT_7F => X"588BBEF0235588BAEC1D4F80B2E3144575A6D606366696C5F4245382B0DF0D3C",
|
1031 |
|
|
INITP_00 => X"E03C719993495AAAAA52DB36338F03FFF0E324AD6A498E0F1CCAA4C172B0E8CB",
|
1032 |
|
|
INITP_01 => X"03E0F1E39CE66664DB25B4A56AD555555AA56969249B3263318E38787E03FFFF",
|
1033 |
|
|
INITP_02 => X"6AD6B5AD2DA4924926C9B32666663319CE31C71E3C3C3E0F80FE007FFFFFFFFE",
|
1034 |
|
|
INITP_03 => X"C3C38F1C638C67319999999326C9B6DB6DA5A5A5295A956AAD5555555555AA95",
|
1035 |
|
|
INITP_04 => X"8E1C78F0F1E0F0F87C1F83F01FC07F801FFC0003FFFFFFFFFFFFFFC1C07E0783",
|
1036 |
|
|
INITP_05 => X"A5A4B6D2496DB24936D9364D9B3664CC9999999998CCE67319CE738C738E38E3",
|
1037 |
|
|
INITP_06 => X"2B54AB54AA9554AAAAD555555555552AAAA555AAB54AB54AD5AD4A5294A5A5A5",
|
1038 |
|
|
INITP_07 => X"667333333333333666CC9B364D936C926DB6DB6924B696D2D2D296B4A52B5A95",
|
1039 |
|
|
INITP_08 => X"0000003FFFF0001FFF000FFE00FF803C3C3C78F1E38F1C71CE39C639CE7319CC",
|
1040 |
|
|
INITP_09 => X"E07E03F80FF00FF007FC00FFC003FFE0003FFFF80000007FFFFFFFFFFFFFFFFC",
|
1041 |
|
|
INITP_0A => X"38E38E38E38E1C70E3C78F1E3C387878F0F078787C3E1F0783E0F83F07E07C0F",
|
1042 |
|
|
INITP_0B => X"664CCCCCCCCCCCCCE6666333199CCC673398C67318C6318C631CE31CE31C738E",
|
1043 |
|
|
INITP_0C => X"B6DA4925B6DB6DB6DB64926DB249B64DB26C9B26C99366CD9B3664CD99B33266",
|
1044 |
|
|
INITP_0D => X"4A952A54A95AB52B5295AD4A5294A5296B5A52D2969696969696D2DA5B496D24",
|
1045 |
|
|
SRVAL_A => X"000000000",
|
1046 |
|
|
SRVAL_B => X"000000000",
|
1047 |
|
|
INIT_00 => X"10EEAD4BCA286786846322C241A0DFFFFDBC3B7B7A3AB9F9F17170F0E0E0C000",
|
1048 |
|
|
INIT_01 => X"513D1AE6A24FEC79F663C00D4A7895A3A18F6D3BF9A745D452C11F6EADDBFA09",
|
1049 |
|
|
INIT_02 => X"0C00EBCFAB7F4B0FCC802CD16D028F14900572D8358AD71D5A90BDE30117252B",
|
1050 |
|
|
INIT_03 => X"4E3F2707E0B1793AF3A44EEF881AA4269F117CDE388BD5185385B0D3EF020D11",
|
1051 |
|
|
INIT_04 => X"87FD6FDD47AE106EC91F72C00B5295D30E4579A8D3FA1E3D597084949FA7AB56",
|
1052 |
|
|
INIT_05 => X"B6A999846B4F2F0AE2B686521ADF9F5B14C87926CF7415B24BE072FF890E900E",
|
1053 |
|
|
INIT_06 => X"43B31F87EC4CA90156A7F43D82C3013A70A1CFF91F415F7990A2B1BBC2C5C4BF",
|
1054 |
|
|
INIT_07 => X"3D2A12F7D7B48D623301CA90510FC97F31E08A30D3720DA437C651D85CDB57CF",
|
1055 |
|
|
INIT_08 => X"DA0E40719FCBF61E456A8CADCCE9041D34495D6E7D8B96A0A7ADB1B3B2B0594D",
|
1056 |
|
|
INIT_09 => X"5CCE3DAB1782EA50B41777D6328DE63D92E53685D21D67AEF43779B9F6326CA4",
|
1057 |
|
|
INIT_0A => X"2BDA8833DD842ACE6F0FAD49E47C12A739CA58E570F980058809880681FB72E8",
|
1058 |
|
|
INIT_0B => X"4F3C260FF6DBBE9F7E5B3610E7BD90623200CC965E24E9AB6C2AE7A25B12C77A",
|
1059 |
|
|
INIT_0C => X"D0FA21476B8DADCBE701193044576877848F989FA4A8A9A9A6A29C948A7E7061",
|
1060 |
|
|
INIT_0D => X"B51B80E243A1FE59B2095EB20353A0EC367EC4084A8AC9054078AFE4174877A5",
|
1061 |
|
|
INIT_0E => X"05A849E88521BA51E77B0C9C2AB641C94FD457D756D34EC83FB428990977E34D",
|
1062 |
|
|
INIT_0F => X"C9A885603A11E7BB8D5D2BF7C28A5115D8995816D18A42F7AB5D0DBB6712BA61",
|
1063 |
|
|
INIT_10 => X"83919DA9B4BEC6CED5DCE1E5E8EAECECECEAE8E5E0DBD5CE8C7A67513A2005E8",
|
1064 |
|
|
INIT_11 => X"E20E38628BB3D9FF24486B8EAFCFEE0D2A47637D97B0C8DFF50A1E3143556574",
|
1065 |
|
|
INIT_12 => X"86CF185FA6EB3074B7F83979B8F73470ABE61F5890C6FC316598CAFB2B5A89B6",
|
1066 |
|
|
INIT_13 => X"72D93FA4086BCE2F90EF4EAC0965C01A73CB2278CE2276C81A6BBB0A58A5F13C",
|
1067 |
|
|
INIT_14 => X"A92DB134B637B736B431AD29A31D950D84F96EE255C739A91887F461CC37A10A",
|
1068 |
|
|
INIT_15 => X"2FD17212B250EE8A26C05AF38B22B84DE27508992AB948D663EF7A048D159D23",
|
1069 |
|
|
INIT_16 => X"08C7864300BC7630E9A2590FC4792CDF9141F1A04EFBA853FDA74FF79D43E88C",
|
1070 |
|
|
INIT_17 => X"3613EFCAA47D552C02D8AC805224F5C594622FFCC7915B23EBB2783D01C48647",
|
1071 |
|
|
INIT_18 => X"BFB9B2AAA1978C817467584939281603EFDAC5AE977E654B3014F7D9BA9B7A59",
|
1072 |
|
|
INIT_19 => X"A4BBD1E6FA0E20314252606E7B87929CA6AEB6BCC2C6CACDCFD0D1D0CECCC8C4",
|
1073 |
|
|
INIT_1A => X"EA1E5183B4E41442709CC8F31C456E95BBE005284B6D8EAECDEB0824405A748C",
|
1074 |
|
|
INIT_1B => X"94E53583D11E6BB6004A92DA2166ABEF3375B6F73675B2EF2B66A0DA124980B6",
|
1075 |
|
|
INIT_1C => X"A6137FEB56BF2890F75EC3278BED4FB0106FCD2A86E23C96EF479DF4499DF043",
|
1076 |
|
|
INIT_1D => X"22AC35BD44CB50D558DB5DDE5EDE5CD956D24CC63FB82FA51A8F0375E758C837",
|
1077 |
|
|
INIT_1E => X"0CB258FDA143E58727C665029F3BD67009A138CF64F98D20B243D362F17E0B97",
|
1078 |
|
|
INIT_1F => X"682BEDAE6E2DECA96622DD975008BF762BE09447F9AA5A0AB86612BE6913BC65",
|
1079 |
|
|
INIT_20 => X"3818F6D3B08C664019F1C89F74491DEFC192633200CE9A6631FBC48C531ADFA4",
|
1080 |
|
|
INIT_21 => X"C1BEBCB8B5B1ACA7A29C968F88807870675E54493F34281C1003F5E8D9CBBC58",
|
1081 |
|
|
INIT_22 => X"232F3A454F59636C747D848C93999FA5AAAFB3B7BABDC0C2C3C5C5C6C6C5C4C3",
|
1082 |
|
|
INIT_23 => X"C4DEF8102941586F869CB2C7DCF105182C3E5163748595A6B5C4D3E2F0FD0A17",
|
1083 |
|
|
INIT_24 => X"A7CFF61D43698FB4D8FC20446689ABCCEE0E2F4E6E8DABC9E704213D597590AA",
|
1084 |
|
|
INIT_25 => X"CC02376CA0D4073A6D9FD002326393C2F1204E7CA9D6032F5A85B0DA042E567F",
|
1085 |
|
|
INIT_26 => X"3679BCFF4183C4054585C5044280BEFC3975B1ED28639DD7104982BAF2296096",
|
1086 |
|
|
INIT_27 => X"E53787D82877C61563B1FE4B97E32F7AC50F59A2EC347CC40B5299DE2469AEF2",
|
1087 |
|
|
INIT_28 => X"DC3B9AF856B3106CC8237ED9338DE63F98F0489FF64CA2F74CA1F5499CEF4294",
|
1088 |
|
|
INIT_29 => X"1C89F561CC37A20C76DF47B0187FE64DB3197EE348AC1073D5389AFB5CBD1D7D",
|
1089 |
|
|
INIT_2A => X"A7219B158E067EF66DE45BD146BB30A4188CFF71E455C738A81888F766D442AF",
|
1090 |
|
|
INIT_2B => X"7E068D149B21A72CB136BA3DC043C647C94ACB4BCB4AC948C643C13DBA36B12C",
|
1091 |
|
|
INIT_2C => X"A338CD62F68A1DB042D466F78818A838C755E371FF8C18A430BB46D05AE46DF6",
|
1092 |
|
|
INIT_2D => X"17BA5CFEA041E28222C261009E3CD97613AF4BE6811BB64FE88119B149E0770D",
|
1093 |
|
|
INIT_2E => X"DC8C3CEC9B49F8A65300AD5904B05B05AF5902AB53FBA34AF0973DE2872CD074",
|
1094 |
|
|
INIT_2F => X"F3B16E2BE8A4601BD6904A04BD762EE69D540BC1772CE1964AFEB16416C87A2B",
|
1095 |
|
|
INIT_30 => X"5F2AF5BF89521BE4AC743B02C98F541ADFA3672BEEB07335F6B77838F8B87735",
|
1096 |
|
|
INIT_31 => X"20F8D0A87F562C02D7AD815529FDD0A2744618E9B9895928F7C593612EFBC793",
|
1097 |
|
|
INIT_32 => X"381D03E8CCB094775A3C1EFFE0C1A18161401EFDDAB895714E2905E0BA946E47",
|
1098 |
|
|
INIT_33 => X"A89B8E807163534434231201F0DECBB8A5917D68543E2812FCE4CDB59D846B52",
|
1099 |
|
|
INIT_34 => X"73737372716F6D6A6864615D58534E48423C352D261D150C02F9EEE4D9CDC1B5",
|
1100 |
|
|
INIT_35 => X"99A6B3BFCBD7E2ECF7010A131C242C333A41474D52575C6064676A6C6F707272",
|
1101 |
|
|
INIT_36 => X"1C36506A829BB3CBE2F910263C51667B8FA2B6C9DBEDFF1021314151606F7D8B",
|
1102 |
|
|
INIT_37 => X"FE254C7298BEE3082C507497BADCFE20416282A2C1E1FF1E3C597693AFCBE601",
|
1103 |
|
|
INIT_38 => X"3F73A7DB0E4072A4D607376797C7F6245280ADDA07335F8AB5DF0A335C85AED6",
|
1104 |
|
|
INIT_39 => X"E22364A4E42463A2E01E5C99D6124E89C4FF3973ADE61E578FC6FD346AA0D50A",
|
1105 |
|
|
INIT_3A => X"E83684D11E6AB6024D98E22C76BF085199E0276EB5FB4085CA0F5396D91C5FA0",
|
1106 |
|
|
INIT_3B => X"52AD0862BB156DC61E76CD247AD1267CD02579CD2073C51769BA0B5CACFB4B9A",
|
1107 |
|
|
INIT_3C => X"228AF158BE248AF054B91D81E447A90C6DCF2F90F050AF0E6CCB2886E23F9BF7",
|
1108 |
|
|
INIT_3D => X"59CE42B5289B0E80F263D444B424930271DF4CBA2693FF6BD641AB167FE851BA",
|
1109 |
|
|
INIT_3E => X"F97AFB7BFB7BFA79F775F370EC69E561DC57D14BC53EB72FA71F960D83F96FE4",
|
1110 |
|
|
INIT_3F => X"02901EAB37C450DB66F17B058E17A028B038BF46CC52D75CE166EA6DF073F577",
|
1111 |
|
|
INIT_40 => X"7812AC46DF7810A840D86E059B31C65BF08417AB3ED062F48617A738C757E674",
|
1112 |
|
|
INIT_41 => X"5A01A74EF3993EE3872BCE7114B658FA9B3CDC7C1CBB5AF89634D16E0AA642DD",
|
1113 |
|
|
INIT_42 => X"AA5D11C37628D98B3BEC9C4CFBAA5806B4610EBB6712BE6913BE6711BA620AB2",
|
1114 |
|
|
INIT_43 => X"6A2AE9A96826E4A25F1CD995510CC7823CF6AF6821D99148FFB66C22D88D42F6",
|
1115 |
|
|
INIT_44 => X"CDB49A7F654B3015FADFC3A78B6F53371AFDE0C3A5886A4C2E0FE1A46627E8A9",
|
1116 |
|
|
INIT_45 => X"9F8B7864503B2712FDE8D3BDA8927C654F38210AF3DCC4AC947C644B321900E7",
|
1117 |
|
|
INIT_46 => X"AA9D8F82746657493A2B1C0DFDEEDECEBDAD9C8B7A695846342210FEEBD8C5B2",
|
1118 |
|
|
INIT_47 => X"F0E9E2DAD2CAC2BAB1A9A0978D847A70665C51473C31251A0E03F7EADED1C4B8",
|
1119 |
|
|
INIT_48 => X"72716F6E6C6A686664615E5B5855514E4A45413D38332E28231D18120B05FEF7",
|
1120 |
|
|
INIT_49 => X"2F34393D42464A4E5255595C5F626466696B6C6E707172737374747474747372",
|
1121 |
|
|
INIT_4A => X"28343E49545E68727C868F99A2AAB3BCC4CCD4DCE3EBF2F9FF060C13191E242A",
|
1122 |
|
|
INIT_4B => X"5F718292A3B4C4D4E4F4031222303F4E5C6A788694A1AEBCC8D5E2EEFA06121D",
|
1123 |
|
|
INIT_4C => X"D4EB021930475D73899FB4CADFF4091E32465A6E8295A9BCCFE1F406192A3C4E",
|
1124 |
|
|
INIT_4D => X"88A5C2DFFC1835516D89A4C0DBF6112B46607A94AEC8E1FA132C445D758DA5BD",
|
1125 |
|
|
INIT_4E => X"7A9DC1E406294B6D90B1D3F41637587899B9D9F91939587796B5D4F2102E4C6A",
|
1126 |
|
|
INIT_4F => X"ACD6FF285179A2CAF21A416990B7DE052B52789EC3E90E34597EA2C7EB0F3357",
|
1127 |
|
|
INIT_50 => X"1F4F7EADDC0A386795C2F01E4B78A5D1FE2A5682AEDA05305B86B1DB052F5983",
|
1128 |
|
|
INIT_51 => X"D3093E73A7DC104478ACE0134679ACDF114476A8D90B3C6D9ECF00306090C0F0",
|
1129 |
|
|
INIT_52 => X"C905407AB5EF2A649ED7114A83BCF52E669ED60E467DB5EC235A90C6FD33689E",
|
1130 |
|
|
INIT_53 => X"024384C4054585C5054584C4034280BFFD3B79B7F5326FACE926629FDB17528E",
|
1131 |
|
|
INIT_54 => X"7DC40B5198DE246AB0F53B80C50A4E93D71B5FA2E6296CAFF23577B9FB3D7FC0",
|
1132 |
|
|
INIT_55 => X"3C89D6226EBB06529EE93580CA1560AAF43E88D11B64ADF63E87CF175FA7EE36",
|
1133 |
|
|
INIT_56 => X"4092E53789DB2D7FD02172C31465B50555A5F44493E23180CE1D6BB90754A2EF",
|
1134 |
|
|
INIT_57 => X"88E03991E94198F0479EF54CA2F94FA5FB51A6FB50A5FA4FA3F74B9FF34699EC",
|
1135 |
|
|
INIT_58 => X"1674D2308EEC49A60461BD1A76D22E8AE6429DF853AE0862BD1771CA247DD62F",
|
1136 |
|
|
INIT_59 => X"EA4EB21679DD40A30669CB2E90F254B51778D93A9BFC5CBC1C7CDC3B9AF958B7",
|
1137 |
|
|
INIT_5A => X"056FD842AB157EE74FB82088F058C0278EF55CC32A90F65CC2278DF257BC2186",
|
1138 |
|
|
INIT_5B => X"67D746B625940371E04EBC2A980573E04DBA2693FF6BD743AF1A85F05BC6309B",
|
1139 |
|
|
INIT_5C => X"1187FC71E65BCF44B82CA01487FA6EE053C638AA1C8E0072E354C536A61787F7",
|
1140 |
|
|
INIT_5D => X"0480FB75F06BE55FD953CC46BF38B129A21A920A82FA71E85FD64DC33AB0269C",
|
1141 |
|
|
INIT_5E => X"41C242C343C343C343C242C140BE3DBB39B735B330AE2BA825A11E9A16920E89",
|
1142 |
|
|
INIT_5F => X"C74DD45AE066EC71F67C00850A8E12971B9E22A528AB2EB133B638BA3BBD3EC0",
|
1143 |
|
|
INIT_60 => X"9724B03CC753DE69F47F0A941EA832BC46CF58E16AF37C048C149C24AB32B940",
|
1144 |
|
|
INIT_61 => X"B345D768FA8B1CAC3DCE5EEE7E0E9D2DBC4BDA68F78514A22FBD4AD865F27E0B",
|
1145 |
|
|
INIT_62 => X"1AB249E0770EA53BD268FD9329BE53E87D12A63BCF63F78A1EB144D76AFC8F21",
|
1146 |
|
|
INIT_63 => X"CE6B08A541DE7A16B24EE98420BB55F08B25BF59F38C26BF58F18A22BB53EB83",
|
1147 |
|
|
INIT_64 => X"CE7113B658FA9C3DDF8021C26304A444E48424C46302A140DF7D1CBA58F69331",
|
1148 |
|
|
INIT_65 => X"1CC46C14BC640BB25900A74DF49A40E68B31D67B20C56A0EB256FA9E42E5882B",
|
1149 |
|
|
INIT_66 => X"B86513C06E1BC87521CE7A26D27E29D5802BD6802BD6802AD47D27D07922CB74",
|
1150 |
|
|
INIT_67 => X"A25508BB6E21D38638EA9C4DFFB06112C37324D48434E49343F2A150FEAD5B0A",
|
1151 |
|
|
INIT_68 => X"DB944D05BE762EE69E550CC37A31E89E550BC1762CE2974C01B56A1ED3873BEE",
|
1152 |
|
|
INIT_69 => X"6423E19F5D1AD8955210CC894602BE7A36F1AD6823DE99540EC8823CF6B06922",
|
1153 |
|
|
INIT_6A => X"3E02C5894C0FD295581ADC9F6123E4A66728E9AA6A2BEBAB6B2BEAAA6928E7A6",
|
1154 |
|
|
INIT_6B => X"6831FAC38C551DE6AE763D05CC945B22E9AF763C02C88E5319DEA3682CF1B67A",
|
1155 |
|
|
INIT_6C => X"E4B2814F1EECBA875522F0BD8A5623EFBC88541FEBB6814C17E2AC77410BD59E",
|
1156 |
|
|
INIT_6D => X"B185592D01D4A87B4E21F4C6986B3D0EE0B2835425F6C697673707D7A7764515",
|
1157 |
|
|
INIT_6E => X"D1AB845E3710E8C19A724A22FAD1A880572E04DBB2885E3409DFB48A5E3408DD",
|
1158 |
|
|
INIT_6F => X"442402E1C09E7C5A3816F3D0AE8A674420FDD9B5916C4823FED9B48F69431EF8",
|
1159 |
|
|
INIT_70 => X"0BF0D4B89C8063462A0DF0D2B5977A5C3E1F01E2C3A48566462707E7C7A68665",
|
1160 |
|
|
INIT_71 => X"2610FAE3CCB69E877058402810F8E0C7AE957C634A3016FCE2C8AE93785D4227",
|
1161 |
|
|
INIT_72 => X"9685746352402E1C0AF8E6D3C0AD9A8774604C382410FCE7D2BEA8937E68523C",
|
1162 |
|
|
INIT_73 => X"5B5044382C201307FAEDE0D3C5B8AA9C8E807163544536271708F8E8D8C8B8A7",
|
1163 |
|
|
INIT_74 => X"76706A635C554E473F38302820180F07FEF5ECE3D9D0C6BCB2A89D93887D7267",
|
1164 |
|
|
INIT_75 => X"E8E6E5E4E2E1DFDDDBD9D6D4D1CECBC7C4C0BDB8B4B0ACA7A29D98938E88827C",
|
1165 |
|
|
INIT_76 => X"B0B4B8BCC0C4C7CACDD0D3D6D8DBDDDFE1E2E4E5E6E7E8E9E9EAEAEAEAEAE9E8",
|
1166 |
|
|
INIT_77 => X"CFD9E2ECF5FD060F171F2830373F464D545C62696F767C82878D92989DA2A7AB",
|
1167 |
|
|
INIT_78 => X"47566473818F9DABB9C6D4E1EEFA0714202C3844505B67727D88929DA7B2BCC6",
|
1168 |
|
|
INIT_79 => X"172B3F53667A8DA0B3C5D8EAFD0F2032445566788999AABACADBEBFA0A1A2938",
|
1169 |
|
|
INIT_7A => X"4059728BA4BDD5ED051E354D647C93AAC0D7EE041A30465B71869CB0C5DAEE03",
|
1170 |
|
|
INIT_7B => X"C3E1001E3C597794B2CFEC0925425E7A96B2CEE905203B56708BA5C0DAF40D27",
|
1171 |
|
|
INIT_7C => X"A0C3E70A2D507396B8DAFD1E406283A5C6E70829496A8AAACAE90928486786A4",
|
1172 |
|
|
INIT_7D => X"D700285179A1C9F11940688FB6DC032A50769CC2E80D33587DA2C7EB1034587C",
|
1173 |
|
|
INITP_0E => X"A955555555555555555555555555AAAAAA55556AAAD556AA9552AB552A954AB5",
|
1174 |
|
|
INIT_FILE => "NONE",
|
1175 |
|
|
RAM_EXTENSION_A => "NONE",
|
1176 |
|
|
RAM_EXTENSION_B => "NONE",
|
1177 |
|
|
READ_WIDTH_A => 9,
|
1178 |
|
|
READ_WIDTH_B => 9,
|
1179 |
|
|
SIM_COLLISION_CHECK => "ALL",
|
1180 |
|
|
SIM_MODE => "SAFE",
|
1181 |
|
|
INIT_A => X"000000000",
|
1182 |
|
|
INIT_B => X"000000000",
|
1183 |
|
|
WRITE_MODE_A => "WRITE_FIRST",
|
1184 |
|
|
WRITE_MODE_B => "WRITE_FIRST",
|
1185 |
|
|
WRITE_WIDTH_A => 9,
|
1186 |
|
|
WRITE_WIDTH_B => 9,
|
1187 |
|
|
INITP_0F => X"A5294AD6A52B52B52A56AD5AB54A956A954AA556AA554AAB5552AAA55556AAAA"
|
1188 |
|
|
)
|
1189 |
|
|
port map (
|
1190 |
|
|
ENAU => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_0_cmp_eq0000,
|
1191 |
|
|
ENAL => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_0_cmp_eq0000,
|
1192 |
|
|
ENBU => BU2_doutb(0),
|
1193 |
|
|
ENBL => BU2_doutb(0),
|
1194 |
|
|
SSRAU => BU2_doutb(0),
|
1195 |
|
|
SSRAL => BU2_doutb(0),
|
1196 |
|
|
SSRBU => BU2_doutb(0),
|
1197 |
|
|
SSRBL => BU2_doutb(0),
|
1198 |
|
|
CLKAU => clka,
|
1199 |
|
|
CLKAL => clka,
|
1200 |
|
|
CLKBU => BU2_doutb(0),
|
1201 |
|
|
CLKBL => BU2_doutb(0),
|
1202 |
|
|
REGCLKAU => clka,
|
1203 |
|
|
REGCLKAL => clka,
|
1204 |
|
|
REGCLKBU => BU2_doutb(0),
|
1205 |
|
|
REGCLKBL => BU2_doutb(0),
|
1206 |
|
|
REGCEAU => BU2_doutb(0),
|
1207 |
|
|
REGCEAL => BU2_doutb(0),
|
1208 |
|
|
REGCEBU => BU2_doutb(0),
|
1209 |
|
|
REGCEBL => BU2_doutb(0),
|
1210 |
|
|
CASCADEINLATA => BU2_doutb(0),
|
1211 |
|
|
CASCADEINLATB => BU2_doutb(0),
|
1212 |
|
|
CASCADEINREGA => BU2_doutb(0),
|
1213 |
|
|
CASCADEINREGB => BU2_doutb(0),
|
1214 |
|
|
CASCADEOUTLATA => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATA_UNCONNECTED,
|
1215 |
|
|
CASCADEOUTLATB => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATB_UNCONNECTED,
|
1216 |
|
|
CASCADEOUTREGA => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGA_UNCONNECTED,
|
1217 |
|
|
CASCADEOUTREGB => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGB_UNCONNECTED,
|
1218 |
|
|
DIA(31) => BU2_doutb(0),
|
1219 |
|
|
DIA(30) => BU2_doutb(0),
|
1220 |
|
|
DIA(29) => BU2_doutb(0),
|
1221 |
|
|
DIA(28) => BU2_doutb(0),
|
1222 |
|
|
DIA(27) => BU2_doutb(0),
|
1223 |
|
|
DIA(26) => BU2_doutb(0),
|
1224 |
|
|
DIA(25) => BU2_doutb(0),
|
1225 |
|
|
DIA(24) => BU2_doutb(0),
|
1226 |
|
|
DIA(23) => BU2_doutb(0),
|
1227 |
|
|
DIA(22) => BU2_doutb(0),
|
1228 |
|
|
DIA(21) => BU2_doutb(0),
|
1229 |
|
|
DIA(20) => BU2_doutb(0),
|
1230 |
|
|
DIA(19) => BU2_doutb(0),
|
1231 |
|
|
DIA(18) => BU2_doutb(0),
|
1232 |
|
|
DIA(17) => BU2_doutb(0),
|
1233 |
|
|
DIA(16) => BU2_doutb(0),
|
1234 |
|
|
DIA(15) => BU2_doutb(0),
|
1235 |
|
|
DIA(14) => BU2_doutb(0),
|
1236 |
|
|
DIA(13) => BU2_doutb(0),
|
1237 |
|
|
DIA(12) => BU2_doutb(0),
|
1238 |
|
|
DIA(11) => BU2_doutb(0),
|
1239 |
|
|
DIA(10) => BU2_doutb(0),
|
1240 |
|
|
DIA(9) => BU2_doutb(0),
|
1241 |
|
|
DIA(8) => BU2_doutb(0),
|
1242 |
|
|
DIA(7) => BU2_doutb(0),
|
1243 |
|
|
DIA(6) => BU2_doutb(0),
|
1244 |
|
|
DIA(5) => BU2_doutb(0),
|
1245 |
|
|
DIA(4) => BU2_doutb(0),
|
1246 |
|
|
DIA(3) => BU2_doutb(0),
|
1247 |
|
|
DIA(2) => BU2_doutb(0),
|
1248 |
|
|
DIA(1) => BU2_doutb(0),
|
1249 |
|
|
DIA(0) => BU2_doutb(0),
|
1250 |
|
|
DIPA(3) => BU2_doutb(0),
|
1251 |
|
|
DIPA(2) => BU2_doutb(0),
|
1252 |
|
|
DIPA(1) => BU2_doutb(0),
|
1253 |
|
|
DIPA(0) => BU2_doutb(0),
|
1254 |
|
|
DIB(31) => BU2_doutb(0),
|
1255 |
|
|
DIB(30) => BU2_doutb(0),
|
1256 |
|
|
DIB(29) => BU2_doutb(0),
|
1257 |
|
|
DIB(28) => BU2_doutb(0),
|
1258 |
|
|
DIB(27) => BU2_doutb(0),
|
1259 |
|
|
DIB(26) => BU2_doutb(0),
|
1260 |
|
|
DIB(25) => BU2_doutb(0),
|
1261 |
|
|
DIB(24) => BU2_doutb(0),
|
1262 |
|
|
DIB(23) => BU2_doutb(0),
|
1263 |
|
|
DIB(22) => BU2_doutb(0),
|
1264 |
|
|
DIB(21) => BU2_doutb(0),
|
1265 |
|
|
DIB(20) => BU2_doutb(0),
|
1266 |
|
|
DIB(19) => BU2_doutb(0),
|
1267 |
|
|
DIB(18) => BU2_doutb(0),
|
1268 |
|
|
DIB(17) => BU2_doutb(0),
|
1269 |
|
|
DIB(16) => BU2_doutb(0),
|
1270 |
|
|
DIB(15) => BU2_doutb(0),
|
1271 |
|
|
DIB(14) => BU2_doutb(0),
|
1272 |
|
|
DIB(13) => BU2_doutb(0),
|
1273 |
|
|
DIB(12) => BU2_doutb(0),
|
1274 |
|
|
DIB(11) => BU2_doutb(0),
|
1275 |
|
|
DIB(10) => BU2_doutb(0),
|
1276 |
|
|
DIB(9) => BU2_doutb(0),
|
1277 |
|
|
DIB(8) => BU2_doutb(0),
|
1278 |
|
|
DIB(7) => BU2_doutb(0),
|
1279 |
|
|
DIB(6) => BU2_doutb(0),
|
1280 |
|
|
DIB(5) => BU2_doutb(0),
|
1281 |
|
|
DIB(4) => BU2_doutb(0),
|
1282 |
|
|
DIB(3) => BU2_doutb(0),
|
1283 |
|
|
DIB(2) => BU2_doutb(0),
|
1284 |
|
|
DIB(1) => BU2_doutb(0),
|
1285 |
|
|
DIB(0) => BU2_doutb(0),
|
1286 |
|
|
DIPB(3) => BU2_doutb(0),
|
1287 |
|
|
DIPB(2) => BU2_doutb(0),
|
1288 |
|
|
DIPB(1) => BU2_doutb(0),
|
1289 |
|
|
DIPB(0) => BU2_doutb(0),
|
1290 |
|
|
ADDRAL(15) => BU2_doutb(0),
|
1291 |
|
|
ADDRAL(14) => addra_2(11),
|
1292 |
|
|
ADDRAL(13) => addra_2(10),
|
1293 |
|
|
ADDRAL(12) => addra_2(9),
|
1294 |
|
|
ADDRAL(11) => addra_2(8),
|
1295 |
|
|
ADDRAL(10) => addra_2(7),
|
1296 |
|
|
ADDRAL(9) => addra_2(6),
|
1297 |
|
|
ADDRAL(8) => addra_2(5),
|
1298 |
|
|
ADDRAL(7) => addra_2(4),
|
1299 |
|
|
ADDRAL(6) => addra_2(3),
|
1300 |
|
|
ADDRAL(5) => addra_2(2),
|
1301 |
|
|
ADDRAL(4) => addra_2(1),
|
1302 |
|
|
ADDRAL(3) => addra_2(0),
|
1303 |
|
|
ADDRAL(2) => BU2_doutb(0),
|
1304 |
|
|
ADDRAL(1) => BU2_doutb(0),
|
1305 |
|
|
ADDRAL(0) => BU2_doutb(0),
|
1306 |
|
|
ADDRAU(14) => addra_2(11),
|
1307 |
|
|
ADDRAU(13) => addra_2(10),
|
1308 |
|
|
ADDRAU(12) => addra_2(9),
|
1309 |
|
|
ADDRAU(11) => addra_2(8),
|
1310 |
|
|
ADDRAU(10) => addra_2(7),
|
1311 |
|
|
ADDRAU(9) => addra_2(6),
|
1312 |
|
|
ADDRAU(8) => addra_2(5),
|
1313 |
|
|
ADDRAU(7) => addra_2(4),
|
1314 |
|
|
ADDRAU(6) => addra_2(3),
|
1315 |
|
|
ADDRAU(5) => addra_2(2),
|
1316 |
|
|
ADDRAU(4) => addra_2(1),
|
1317 |
|
|
ADDRAU(3) => addra_2(0),
|
1318 |
|
|
ADDRAU(2) => BU2_doutb(0),
|
1319 |
|
|
ADDRAU(1) => BU2_doutb(0),
|
1320 |
|
|
ADDRAU(0) => BU2_doutb(0),
|
1321 |
|
|
ADDRBL(15) => BU2_doutb(0),
|
1322 |
|
|
ADDRBL(14) => BU2_doutb(0),
|
1323 |
|
|
ADDRBL(13) => BU2_doutb(0),
|
1324 |
|
|
ADDRBL(12) => BU2_doutb(0),
|
1325 |
|
|
ADDRBL(11) => BU2_doutb(0),
|
1326 |
|
|
ADDRBL(10) => BU2_doutb(0),
|
1327 |
|
|
ADDRBL(9) => BU2_doutb(0),
|
1328 |
|
|
ADDRBL(8) => BU2_doutb(0),
|
1329 |
|
|
ADDRBL(7) => BU2_doutb(0),
|
1330 |
|
|
ADDRBL(6) => BU2_doutb(0),
|
1331 |
|
|
ADDRBL(5) => BU2_doutb(0),
|
1332 |
|
|
ADDRBL(4) => BU2_doutb(0),
|
1333 |
|
|
ADDRBL(3) => BU2_doutb(0),
|
1334 |
|
|
ADDRBL(2) => BU2_doutb(0),
|
1335 |
|
|
ADDRBL(1) => BU2_doutb(0),
|
1336 |
|
|
ADDRBL(0) => BU2_doutb(0),
|
1337 |
|
|
ADDRBU(14) => BU2_doutb(0),
|
1338 |
|
|
ADDRBU(13) => BU2_doutb(0),
|
1339 |
|
|
ADDRBU(12) => BU2_doutb(0),
|
1340 |
|
|
ADDRBU(11) => BU2_doutb(0),
|
1341 |
|
|
ADDRBU(10) => BU2_doutb(0),
|
1342 |
|
|
ADDRBU(9) => BU2_doutb(0),
|
1343 |
|
|
ADDRBU(8) => BU2_doutb(0),
|
1344 |
|
|
ADDRBU(7) => BU2_doutb(0),
|
1345 |
|
|
ADDRBU(6) => BU2_doutb(0),
|
1346 |
|
|
ADDRBU(5) => BU2_doutb(0),
|
1347 |
|
|
ADDRBU(4) => BU2_doutb(0),
|
1348 |
|
|
ADDRBU(3) => BU2_doutb(0),
|
1349 |
|
|
ADDRBU(2) => BU2_doutb(0),
|
1350 |
|
|
ADDRBU(1) => BU2_doutb(0),
|
1351 |
|
|
ADDRBU(0) => BU2_doutb(0),
|
1352 |
|
|
WEAU(3) => BU2_doutb(0),
|
1353 |
|
|
WEAU(2) => BU2_doutb(0),
|
1354 |
|
|
WEAU(1) => BU2_doutb(0),
|
1355 |
|
|
WEAU(0) => BU2_doutb(0),
|
1356 |
|
|
WEAL(3) => BU2_doutb(0),
|
1357 |
|
|
WEAL(2) => BU2_doutb(0),
|
1358 |
|
|
WEAL(1) => BU2_doutb(0),
|
1359 |
|
|
WEAL(0) => BU2_doutb(0),
|
1360 |
|
|
WEBU(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_7_UNCONNECTED,
|
1361 |
|
|
WEBU(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_6_UNCONNECTED,
|
1362 |
|
|
WEBU(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_5_UNCONNECTED,
|
1363 |
|
|
WEBU(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_4_UNCONNECTED,
|
1364 |
|
|
WEBU(3) => BU2_doutb(0),
|
1365 |
|
|
WEBU(2) => BU2_doutb(0),
|
1366 |
|
|
WEBU(1) => BU2_doutb(0),
|
1367 |
|
|
WEBU(0) => BU2_doutb(0),
|
1368 |
|
|
WEBL(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_7_UNCONNECTED,
|
1369 |
|
|
WEBL(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_6_UNCONNECTED,
|
1370 |
|
|
WEBL(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_5_UNCONNECTED,
|
1371 |
|
|
WEBL(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_4_UNCONNECTED,
|
1372 |
|
|
WEBL(3) => BU2_doutb(0),
|
1373 |
|
|
WEBL(2) => BU2_doutb(0),
|
1374 |
|
|
WEBL(1) => BU2_doutb(0),
|
1375 |
|
|
WEBL(0) => BU2_doutb(0),
|
1376 |
|
|
DOA(31) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_31_UNCONNECTED,
|
1377 |
|
|
DOA(30) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_30_UNCONNECTED,
|
1378 |
|
|
DOA(29) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_29_UNCONNECTED,
|
1379 |
|
|
DOA(28) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_28_UNCONNECTED,
|
1380 |
|
|
DOA(27) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_27_UNCONNECTED,
|
1381 |
|
|
DOA(26) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_26_UNCONNECTED,
|
1382 |
|
|
DOA(25) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_25_UNCONNECTED,
|
1383 |
|
|
DOA(24) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_24_UNCONNECTED,
|
1384 |
|
|
DOA(23) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_23_UNCONNECTED,
|
1385 |
|
|
DOA(22) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_22_UNCONNECTED,
|
1386 |
|
|
DOA(21) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_21_UNCONNECTED,
|
1387 |
|
|
DOA(20) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_20_UNCONNECTED,
|
1388 |
|
|
DOA(19) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_19_UNCONNECTED,
|
1389 |
|
|
DOA(18) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_18_UNCONNECTED,
|
1390 |
|
|
DOA(17) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_17_UNCONNECTED,
|
1391 |
|
|
DOA(16) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_16_UNCONNECTED,
|
1392 |
|
|
DOA(15) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_15_UNCONNECTED,
|
1393 |
|
|
DOA(14) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_14_UNCONNECTED,
|
1394 |
|
|
DOA(13) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_13_UNCONNECTED,
|
1395 |
|
|
DOA(12) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_12_UNCONNECTED,
|
1396 |
|
|
DOA(11) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_11_UNCONNECTED,
|
1397 |
|
|
DOA(10) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_10_UNCONNECTED,
|
1398 |
|
|
DOA(9) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_9_UNCONNECTED,
|
1399 |
|
|
DOA(8) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_8_UNCONNECTED,
|
1400 |
|
|
DOA(7) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta(7),
|
1401 |
|
|
DOA(6) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta(6),
|
1402 |
|
|
DOA(5) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta(5),
|
1403 |
|
|
DOA(4) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta(4),
|
1404 |
|
|
DOA(3) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta(3),
|
1405 |
|
|
DOA(2) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta(2),
|
1406 |
|
|
DOA(1) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta(1),
|
1407 |
|
|
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta(0),
|
1408 |
|
|
DOPA(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_3_UNCONNECTED,
|
1409 |
|
|
DOPA(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_2_UNCONNECTED,
|
1410 |
|
|
DOPA(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_1_UNCONNECTED,
|
1411 |
|
|
DOPA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta(8),
|
1412 |
|
|
DOB(31) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_31_UNCONNECTED,
|
1413 |
|
|
DOB(30) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_30_UNCONNECTED,
|
1414 |
|
|
DOB(29) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_29_UNCONNECTED,
|
1415 |
|
|
DOB(28) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_28_UNCONNECTED,
|
1416 |
|
|
DOB(27) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_27_UNCONNECTED,
|
1417 |
|
|
DOB(26) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_26_UNCONNECTED,
|
1418 |
|
|
DOB(25) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_25_UNCONNECTED,
|
1419 |
|
|
DOB(24) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_24_UNCONNECTED,
|
1420 |
|
|
DOB(23) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_23_UNCONNECTED,
|
1421 |
|
|
DOB(22) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_22_UNCONNECTED,
|
1422 |
|
|
DOB(21) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_21_UNCONNECTED,
|
1423 |
|
|
DOB(20) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_20_UNCONNECTED,
|
1424 |
|
|
DOB(19) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_19_UNCONNECTED,
|
1425 |
|
|
DOB(18) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_18_UNCONNECTED,
|
1426 |
|
|
DOB(17) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_17_UNCONNECTED,
|
1427 |
|
|
DOB(16) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_16_UNCONNECTED,
|
1428 |
|
|
DOB(15) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_15_UNCONNECTED,
|
1429 |
|
|
DOB(14) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_14_UNCONNECTED,
|
1430 |
|
|
DOB(13) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_13_UNCONNECTED,
|
1431 |
|
|
DOB(12) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_12_UNCONNECTED,
|
1432 |
|
|
DOB(11) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_11_UNCONNECTED,
|
1433 |
|
|
DOB(10) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_10_UNCONNECTED,
|
1434 |
|
|
DOB(9) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_9_UNCONNECTED,
|
1435 |
|
|
DOB(8) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_8_UNCONNECTED,
|
1436 |
|
|
DOB(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_7_UNCONNECTED,
|
1437 |
|
|
DOB(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_6_UNCONNECTED,
|
1438 |
|
|
DOB(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_5_UNCONNECTED,
|
1439 |
|
|
DOB(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_4_UNCONNECTED,
|
1440 |
|
|
DOB(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_3_UNCONNECTED,
|
1441 |
|
|
DOB(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_2_UNCONNECTED,
|
1442 |
|
|
DOB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_1_UNCONNECTED,
|
1443 |
|
|
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_0_UNCONNECTED,
|
1444 |
|
|
DOPB(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_3_UNCONNECTED,
|
1445 |
|
|
DOPB(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_2_UNCONNECTED,
|
1446 |
|
|
DOPB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_1_UNCONNECTED,
|
1447 |
|
|
DOPB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_0_UNCONNECTED
|
1448 |
|
|
);
|
1449 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP : RAMB36_EXP
|
1450 |
|
|
generic map(
|
1451 |
|
|
DOA_REG => 0,
|
1452 |
|
|
DOB_REG => 0,
|
1453 |
|
|
INIT_7E => X"AD56FEA750F8A149F29A42EB933BE38B33DB832BD37A22CA7119C0670FB65D04",
|
1454 |
|
|
INIT_7F => X"751FCA741FC9741EC8721CC6701AC46E18C26B15BE6811BB640DB66009B25B04",
|
1455 |
|
|
INITP_00 => X"D924926DB6DB6D24924B6DA496D24B696D2DA5A4B4B4B4B4B5A5AD296B4A5294",
|
1456 |
|
|
INITP_01 => X"33333333332666666CCCD99933664CD993264C9B364D9364D93649B24DB249B6",
|
1457 |
|
|
INITP_02 => X"7E07C0FC1F83F07E0F81F07C1F07C1F07C3E0F87C1E0F0783C1E18CCCE666667",
|
1458 |
|
|
INITP_03 => X"FF801FF801FF007FC01FE01FF00FF01FE03FC07F01FC07F03F81FC0FE07E07E0",
|
1459 |
|
|
INITP_04 => X"E000000007FFFFFF000003FFFFC0000FFFF8000FFFE000FFF8003FFC007FF001",
|
1460 |
|
|
INITP_05 => X"000007FFFFFF000000003FFFFFFFFFFFFFFFF800000000007FFFFFFFFFFFFFFF",
|
1461 |
|
|
INITP_06 => X"F803FE007FC00FFC00FFE003FF8007FF8003FFE0007FFE0001FFFF00003FFFFC",
|
1462 |
|
|
INITP_07 => X"E07E0FC0F81F81F81F81FC0FC07E03F81FC07F01FC07F80FF00FE01FE00FF007",
|
1463 |
|
|
INITP_08 => X"3C3E1E1E1F0F0F8783C3E1F0F87C3E1F0783E0F07C1F07C1F07C1F83E0FC1F83",
|
1464 |
|
|
INITP_09 => X"E1C70E3871E3871E3C70E1C3870E1C3878F1E1C3C7878F0F1E1E1E1C3C3C3C3C",
|
1465 |
|
|
INITP_0A => X"C639C738C718E39C718E39C71C638E38E39C71C71C71C71C78E38E38F1C71E38",
|
1466 |
|
|
INITP_0B => X"99CC67319CC63398C67398C6739CE6318C6318C6318C739CE318C738C639C639",
|
1467 |
|
|
INITP_0C => X"E6666666666733333319999CCCCE6667333999CCC66733199CCE673399CC6633",
|
1468 |
|
|
INITP_0D => X"6CC99B33666CCC999B3326664CCCC99999333333266666666666CCCCCCCCCCCC",
|
1469 |
|
|
SRVAL_A => X"000000000",
|
1470 |
|
|
SRVAL_B => X"000000000",
|
1471 |
|
|
INIT_00 => X"A2DA124A82B9F1285F96CC033A70A6DC12477CB2E71C5185BAEE22568ABEF125",
|
1472 |
|
|
INIT_01 => X"4986C3003D7AB6F22F6BA6E21E5994CF0A457FBAF42E68A2DB154E87C0F9316A",
|
1473 |
|
|
INIT_02 => X"4D90D2145697D91A5B9CDE1E5F9FE020609FDF1E5E9DDC1B5998D6145290CE0C",
|
1474 |
|
|
INIT_03 => X"AFF63E85CC1259A0E62C72B8FE4388CE12579CE02569ADF13578BCFF4285C80B",
|
1475 |
|
|
INIT_04 => X"6FBC0854A0EC3783CE1A64AFFA448FD9236DB7014A93DC266EB7004890D82068",
|
1476 |
|
|
INIT_05 => X"8EDF3082D32474C51565B60655A5F44493E2307FCE1C6AB80654A1EE3C89D622",
|
1477 |
|
|
INIT_06 => X"0C62B80F65BB1066BB1066BA0F64B80D61B5095CB00356A9FC4FA2F44698EA3C",
|
1478 |
|
|
INIT_07 => X"E945A0FB56B10C66C11B75CF2982DC358FE74099F24AA2FA52AA0259B0075EB5",
|
1479 |
|
|
INIT_08 => X"2788E848A80868C72786E544A20160BE1C7AD83693F04EAB0864C11E7AD6328E",
|
1480 |
|
|
INIT_09 => X"C52B90F55ABF2488ED51B5197CE044A70A6DD03295F85ABC1E7FE142A30566C6",
|
1481 |
|
|
INIT_0A => X"C5309A046ED841AB147DE64FB82089F159C12990F85FC62D94FB62C82E94FA60",
|
1482 |
|
|
INIT_0B => X"26950574E251C02E9D0B78E654C22F9C0976E350BC2894006CD843AE1A84F05A",
|
1483 |
|
|
INIT_0C => X"EA5ED246BA2DA11488FA6DE053C537AA1C8EFF70E253C435A61687F767D747B6",
|
1484 |
|
|
INIT_0D => X"1088027AF36CE45CD54CC43CB42BA21990077EF46AE056CC42B72CA2178C0075",
|
1485 |
|
|
INIT_0E => X"98169412900D8A0885027EFB77F470EC68E35EDA55D04BC640BB35AF29A31C96",
|
1486 |
|
|
INIT_0F => X"85088A0E90129416981A9C1D9E20A122A223A323A323A322A222A0209E1D9C1A",
|
1487 |
|
|
INIT_10 => X"D65EE56CF47B028910971DA32AB036BB41C64CD056DA5FE468EC70F478FB7F02",
|
1488 |
|
|
INIT_11 => X"450CD2985E24EAB0763C01C78C5217DCA2672CE26CF67F08921AA32CB53DC64E",
|
1489 |
|
|
INIT_12 => X"521BE4AC753E06CE965E27EFB67E460ED69D652CF3BB824910D79E642BF2B87F",
|
1490 |
|
|
INIT_13 => X"12DEA8743E09D49F6A34FEC9935E28F2BC86501AE3AD77400AD39C662FF8C18A",
|
1491 |
|
|
INIT_14 => X"855220EEBB885622F0BC8A5623F0BC895522EEBA86521EEAB6824E19E5B07C47",
|
1492 |
|
|
INIT_15 => X"AB7B4B1BEABA8A5929F8C797663504D3A2703F0EDCAB794816E4B2804E1CEAB8",
|
1493 |
|
|
INIT_16 => X"845729FBCDA0714315E7B98A5C2DFFD0A1724415E6B6875828F9CA9A6A3B0BDB",
|
1494 |
|
|
INIT_17 => X"12E6BB8F64380DE1B58A5E3206DAAD815428FCCFA276491CEFC295673A0DDFB2",
|
1495 |
|
|
INIT_18 => X"522A01D8AE855C3309E0B68D63390FE5BC91673D13E8BE93693E13E9BE93683D",
|
1496 |
|
|
INIT_19 => X"4821FAD4AD865F3811EAC39C744D26FED6AF875F370FE7BF976F461EF5CDA47B",
|
1497 |
|
|
INIT_1A => X"F1CDA884603B17F2CEA9845F3A15F0CBA6805B3610EAC49F79532D07E1BB946E",
|
1498 |
|
|
INIT_1B => X"4F2D0BE9C7A583613E1CFAD7B4926F4C2906E3C09D7A563310ECC8A5815D3915",
|
1499 |
|
|
INIT_1C => X"62422303E4C4A48464442404E4C3A38262412000DFBE9D7C5B3A18F7D5B49271",
|
1500 |
|
|
INIT_1D => X"2A0CEFD2B5977A5C3F2103E5C7A98B6D4F3112F4D5B7987A5B3C1DFEDFC0A081",
|
1501 |
|
|
INIT_1E => X"A78C71563B2005EACEB3987C6045290DF1D6B99D8165492C10F3D7BA9D806447",
|
1502 |
|
|
INIT_1F => X"D9C1A890775E452C14FAE2C8AF967C63493016FCE2C8AE947A60462C11F6DCC1",
|
1503 |
|
|
INIT_20 => X"C1AB957F68523C250EF8E1CAB39C856E563F2810F9E1CAB29A826A523A220AF2",
|
1504 |
|
|
INIT_21 => X"604C382410FCE8D3BFAA96826D58442F1A05F0DBC5B09B85705A452F1903EDD8",
|
1505 |
|
|
INIT_22 => X"B4A2917F6D5C4A38261401EFDDCAB8A593806E5B4835220FFCE8D5C2AE9B8773",
|
1506 |
|
|
INIT_23 => X"BEAFA090817262524333231303F3E3D3C2B2A29180705F4E3D2C1C0AF9E8D7C5",
|
1507 |
|
|
INIT_24 => X"807366594C3E31241609FBEEE0D2C4B6A89A8C7E706153443627180AFBECDDCE",
|
1508 |
|
|
INIT_25 => X"F8EDE2D8CDC2B7ACA0958A7F73685C5045392D211509FDF1E4D8CCBFB3A6998C",
|
1509 |
|
|
INIT_26 => X"271E160D05FCF3EBE2D9D0C7BEB4ABA2988F857C72685E544A40362C22170D02",
|
1510 |
|
|
INIT_27 => X"0D0700FAF4EEE7E1DAD4CDC6BFB8B1AAA39C948D867E766F675F5750483F372F",
|
1511 |
|
|
INIT_28 => X"AAA7A39F9B97928E8A85817C78736E6A65605B56504B46413B36302A241F1913",
|
1512 |
|
|
INIT_29 => X"00FEFDFBF9F7F5F3F1EFEDEBE8E6E3E1DEDCD9D6D3D0CDCAC6C3C0BDB9B6B2AE",
|
1513 |
|
|
INIT_2A => X"0D0E0E0F0F10101010101010101010100F0F0E0E0D0C0C0B0A09080705040301",
|
1514 |
|
|
INIT_2B => X"D2D5D8DBDDE0E3E5E8EAECEEF0F3F5F6F8FAFCFEFF01020405060708090A0B0C",
|
1515 |
|
|
INIT_2C => X"50555A5F64696E72777C8084898D92969A9EA2A6AAADB1B5B8BCBFC2C6C9CCCF",
|
1516 |
|
|
INIT_2D => X"868D949CA3AAB1B8BFC6CCD3DAE0E7EDF4FA00060C12181E242A2F353A40454A",
|
1517 |
|
|
INIT_2E => X"747E87919AA4ADB6BFC8D1DAE3ECF5FD060E171F2730384048505860676F767E",
|
1518 |
|
|
INIT_2F => X"1C28333F4B56626D78848F9AA5B0BBC6D1DCE6F1FB06101A252F39434D57616A",
|
1519 |
|
|
INIT_30 => X"7C8A98A6B4C2D0DDEBF80613212E3B4855626F7C8895A2AEBBC7D3E0ECF80410",
|
1520 |
|
|
INIT_31 => X"96A7B7C7D7E7F707162636465564748392A2B0C0CEDDECFB0A1827354452606E",
|
1521 |
|
|
INIT_32 => X"6A7C8FA1B3C6D8EAFC0E1F3143546678899AACBDCEDFF0011223344455657686",
|
1522 |
|
|
INIT_33 => X"F70C2035495E72869AAEC3D7EAFE1226394D6074879AAEC1D4E7FA0D1F324558",
|
1523 |
|
|
INIT_34 => X"3E556C8399B0C6DDF30920364C62788EA4B9CFE4FA10253A50657A8FA4B9CEE2",
|
1524 |
|
|
INIT_35 => X"4059728AA3BCD5ED061E374F678098B0C8E0F80F273F566E859DB4CBE2F91027",
|
1525 |
|
|
INIT_36 => X"FB16324D68829DB8D3EE08233D58728CA6C0DAF40E28425B758FA8C1DBF40D26",
|
1526 |
|
|
INIT_37 => X"718FACC9E604203D5A7794B1CDEA06233F5B7794B0CCE8041F3B57728EA9C5E0",
|
1527 |
|
|
INIT_38 => X"A2C2E101203F5E7E9CBCDAF91837557492B1CFEE0C2A486684A2C0DEFB193654",
|
1528 |
|
|
INIT_39 => X"8EB0D1F3143657789ABBDCFD1E3F5F80A1C1E20223436384A4C4E40423436383",
|
1529 |
|
|
INIT_3A => X"35597CA0C4E70B2E527598BBDE0224476A8DB0D2F5173A5C7EA0C3E507294A6C",
|
1530 |
|
|
INIT_3B => X"97BDE3092F547AA0C5EB10355A80A5CAEE14385D82A6CBF014385D81A5C9ED11",
|
1531 |
|
|
INIT_3C => X"B5DD052D557DA5CCF41C436A92B9E0082E567DA4CAF1183E658CB2D8FF254B71",
|
1532 |
|
|
INIT_3D => X"8EB9E30D37618BB5DE08325C85AED8012A537DA6CEF72049729AC3EB143C658D",
|
1533 |
|
|
INIT_3E => X"24507CA9D5012D5985B1DD0834608BB6E20D38638EBAE4103A6590BAE50F3A64",
|
1534 |
|
|
INIT_3F => X"75A4D2012F5D8BB9E71543719FCCFA285583B0DD0A386592BFEC1845729ECBF8",
|
1535 |
|
|
INIT_40 => X"83B4E4154575A6D606366696C6F6255585B4E4134272A1D0FF2E5D8CBBEA1847",
|
1536 |
|
|
INIT_41 => X"4D80B3E5184A7CAFE1134577AADB0D3F71A2D40537689ACBFC2D5E8FC0F12252",
|
1537 |
|
|
INIT_42 => X"D4093E72A7DC104479ADE1164A7EB2E6194D81B4E81B4F82B6E91C4F82B5E81B",
|
1538 |
|
|
INIT_43 => X"184F86BDF32A6097CE043A70A6DC13497FB4EA20568BC1F62C6196CB00366AA0",
|
1539 |
|
|
INIT_44 => X"19528BC4FC356EA6DF185088C0F93169A1D9114880B8F0275F96CD053C73AAE1",
|
1540 |
|
|
INIT_45 => X"D7124D88C3FE3873AEE8235D98D20C4680BAF42E68A2DC154F88C2FB346EA7E0",
|
1541 |
|
|
INIT_46 => X"5390CD0A4784C0FD3A77B3F02C68A5E11D5995D10D4985C1FC3873AFEA26619C",
|
1542 |
|
|
INIT_47 => X"8CCB0A4988C7064584C201407EBCFB3978B6F43270AEEC2A67A5E2205E9BD816",
|
1543 |
|
|
INIT_48 => X"83C4054688C80A4A8BCC0D4D8ECE0F4F90D0105090D0105090D00F4F8ECE0D4C",
|
1544 |
|
|
INIT_49 => X"387BBE024588CB0E5194D6195C9EE12366A8EA2C6EB0F23476B8FA3C7DBE0042",
|
1545 |
|
|
INIT_4A => X"ABF0367BC0054A8FD4195EA3E82C70B5FA3E82C60B4F93D71B5EA2E62A6DB1F4",
|
1546 |
|
|
INIT_4B => X"DC246BB2FA4188CF165DA4EB3278BF064C92D81F65ABF2387EC3094F95DA2066",
|
1547 |
|
|
INIT_4C => X"CC1660A9F23B84CE1760A8F23A83CC145DA5EE367EC60E569EE62E76BE064D95",
|
1548 |
|
|
INIT_4D => X"7BC7125EA9F4408BD6216CB6024C97E22C76C10C56A0EA347EC8125CA6F03983",
|
1549 |
|
|
INIT_4E => X"E93684D21F6CB90654A0EE3A88D4216EBA0753A0EC3884D11D69B5014C98E430",
|
1550 |
|
|
INIT_4F => X"1665B50454A3F24291E02F7ECC1C6AB90856A4F34290DE2C7AC81664B2004E9C",
|
1551 |
|
|
INIT_50 => X"0253A5F64899EA3C8DDE2F80D12272C31464B50656A6F64797E73787D72676C6",
|
1552 |
|
|
INIT_51 => X"AE0154A8FC4FA2F6489CEE4294E83A8DE03285D72A7CCE2073C51769BB0C5EB0",
|
1553 |
|
|
INIT_52 => X"186EC4196EC4196EC4196EC3186CC2166BC01468BD1166BA0E62B60A5EB2065A",
|
1554 |
|
|
INIT_53 => X"449BF24AA2F950A8FF56AD045BB2085FB60C63BA1066BD1369BF166CC2176DC3",
|
1555 |
|
|
INIT_54 => X"2E88E23B94EE47A0FA53AC055EB61068C11A72CA237BD42C84DC348CE43C94EC",
|
1556 |
|
|
INIT_55 => X"D93590EC48A3FE5AB5106BC6217CD6318CE6419CF650AB055FB9136DC7217BD5",
|
1557 |
|
|
INIT_56 => X"45A2005DBB1876D3308DEA47A4015EBA1774D02D89E6429EFA56B20E6AC6227E",
|
1558 |
|
|
INIT_57 => X"71D0308FEF4EAD0C6CCB2A89E846A60463C1207EDD3B99F856B41270CE2C89E7",
|
1559 |
|
|
INIT_58 => X"5DBF2082E344A60768C92A8BEC4DAE0E6FCF3090F151B11272D23292F252B111",
|
1560 |
|
|
INIT_59 => X"0B6ED23599FC5FC22588EC4EB11477D93C9E0163C6288AEC4FB11375D6389AFC",
|
1561 |
|
|
INIT_5A => X"79DF44AA0F74D93EA4086ED2379C0165CA2E93F75CC02488EC50B4187CE044A7",
|
1562 |
|
|
INIT_5B => X"A91078DF46AE157CE34AB1187FE54CB2197FE64CB2197FE54BB1177DE348AE14",
|
1563 |
|
|
INIT_5C => X"9A046DD63FA8127BE44CB61E87F058C12992FA62CB339B036BD33BA30B72DA42",
|
1564 |
|
|
INIT_5D => X"4DB8238FFA65D03BA6117CE651BC2691FB66D03AA40E79E34DB6208AF45EC731",
|
1565 |
|
|
INIT_5E => X"C12E9C0976E350BD2A960370DD49B6228FFB67D440AC1884F05CC7339F0A76E1",
|
1566 |
|
|
INIT_5F => X"F767D645B423920170DE4DBC2A990776E452C02F9D0A79E754C2309E0B79E654",
|
1567 |
|
|
INIT_60 => X"F061D243B425960677E859C93AAA1B8BFB6BDC4CBC2C9C0B7BEB5BCA3AA91988",
|
1568 |
|
|
INIT_61 => X"AA1D900376E95CCF41B426990B7EF062D447B92B9D0F80F264D647B92A9C0D7E",
|
1569 |
|
|
INIT_62 => X"279C1186FB70E459CE42B72B9F1488FC70E458CC40B4289C0F83F66ADD50C437",
|
1570 |
|
|
INIT_63 => X"66DD54CB42B82FA61C930980F66CE258CE44BA30A61C92077DF268DD52C83DB2",
|
1571 |
|
|
INIT_64 => X"68E15AD34CC43DB52EA61E970F87FF77EF67DF57CE46BE35AD249C138A0178EF",
|
1572 |
|
|
INIT_65 => X"2EA8239E18930D88027CF671EB65DF59D34DC640BA33AD26A019920B84FE77F0",
|
1573 |
|
|
INIT_66 => X"B632AF2CA824A11D9916920E8A0682FE79F571EC68E35FDA55D14CC742BD38B3",
|
1574 |
|
|
INIT_67 => X"0180FE7DFB79F876F472F06EEC6AE865E361DE5CD957D451CE4BC946C23FBC39",
|
1575 |
|
|
INIT_68 => X"1090119111921292129212921291119010900F8E0E8D0C8C0A8A098706850482",
|
1576 |
|
|
INIT_69 => X"E264E769EB6DEF71F375F779FA7CFE7F00820384068708890A8B0C8D0D8E0F8F",
|
1577 |
|
|
INIT_6A => X"78FC8004880C9114981CA023A72AAE31B438BB3EC144C74ACD50D356D85BDD60",
|
1578 |
|
|
INIT_6B => X"D258DE64EA70F67B01860C92179D22A72CB237BC41C64ACF54D95DE266EB70F4",
|
1579 |
|
|
INIT_6C => X"F07800870F971FA62EB53DC44CD35AE168EF76FD840B92189F26AC32B93FC64C",
|
1580 |
|
|
INIT_6D => X"D25CE56FF9820C951FA832BB44CD56DF68F17A038B149D25AE36BF47CF57E068",
|
1581 |
|
|
INIT_6E => X"78048F1BA632BD49D45FEA76018C17A12CB742CC57E26CF7810B9620AA34BE48",
|
1582 |
|
|
INIT_6F => X"E370FE8B19A634C14EDB68F5820F9C28B542CE5BE774008C18A431BD49D560EC",
|
1583 |
|
|
INIT_70 => X"12A231C050DF6EFD8C1BAA39C856E57402911FAD3CCA58E67402901EAC3AC855",
|
1584 |
|
|
INIT_71 => X"079829BA4CDD6EFE8F20B142D263F38414A435C555E575059525B545D464F483",
|
1585 |
|
|
INIT_72 => X"C053E6790C9F32C557EA7C0FA234C659EB7D0FA133C557E97B0C9E30C153E476",
|
1586 |
|
|
INIT_73 => X"3FD468FD9227BC50E5790EA236CA5EF3871BAF43D66AFE9225B94CE073069A2D",
|
1587 |
|
|
INIT_74 => X"8219B046DD740AA137CD64FA9026BC52E87E14A93FD56A00952AC055EA8014AA",
|
1588 |
|
|
INIT_75 => X"8C24BD55EE861EB64FE77F17AF47DF770EA63ED56D049C33CA62F99027BE55EC",
|
1589 |
|
|
INIT_76 => X"5AF58F2AC45EF8922CC660FA942EC761FA942DC660F9922CC55EF79029C25AF3",
|
1590 |
|
|
INIT_77 => X"EF8B27C460FC9733CF6B07A23EDA7511AC47E27E19B44FEA8520BB56F08B25C0",
|
1591 |
|
|
INIT_78 => X"49E78523C15FFD9A38D67311AE4CE98623C15EFB9835D16E0BA844E17E1AB653",
|
1592 |
|
|
INIT_79 => X"6A0AAA4AE98928C86707A645E48423C261009F3EDC7B1AB857F59432D16F0DAB",
|
1593 |
|
|
INIT_7A => X"51F29436D7781ABB5CFE9F40E18223C46405A647E78828C96909AA4AEA8A2ACA",
|
1594 |
|
|
INIT_7B => X"FEA145E88B2FD27518BB5E01A446E98C2ED17416B85BFD9F41E48527CA6B0DAF",
|
1595 |
|
|
INIT_7C => X"7117BC6106AB50F59A3EE3882DD1761ABF6307AC50F4983CE08428CC6F13B65A",
|
1596 |
|
|
INIT_7D => X"AC53FAA148EE953CE28930D67C23C96F16BC6208AE54FAA045EB9136DC8127CC",
|
1597 |
|
|
INITP_0E => X"B24D9364D9364D9364D9366C9B364D9B364C99366CD9B366CC993266CC993366",
|
1598 |
|
|
INIT_FILE => "NONE",
|
1599 |
|
|
RAM_EXTENSION_A => "NONE",
|
1600 |
|
|
RAM_EXTENSION_B => "NONE",
|
1601 |
|
|
READ_WIDTH_A => 9,
|
1602 |
|
|
READ_WIDTH_B => 9,
|
1603 |
|
|
SIM_COLLISION_CHECK => "ALL",
|
1604 |
|
|
SIM_MODE => "SAFE",
|
1605 |
|
|
INIT_A => X"000000000",
|
1606 |
|
|
INIT_B => X"000000000",
|
1607 |
|
|
WRITE_MODE_A => "WRITE_FIRST",
|
1608 |
|
|
WRITE_MODE_B => "WRITE_FIRST",
|
1609 |
|
|
WRITE_WIDTH_A => 9,
|
1610 |
|
|
WRITE_WIDTH_B => 9,
|
1611 |
|
|
INITP_0F => X"6DB6DB6D924924926DB6D924936DB249B6D926DB24DB649B649B64DB26D936C9"
|
1612 |
|
|
)
|
1613 |
|
|
port map (
|
1614 |
|
|
ENAU => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_1_cmp_eq0000,
|
1615 |
|
|
ENAL => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_1_cmp_eq0000,
|
1616 |
|
|
ENBU => BU2_doutb(0),
|
1617 |
|
|
ENBL => BU2_doutb(0),
|
1618 |
|
|
SSRAU => BU2_doutb(0),
|
1619 |
|
|
SSRAL => BU2_doutb(0),
|
1620 |
|
|
SSRBU => BU2_doutb(0),
|
1621 |
|
|
SSRBL => BU2_doutb(0),
|
1622 |
|
|
CLKAU => clka,
|
1623 |
|
|
CLKAL => clka,
|
1624 |
|
|
CLKBU => BU2_doutb(0),
|
1625 |
|
|
CLKBL => BU2_doutb(0),
|
1626 |
|
|
REGCLKAU => clka,
|
1627 |
|
|
REGCLKAL => clka,
|
1628 |
|
|
REGCLKBU => BU2_doutb(0),
|
1629 |
|
|
REGCLKBL => BU2_doutb(0),
|
1630 |
|
|
REGCEAU => BU2_doutb(0),
|
1631 |
|
|
REGCEAL => BU2_doutb(0),
|
1632 |
|
|
REGCEBU => BU2_doutb(0),
|
1633 |
|
|
REGCEBL => BU2_doutb(0),
|
1634 |
|
|
CASCADEINLATA => BU2_doutb(0),
|
1635 |
|
|
CASCADEINLATB => BU2_doutb(0),
|
1636 |
|
|
CASCADEINREGA => BU2_doutb(0),
|
1637 |
|
|
CASCADEINREGB => BU2_doutb(0),
|
1638 |
|
|
CASCADEOUTLATA => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATA_UNCONNECTED,
|
1639 |
|
|
CASCADEOUTLATB => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATB_UNCONNECTED,
|
1640 |
|
|
CASCADEOUTREGA => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGA_UNCONNECTED,
|
1641 |
|
|
CASCADEOUTREGB => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGB_UNCONNECTED,
|
1642 |
|
|
DIA(31) => BU2_doutb(0),
|
1643 |
|
|
DIA(30) => BU2_doutb(0),
|
1644 |
|
|
DIA(29) => BU2_doutb(0),
|
1645 |
|
|
DIA(28) => BU2_doutb(0),
|
1646 |
|
|
DIA(27) => BU2_doutb(0),
|
1647 |
|
|
DIA(26) => BU2_doutb(0),
|
1648 |
|
|
DIA(25) => BU2_doutb(0),
|
1649 |
|
|
DIA(24) => BU2_doutb(0),
|
1650 |
|
|
DIA(23) => BU2_doutb(0),
|
1651 |
|
|
DIA(22) => BU2_doutb(0),
|
1652 |
|
|
DIA(21) => BU2_doutb(0),
|
1653 |
|
|
DIA(20) => BU2_doutb(0),
|
1654 |
|
|
DIA(19) => BU2_doutb(0),
|
1655 |
|
|
DIA(18) => BU2_doutb(0),
|
1656 |
|
|
DIA(17) => BU2_doutb(0),
|
1657 |
|
|
DIA(16) => BU2_doutb(0),
|
1658 |
|
|
DIA(15) => BU2_doutb(0),
|
1659 |
|
|
DIA(14) => BU2_doutb(0),
|
1660 |
|
|
DIA(13) => BU2_doutb(0),
|
1661 |
|
|
DIA(12) => BU2_doutb(0),
|
1662 |
|
|
DIA(11) => BU2_doutb(0),
|
1663 |
|
|
DIA(10) => BU2_doutb(0),
|
1664 |
|
|
DIA(9) => BU2_doutb(0),
|
1665 |
|
|
DIA(8) => BU2_doutb(0),
|
1666 |
|
|
DIA(7) => BU2_doutb(0),
|
1667 |
|
|
DIA(6) => BU2_doutb(0),
|
1668 |
|
|
DIA(5) => BU2_doutb(0),
|
1669 |
|
|
DIA(4) => BU2_doutb(0),
|
1670 |
|
|
DIA(3) => BU2_doutb(0),
|
1671 |
|
|
DIA(2) => BU2_doutb(0),
|
1672 |
|
|
DIA(1) => BU2_doutb(0),
|
1673 |
|
|
DIA(0) => BU2_doutb(0),
|
1674 |
|
|
DIPA(3) => BU2_doutb(0),
|
1675 |
|
|
DIPA(2) => BU2_doutb(0),
|
1676 |
|
|
DIPA(1) => BU2_doutb(0),
|
1677 |
|
|
DIPA(0) => BU2_doutb(0),
|
1678 |
|
|
DIB(31) => BU2_doutb(0),
|
1679 |
|
|
DIB(30) => BU2_doutb(0),
|
1680 |
|
|
DIB(29) => BU2_doutb(0),
|
1681 |
|
|
DIB(28) => BU2_doutb(0),
|
1682 |
|
|
DIB(27) => BU2_doutb(0),
|
1683 |
|
|
DIB(26) => BU2_doutb(0),
|
1684 |
|
|
DIB(25) => BU2_doutb(0),
|
1685 |
|
|
DIB(24) => BU2_doutb(0),
|
1686 |
|
|
DIB(23) => BU2_doutb(0),
|
1687 |
|
|
DIB(22) => BU2_doutb(0),
|
1688 |
|
|
DIB(21) => BU2_doutb(0),
|
1689 |
|
|
DIB(20) => BU2_doutb(0),
|
1690 |
|
|
DIB(19) => BU2_doutb(0),
|
1691 |
|
|
DIB(18) => BU2_doutb(0),
|
1692 |
|
|
DIB(17) => BU2_doutb(0),
|
1693 |
|
|
DIB(16) => BU2_doutb(0),
|
1694 |
|
|
DIB(15) => BU2_doutb(0),
|
1695 |
|
|
DIB(14) => BU2_doutb(0),
|
1696 |
|
|
DIB(13) => BU2_doutb(0),
|
1697 |
|
|
DIB(12) => BU2_doutb(0),
|
1698 |
|
|
DIB(11) => BU2_doutb(0),
|
1699 |
|
|
DIB(10) => BU2_doutb(0),
|
1700 |
|
|
DIB(9) => BU2_doutb(0),
|
1701 |
|
|
DIB(8) => BU2_doutb(0),
|
1702 |
|
|
DIB(7) => BU2_doutb(0),
|
1703 |
|
|
DIB(6) => BU2_doutb(0),
|
1704 |
|
|
DIB(5) => BU2_doutb(0),
|
1705 |
|
|
DIB(4) => BU2_doutb(0),
|
1706 |
|
|
DIB(3) => BU2_doutb(0),
|
1707 |
|
|
DIB(2) => BU2_doutb(0),
|
1708 |
|
|
DIB(1) => BU2_doutb(0),
|
1709 |
|
|
DIB(0) => BU2_doutb(0),
|
1710 |
|
|
DIPB(3) => BU2_doutb(0),
|
1711 |
|
|
DIPB(2) => BU2_doutb(0),
|
1712 |
|
|
DIPB(1) => BU2_doutb(0),
|
1713 |
|
|
DIPB(0) => BU2_doutb(0),
|
1714 |
|
|
ADDRAL(15) => BU2_doutb(0),
|
1715 |
|
|
ADDRAL(14) => addra_2(11),
|
1716 |
|
|
ADDRAL(13) => addra_2(10),
|
1717 |
|
|
ADDRAL(12) => addra_2(9),
|
1718 |
|
|
ADDRAL(11) => addra_2(8),
|
1719 |
|
|
ADDRAL(10) => addra_2(7),
|
1720 |
|
|
ADDRAL(9) => addra_2(6),
|
1721 |
|
|
ADDRAL(8) => addra_2(5),
|
1722 |
|
|
ADDRAL(7) => addra_2(4),
|
1723 |
|
|
ADDRAL(6) => addra_2(3),
|
1724 |
|
|
ADDRAL(5) => addra_2(2),
|
1725 |
|
|
ADDRAL(4) => addra_2(1),
|
1726 |
|
|
ADDRAL(3) => addra_2(0),
|
1727 |
|
|
ADDRAL(2) => BU2_doutb(0),
|
1728 |
|
|
ADDRAL(1) => BU2_doutb(0),
|
1729 |
|
|
ADDRAL(0) => BU2_doutb(0),
|
1730 |
|
|
ADDRAU(14) => addra_2(11),
|
1731 |
|
|
ADDRAU(13) => addra_2(10),
|
1732 |
|
|
ADDRAU(12) => addra_2(9),
|
1733 |
|
|
ADDRAU(11) => addra_2(8),
|
1734 |
|
|
ADDRAU(10) => addra_2(7),
|
1735 |
|
|
ADDRAU(9) => addra_2(6),
|
1736 |
|
|
ADDRAU(8) => addra_2(5),
|
1737 |
|
|
ADDRAU(7) => addra_2(4),
|
1738 |
|
|
ADDRAU(6) => addra_2(3),
|
1739 |
|
|
ADDRAU(5) => addra_2(2),
|
1740 |
|
|
ADDRAU(4) => addra_2(1),
|
1741 |
|
|
ADDRAU(3) => addra_2(0),
|
1742 |
|
|
ADDRAU(2) => BU2_doutb(0),
|
1743 |
|
|
ADDRAU(1) => BU2_doutb(0),
|
1744 |
|
|
ADDRAU(0) => BU2_doutb(0),
|
1745 |
|
|
ADDRBL(15) => BU2_doutb(0),
|
1746 |
|
|
ADDRBL(14) => BU2_doutb(0),
|
1747 |
|
|
ADDRBL(13) => BU2_doutb(0),
|
1748 |
|
|
ADDRBL(12) => BU2_doutb(0),
|
1749 |
|
|
ADDRBL(11) => BU2_doutb(0),
|
1750 |
|
|
ADDRBL(10) => BU2_doutb(0),
|
1751 |
|
|
ADDRBL(9) => BU2_doutb(0),
|
1752 |
|
|
ADDRBL(8) => BU2_doutb(0),
|
1753 |
|
|
ADDRBL(7) => BU2_doutb(0),
|
1754 |
|
|
ADDRBL(6) => BU2_doutb(0),
|
1755 |
|
|
ADDRBL(5) => BU2_doutb(0),
|
1756 |
|
|
ADDRBL(4) => BU2_doutb(0),
|
1757 |
|
|
ADDRBL(3) => BU2_doutb(0),
|
1758 |
|
|
ADDRBL(2) => BU2_doutb(0),
|
1759 |
|
|
ADDRBL(1) => BU2_doutb(0),
|
1760 |
|
|
ADDRBL(0) => BU2_doutb(0),
|
1761 |
|
|
ADDRBU(14) => BU2_doutb(0),
|
1762 |
|
|
ADDRBU(13) => BU2_doutb(0),
|
1763 |
|
|
ADDRBU(12) => BU2_doutb(0),
|
1764 |
|
|
ADDRBU(11) => BU2_doutb(0),
|
1765 |
|
|
ADDRBU(10) => BU2_doutb(0),
|
1766 |
|
|
ADDRBU(9) => BU2_doutb(0),
|
1767 |
|
|
ADDRBU(8) => BU2_doutb(0),
|
1768 |
|
|
ADDRBU(7) => BU2_doutb(0),
|
1769 |
|
|
ADDRBU(6) => BU2_doutb(0),
|
1770 |
|
|
ADDRBU(5) => BU2_doutb(0),
|
1771 |
|
|
ADDRBU(4) => BU2_doutb(0),
|
1772 |
|
|
ADDRBU(3) => BU2_doutb(0),
|
1773 |
|
|
ADDRBU(2) => BU2_doutb(0),
|
1774 |
|
|
ADDRBU(1) => BU2_doutb(0),
|
1775 |
|
|
ADDRBU(0) => BU2_doutb(0),
|
1776 |
|
|
WEAU(3) => BU2_doutb(0),
|
1777 |
|
|
WEAU(2) => BU2_doutb(0),
|
1778 |
|
|
WEAU(1) => BU2_doutb(0),
|
1779 |
|
|
WEAU(0) => BU2_doutb(0),
|
1780 |
|
|
WEAL(3) => BU2_doutb(0),
|
1781 |
|
|
WEAL(2) => BU2_doutb(0),
|
1782 |
|
|
WEAL(1) => BU2_doutb(0),
|
1783 |
|
|
WEAL(0) => BU2_doutb(0),
|
1784 |
|
|
WEBU(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_7_UNCONNECTED,
|
1785 |
|
|
WEBU(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_6_UNCONNECTED,
|
1786 |
|
|
WEBU(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_5_UNCONNECTED,
|
1787 |
|
|
WEBU(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_4_UNCONNECTED,
|
1788 |
|
|
WEBU(3) => BU2_doutb(0),
|
1789 |
|
|
WEBU(2) => BU2_doutb(0),
|
1790 |
|
|
WEBU(1) => BU2_doutb(0),
|
1791 |
|
|
WEBU(0) => BU2_doutb(0),
|
1792 |
|
|
WEBL(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_7_UNCONNECTED,
|
1793 |
|
|
WEBL(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_6_UNCONNECTED,
|
1794 |
|
|
WEBL(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_5_UNCONNECTED,
|
1795 |
|
|
WEBL(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_4_UNCONNECTED,
|
1796 |
|
|
WEBL(3) => BU2_doutb(0),
|
1797 |
|
|
WEBL(2) => BU2_doutb(0),
|
1798 |
|
|
WEBL(1) => BU2_doutb(0),
|
1799 |
|
|
WEBL(0) => BU2_doutb(0),
|
1800 |
|
|
DOA(31) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_31_UNCONNECTED,
|
1801 |
|
|
DOA(30) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_30_UNCONNECTED,
|
1802 |
|
|
DOA(29) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_29_UNCONNECTED,
|
1803 |
|
|
DOA(28) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_28_UNCONNECTED,
|
1804 |
|
|
DOA(27) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_27_UNCONNECTED,
|
1805 |
|
|
DOA(26) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_26_UNCONNECTED,
|
1806 |
|
|
DOA(25) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_25_UNCONNECTED,
|
1807 |
|
|
DOA(24) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_24_UNCONNECTED,
|
1808 |
|
|
DOA(23) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_23_UNCONNECTED,
|
1809 |
|
|
DOA(22) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_22_UNCONNECTED,
|
1810 |
|
|
DOA(21) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_21_UNCONNECTED,
|
1811 |
|
|
DOA(20) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_20_UNCONNECTED,
|
1812 |
|
|
DOA(19) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_19_UNCONNECTED,
|
1813 |
|
|
DOA(18) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_18_UNCONNECTED,
|
1814 |
|
|
DOA(17) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_17_UNCONNECTED,
|
1815 |
|
|
DOA(16) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_16_UNCONNECTED,
|
1816 |
|
|
DOA(15) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_15_UNCONNECTED,
|
1817 |
|
|
DOA(14) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_14_UNCONNECTED,
|
1818 |
|
|
DOA(13) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_13_UNCONNECTED,
|
1819 |
|
|
DOA(12) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_12_UNCONNECTED,
|
1820 |
|
|
DOA(11) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_11_UNCONNECTED,
|
1821 |
|
|
DOA(10) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_10_UNCONNECTED,
|
1822 |
|
|
DOA(9) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_9_UNCONNECTED,
|
1823 |
|
|
DOA(8) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_8_UNCONNECTED,
|
1824 |
|
|
DOA(7) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta0(7),
|
1825 |
|
|
DOA(6) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta0(6),
|
1826 |
|
|
DOA(5) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta0(5),
|
1827 |
|
|
DOA(4) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta0(4),
|
1828 |
|
|
DOA(3) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta0(3),
|
1829 |
|
|
DOA(2) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta0(2),
|
1830 |
|
|
DOA(1) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta0(1),
|
1831 |
|
|
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta0(0),
|
1832 |
|
|
DOPA(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_3_UNCONNECTED,
|
1833 |
|
|
DOPA(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_2_UNCONNECTED,
|
1834 |
|
|
DOPA(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_1_UNCONNECTED,
|
1835 |
|
|
DOPA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta0(8),
|
1836 |
|
|
DOB(31) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_31_UNCONNECTED,
|
1837 |
|
|
DOB(30) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_30_UNCONNECTED,
|
1838 |
|
|
DOB(29) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_29_UNCONNECTED,
|
1839 |
|
|
DOB(28) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_28_UNCONNECTED,
|
1840 |
|
|
DOB(27) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_27_UNCONNECTED,
|
1841 |
|
|
DOB(26) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_26_UNCONNECTED,
|
1842 |
|
|
DOB(25) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_25_UNCONNECTED,
|
1843 |
|
|
DOB(24) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_24_UNCONNECTED,
|
1844 |
|
|
DOB(23) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_23_UNCONNECTED,
|
1845 |
|
|
DOB(22) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_22_UNCONNECTED,
|
1846 |
|
|
DOB(21) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_21_UNCONNECTED,
|
1847 |
|
|
DOB(20) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_20_UNCONNECTED,
|
1848 |
|
|
DOB(19) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_19_UNCONNECTED,
|
1849 |
|
|
DOB(18) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_18_UNCONNECTED,
|
1850 |
|
|
DOB(17) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_17_UNCONNECTED,
|
1851 |
|
|
DOB(16) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_16_UNCONNECTED,
|
1852 |
|
|
DOB(15) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_15_UNCONNECTED,
|
1853 |
|
|
DOB(14) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_14_UNCONNECTED,
|
1854 |
|
|
DOB(13) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_13_UNCONNECTED,
|
1855 |
|
|
DOB(12) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_12_UNCONNECTED,
|
1856 |
|
|
DOB(11) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_11_UNCONNECTED,
|
1857 |
|
|
DOB(10) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_10_UNCONNECTED,
|
1858 |
|
|
DOB(9) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_9_UNCONNECTED,
|
1859 |
|
|
DOB(8) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_8_UNCONNECTED,
|
1860 |
|
|
DOB(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_7_UNCONNECTED,
|
1861 |
|
|
DOB(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_6_UNCONNECTED,
|
1862 |
|
|
DOB(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_5_UNCONNECTED,
|
1863 |
|
|
DOB(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_4_UNCONNECTED,
|
1864 |
|
|
DOB(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_3_UNCONNECTED,
|
1865 |
|
|
DOB(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_2_UNCONNECTED,
|
1866 |
|
|
DOB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_1_UNCONNECTED,
|
1867 |
|
|
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_0_UNCONNECTED,
|
1868 |
|
|
DOPB(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_3_UNCONNECTED,
|
1869 |
|
|
DOPB(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_2_UNCONNECTED,
|
1870 |
|
|
DOPB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_1_UNCONNECTED,
|
1871 |
|
|
DOPB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_0_UNCONNECTED
|
1872 |
|
|
);
|
1873 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP : RAMB36_EXP
|
1874 |
|
|
generic map(
|
1875 |
|
|
DOA_REG => 0,
|
1876 |
|
|
DOB_REG => 0,
|
1877 |
|
|
INIT_7E => X"A75D14CA8036ECA2580EC47A30E69C5208BD7329DF944A00B66C21D78C42F8AD",
|
1878 |
|
|
INIT_7F => X"D68D44FBB2681FD68C43FAB0671ED48B41F8AE651BD2883EF5AB6218CE843AF1",
|
1879 |
|
|
INITP_00 => X"4B692D25B496DA4B6925B492DB492DB6924B6DA4925B6DB692492492DB6DB6DB",
|
1880 |
|
|
INITP_01 => X"D296B4B5A5AD2D2969694B4B4B4B4B4B4B4B4B4B6969692D2D25A4B4B696D25A",
|
1881 |
|
|
INITP_02 => X"AD4AD4A56B5295AD4A56B5AD4A5294A5294A5294A5294B5AD694A5AD294B5A52",
|
1882 |
|
|
INITP_03 => X"956A956A956A956AD52A54AB56AD5AB56A54A952B56A56AD4AD5A95A95A95A95",
|
1883 |
|
|
INITP_04 => X"AB555AAA9554AAB554AAB554AA9552AA556AA556AA556AB552A954AA552AD56A",
|
1884 |
|
|
INITP_05 => X"555555554AAAAAAAAD5555552AAAAA955555AAAAA55554AAAAD5552AAAD555AA",
|
1885 |
|
|
INITP_06 => X"AAAB555555555552AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA955",
|
1886 |
|
|
INITP_07 => X"5552AAB5552AAA5554AAAB5555AAAA955552AAAA955555AAAAAAD5555552AAAA",
|
1887 |
|
|
INITP_08 => X"56A956AB54AA552A954AA552A955AA955AA955AAB552AA555AAB554AAB554AAA",
|
1888 |
|
|
INITP_09 => X"8C67398C67398CE7319CE63398C67315AB56AD5AB56A952A55AB54A956A956A9",
|
1889 |
|
|
INITP_0A => X"38C6318C631CE739CE739CE739CE7398C6318C6319CE7398C6319CE7318C6739",
|
1890 |
|
|
INITP_0B => X"31CE31C639C639C639C631CE31CE318E718C739C631CE718C639CE718C639CE7",
|
1891 |
|
|
INITP_0C => X"39C71C638E39C71CE38C71C638E71CE38C718E39C738E71CE39C638C718E718E",
|
1892 |
|
|
INITP_0D => X"1C38E38E38E38E38E38E38E38E38E38E38C71C71C71C718E38E38E71C71C638E",
|
1893 |
|
|
SRVAL_A => X"000000000",
|
1894 |
|
|
SRVAL_B => X"000000000",
|
1895 |
|
|
INIT_00 => X"04B05C09B5610DB96511BD6915C16C18C36F1AC6711CC8731EC9741FCA751FCA",
|
1896 |
|
|
INIT_01 => X"5A08B66412C06E1CCA7825D3802EDB8936E3913EEB9845F29F4CF8A552FEAB57",
|
1897 |
|
|
INIT_02 => X"7828D88837E79746F6A55504B36312C1701FCE7D2CDB8A38E79544F3A14FFEAC",
|
1898 |
|
|
INIT_03 => X"5D0FC17224D58638E99B4CFDAE5F10C17223D38434E59646F7A75708B86818C8",
|
1899 |
|
|
INIT_04 => X"0ABE7125D88B3EF1A4580ABD7023D6883BEDA05205B76A1CCE8032E49648FAAC",
|
1900 |
|
|
INIT_05 => X"7F34EA9F5409BE7227DC9145FAAF6317CC8034E99D5105B96D21D5883CF0A357",
|
1901 |
|
|
INIT_06 => X"BC732AE1984E05BC7228DF954C02B86F25DB9147FDB2681ED4893FF4AA5F15CA",
|
1902 |
|
|
INIT_07 => X"C17A32EBA45C14CD853DF6AE661ED68E46FEB56D24DC944B03BA7129E0974E05",
|
1903 |
|
|
INIT_08 => X"8E4903BE7832ECA6601AD48E4802BC752FE8A25B15CE8740FAB36C25DE975008",
|
1904 |
|
|
INIT_09 => X"24E09C5814D08C4804C07B37F2AE6A25E09C5712CD8843FEB9742FEAA45F1AD4",
|
1905 |
|
|
INIT_0A => X"8240FEBC7A37F5B2702EEBA86623E09D5A17D4914E0BC88441FDBA7633EFAC68",
|
1906 |
|
|
INIT_0B => X"A96928E8A86726E6A56423E2A1601FDE9D5C1AD9985615D391500ECC8A4806C4",
|
1907 |
|
|
INIT_0C => X"995A1CDD9E5F20E1A26324E5A66627E8A86929E9AA6A2AEAAA6A2AEAAA6A2AEA",
|
1908 |
|
|
INIT_0D => X"5215D89B5E21E4A6692CEEB17336F8BA7C3F01C3854709CB8C4E10D2935516D8",
|
1909 |
|
|
INIT_0E => X"D4995D22E7AB7034F8BD81450ACE92561ADEA26529EDB07438FBBE824508CC8F",
|
1910 |
|
|
INIT_0F => X"1FE6AC7239FFC58B5118DDA3692FF5BB80460CD1965C21E6AC7136FBC0854A0F",
|
1911 |
|
|
INIT_10 => X"34FCC48C541CE4AC743B03CB925A21E9B0783F06CD945B22E9B0773E05CB9258",
|
1912 |
|
|
INIT_11 => X"12DCA66F3903CC965F29F2BC854E17E0AA723C04CD965F28F0B9824A12DBA36C",
|
1913 |
|
|
INIT_12 => X"BA85511CE8B37E4A15E0AB76410CD7A26D3702CC97622CF6C18B5520EAB47E48",
|
1914 |
|
|
INIT_13 => X"2BF9C693602DFAC794612EFAC794602DF9C6925E2BF7C38F5B27F3BF8B5722EE",
|
1915 |
|
|
INIT_14 => X"673605D4A271400EDDAC7A4917E5B482501EECBA885624F2BF8D5B28F6C3915E",
|
1916 |
|
|
INIT_15 => X"6D3D0EDEAF7F5020F0C091613101D1A1714010E0AF7F4F1EEDBD8C5B2BFAC998",
|
1917 |
|
|
INIT_16 => X"3D0FE1B386582AFCCEA0714315E7B88A5B2DFED0A1724314E6B788592AFACB9C",
|
1918 |
|
|
INIT_17 => X"D7AB7F5327FACEA275491CF0C3976A3D10E4B78A5D3003D5A87B4E20F3C5986A",
|
1919 |
|
|
INIT_18 => X"3C11E7BD92683D12E8BD92673C11E6BB90653A0EE3B88C61350ADEB2865B2F03",
|
1920 |
|
|
INIT_19 => X"6B421AF1C89F764D24FBD2A980562D04DAB1875D340AE0B68D63390FE5BA9066",
|
1921 |
|
|
INIT_1A => X"653E17F0C9A27B532C04DDB58E663E17EFC79F774F27FFD7AF865E360DE5BC94",
|
1922 |
|
|
INIT_1B => X"2B05E0BA956F4A24FED8B38D67411BF5CFA8825C360FE9C29C754E2801DAB38C",
|
1923 |
|
|
INIT_1C => X"BB9773502C08E4C09C78532F0BE7C29E7955300CE7C29D78542F0AE5BF9A7550",
|
1924 |
|
|
INIT_1D => X"16F4D2B08E6C492604E2BF9C7A583412EFCCA98663401DFAD7B3906D492602DE",
|
1925 |
|
|
INIT_1E => X"3D1CFCDCBB9A7A593817F6D6B4947251300FEECCAB8A68462403E2C09E7C5A38",
|
1926 |
|
|
INIT_1F => X"2F10F2D2B49476563818F9DABA9B7C5C3C1DFDDEBE9E7E5E3E1EFEDEBE9E7E5D",
|
1927 |
|
|
INIT_20 => X"ECD0B295785A3D2002E4C7A98C6E503214F6D8BA9C7E60422305E6C8AA8B6C4E",
|
1928 |
|
|
INIT_21 => X"765A3F2408ECD0B4987C6044280CF0D4B89C7F62462A0DF0D4B79A7E6044260A",
|
1929 |
|
|
INIT_22 => X"CBB1987E64492F15FAE0C6AC91775C42270CF2D7BCA1866B50351AFEE4C8AD92",
|
1930 |
|
|
INIT_23 => X"ECD4BCA48B725A422910F8DEC6AD947B62493017FEE4CBB2987F664C3218FFE5",
|
1931 |
|
|
INIT_24 => X"DAC3AC967E68513A230CF5DEC6B098816A523A230CF4DCC4AC947C654D341C04",
|
1932 |
|
|
INIT_25 => X"937E69543E2A14FFEAD4BEA9947E68523C2711FBE5CFB9A38D76604A341D06F0",
|
1933 |
|
|
INIT_26 => X"1906F2DECBB7A4907C6854402C1804F0DCC8B4A08B77624E392410FBE6D2BDA8",
|
1934 |
|
|
INIT_27 => X"6B594836241200EEDCC9B7A492806E5B48362310FEEBD8C5B29F8C796652402C",
|
1935 |
|
|
INIT_28 => X"8A7A6A594938281807F6E6D5C4B4A39281705F4E3C2C1A09F8E6D5C3B2A08E7D",
|
1936 |
|
|
INIT_29 => X"7667584A3B2C1E0E00F0E2D2C3B4A596867768584838291A0AFAEADACABAAA9A",
|
1937 |
|
|
INIT_2A => X"2E211407FAECE0D2C5B8AA9C8F827466584A3C2E211304F6E8DACCBEB0A19284",
|
1938 |
|
|
INIT_2B => X"B4A89C91867A6E62574B4034281C1003F7EBDED2C6BAADA094887B6E6255483B",
|
1939 |
|
|
INIT_2C => X"06FCF2E8DED4CAC0B6ACA2988D82786E63584E43382E23180D02F7ECE0D6CABF",
|
1940 |
|
|
INIT_2D => X"261E160D04FCF4EBE2DAD2C8C0B7AEA59C948A81786E665C534A40362D231A10",
|
1941 |
|
|
INIT_2E => X"130C06FFF8F2EAE4DCD6CEC7C0B9B2AAA39C948C847D766E665E564E463E362E",
|
1942 |
|
|
INIT_2F => X"CEC8C4BEB9B4AEA9A49E99938E88827C76716B655F59534C46403A342D26201A",
|
1943 |
|
|
INIT_30 => X"56524F4B4844403C3834312D2824201C1814100B0602FEF9F4F0EBE6E2DCD8D2",
|
1944 |
|
|
INIT_31 => X"ACAAA8A6A4A2A09D9B999694928F8C8A8784827F7C797673706D6A6664605D5A",
|
1945 |
|
|
INIT_32 => X"D0D0CFCECECECDCCCCCACAC9C8C7C6C5C4C3C2C0BFBEBCBBBAB8B6B5B3B2B0AE",
|
1946 |
|
|
INIT_33 => X"C2C2C4C5C6C7C8C9CACACBCCCCCDCECECFCFD0D0D0D0D0D1D1D1D1D1D0D0D0D0",
|
1947 |
|
|
INIT_34 => X"8284878A8C8E919496989A9D9FA2A4A6A8AAACAEAFB1B3B4B6B8B9BBBCBEBFC0",
|
1948 |
|
|
INIT_35 => X"1014181C2024282C3034383C4044484B4E5256595C6063666A6C707376797C7E",
|
1949 |
|
|
INIT_36 => X"6C72787E83888E949A9FA4AAAFB4BABEC4C9CED3D8DDE2E6EBF0F4F9FE02060B",
|
1950 |
|
|
INIT_37 => X"979EA6ADB4BCC2CAD0D8DEE6ECF4FA01080E151C22282E353B42484E545A6066",
|
1951 |
|
|
INIT_38 => X"9099A2ABB4BCC5CED6DFE8F0F80109121A222A323A424A525A626A7178808890",
|
1952 |
|
|
INIT_39 => X"58636E78828C96A1ABB5BFC9D3DDE7F1FA040E18212A343E47505A636C757E87",
|
1953 |
|
|
INIT_3A => X"F0FC08141F2B37424E5A66717C88949FAAB6C0CCD7E2EDF8030E18232E38444E",
|
1954 |
|
|
INIT_3B => X"5663707E8B98A6B3C0CEDBE8F5020F1C2836424F5C6874818E9AA6B2BFCBD7E4",
|
1955 |
|
|
INIT_3C => X"8A9AA8B8C6D6E4F302101F2E3C4B5968768492A1AFBDCBD9E7F503111E2C3A48",
|
1956 |
|
|
INIT_3D => X"8E9FB0C0D0E1F202122232425263728292A2B2C2D2E2F10010202F3E4E5D6C7B",
|
1957 |
|
|
INIT_3E => X"62748698AABCCEE0F2041527384A5C6D7E90A1B2C4D4E6F708192A3B4C5C6D7E",
|
1958 |
|
|
INIT_3F => X"05182C4053667A8EA0B4C7DAEE0014263A4C5F728598AABCCFE2F406192B3E50",
|
1959 |
|
|
INIT_40 => X"778CA2B6CCE0F60A1F34485E72869BB0C4D8ED01162A3E52667A8EA2B6CADEF1",
|
1960 |
|
|
INIT_41 => X"B9D0E6FD142A40576D849AB0C6DCF2081E344A60768CA1B6CCE2F70C22384D62",
|
1961 |
|
|
INIT_42 => X"CBE3FC142C445C738BA3BAD2EA0219304860778EA6BDD4EB021A30475E758CA2",
|
1962 |
|
|
INIT_43 => X"ADC6E0FA132C46607992ACC4DEF71029425B748CA6BED7F0082039526A829AB3",
|
1963 |
|
|
INIT_44 => X"5E7A94B0CBE6001C36516C86A2BCD6F10C26405A758FAAC4DEF8122C46607993",
|
1964 |
|
|
INIT_45 => X"E0FD1A36526F8CA8C4E0FC1935516D89A5C1DDF914304C68849FBAD6F10C2843",
|
1965 |
|
|
INIT_46 => X"32506E8CAAC8E60422405E7B99B6D4F20F2C4A6784A2BFDCF91633506D8AA6C4",
|
1966 |
|
|
INIT_47 => X"547494B3D2F2123150708EAECDEC0B2A496887A6C4E302203F5E7C9AB9D7F614",
|
1967 |
|
|
INIT_48 => X"47688AAACCEC0D2E4F7090B1D2F21333547494B4D5F51636567696B6D5F51534",
|
1968 |
|
|
INIT_49 => X"0A2D507294B7DAFC1E406284A6C9EB0C2E507294B6D8F91B3C5E80A1C2E40426",
|
1969 |
|
|
INIT_4A => X"9EC2E60A2E52769ABEE205294C7094B7DAFE2144688AAED1F4173A5C80A2C5E8",
|
1970 |
|
|
INIT_4B => X"03284E7499BEE4092E54789EC3E80D32567CA0C5EA0E33587CA0C5E90E32567A",
|
1971 |
|
|
INIT_4C => X"1CB044D76AFE9124B84BDE7205982CBF52E5780B9E32C458EA7E10466C92B8DE",
|
1972 |
|
|
INIT_4D => X"A034C85CF08519AD41D569FD9125B94DE175099C30C458EC8013A73ACE62F589",
|
1973 |
|
|
INIT_4E => X"0CA036CA5FF4891EB348DC71069A2FC458ED8216AB40D468FD9126BA4EE3770C",
|
1974 |
|
|
INIT_4F => X"60F68C21B74CE2780DA238CE63F88E23B94EE4790EA338CE63F88D22B84CE276",
|
1975 |
|
|
INIT_50 => X"9D34CA60F78D24BA50E67C13A93FD56C02982EC45AF0861CB248DD73099F34CA",
|
1976 |
|
|
INIT_51 => X"C35AF28820B74EE57C13AA41D86E069C33CA61F88E25BC52E98016AC43DA7007",
|
1977 |
|
|
INIT_52 => X"D26A029A31C961F89028C057EF861EB64DE57C14AB43DA7209A038CF66FE952C",
|
1978 |
|
|
INIT_53 => X"C962FA932CC45CF58E26BE57EF8820B850E98119B14AE27A12AA42DA720AA23A",
|
1979 |
|
|
INIT_54 => X"AA43DC760FA841DA740DA63FD8710AA33CD56E07A039D26B049C35CE66FF9830",
|
1980 |
|
|
INIT_55 => X"730DA741DB750FA943DD7610AA44DE7811AB44DE7812AB44DE7811AA44DE7710",
|
1981 |
|
|
INIT_56 => X"25C05BF6902BC660FB9630CA65009A34CF6A049E38D36D08A23CD6700AA53FD9",
|
1982 |
|
|
INIT_57 => X"C05CF8932ECA65009C37D26E09A440DB7611AC47E27D18B34EE9841FBA55F08A",
|
1983 |
|
|
INIT_58 => X"45E17E1AB652EE8A26C25EFA9632CE6A06A23ED97511AC48E4801BB752EE8A25",
|
1984 |
|
|
INIT_59 => X"B350EC8A26C360FD9A36D3700CA946E27F1BB854F18E2AC663FF9C38D4700CA9",
|
1985 |
|
|
INIT_5A => X"0AA745E2801EBB58F69431CE6C09A644E17E1CB956F3902ECA6805A23FDC7916",
|
1986 |
|
|
INIT_5B => X"4AE88624C361009E3CDA7816B452F08E2CCA6806A442E07E1CBA57F59330CE6C",
|
1987 |
|
|
INIT_5C => X"7312B150EF8E2DCC6B0AA848E68524C261009E3DDC7A19B856F59332D06E0DAB",
|
1988 |
|
|
INIT_5D => X"8626C56505A444E48323C26202A140E07F1FBE5EFD9C3BDB7A19B858F79635D4",
|
1989 |
|
|
INIT_5E => X"8222C36304A444E58526C66606A646E68727C76707A747E78727C76706A646E6",
|
1990 |
|
|
INIT_5F => X"6809AA4BEC8D2ED07012B253F49536D77818B95AFB9C3CDD7E1EBF6000A041E2",
|
1991 |
|
|
INIT_60 => X"37D97A1CBE6002A445E7882ACC6E0FB052F49536D87A1BBC5EFFA042E38425C6",
|
1992 |
|
|
INIT_61 => X"F09235D77A1CBF6104A648EB8D2FD27416B85AFD9F41E38527C96B0DAF51F395",
|
1993 |
|
|
INIT_62 => X"9235D87C1FC26508AC4FF29538DB7E21C4660AAC4FF29538DA7D20C26508AA4D",
|
1994 |
|
|
INIT_63 => X"1EC2660AAE52F69A3DE18528CC7014B75BFEA246E98D30D4771BBE6205A84CEF",
|
1995 |
|
|
INIT_64 => X"9438DD8226CB7014B85D02A64AEF9338DC8024C96D11B65AFEA246EA8E32D67A",
|
1996 |
|
|
INIT_65 => X"F4993EE4892ED3781EC3680DB258FCA246EC9036DA7F24C96E13B85C01A64AEF",
|
1997 |
|
|
INIT_66 => X"3DE3892FD57B21C76D12B85E04AA50F59B41E68C32D77D22C86E13B85E04A94E",
|
1998 |
|
|
INIT_67 => X"7017BE640BB258FFA64CF39940E68C33DA8026CC7319C0660CB258FEA44BF197",
|
1999 |
|
|
INIT_68 => X"8E35DC842BD27A21C87017BE650CB45A02A950F79E45EC933AE0882ED57C23CA",
|
2000 |
|
|
INIT_69 => X"953DE58D35DD852DD57D25CD751CC46C14BC640BB35A02AA52F9A048F0973FE6",
|
2001 |
|
|
INIT_6A => X"862FD88029D27A23CC741DC66E17BF6810B8610AB25A02AB53FCA44CF49C44ED",
|
2002 |
|
|
INIT_6B => X"620BB45E07B05A03AD56FFA852FBA44DF6A049F29B44ED963FE8913AE38C34DD",
|
2003 |
|
|
INIT_6C => X"27D17B25D07A24CE7822CC7620C9731DC7711AC46E18C26B15BE6812BB650EB8",
|
2004 |
|
|
INIT_6D => X"D6822CD7822CD7822DD8822DD7822CD7822CD6812BD6802AD57F2AD47E28D27D",
|
2005 |
|
|
INIT_6E => X"701CC8731ECA7521CC7823CE7924D07B26D27C28D37E29D47F2AD5802BD6812C",
|
2006 |
|
|
INIT_6F => X"F5A14DF9A552FEAA5602AE5A06B25E0AB5610DB96410BC6814BF6B16C26E1AC5",
|
2007 |
|
|
INIT_70 => X"6310BD6A16C4701DCA7623D07C29D6822FDB8834E18D3AE6923FEB9844F09C48",
|
2008 |
|
|
INIT_71 => X"BC6A17C57220CD7A28D58330DD8A38E59240ED9A47F4A14EFCA85602B05C0AB6",
|
2009 |
|
|
INIT_72 => X"00AE5C0AB86614C2711FCD7B29D78532E08E3CEA9846F4A14FFDAA5806B4610E",
|
2010 |
|
|
INIT_73 => X"2DDC8B3AE99846F5A45201B05F0DBC6A19C87625D38230DE8D3BEA9846F5A351",
|
2011 |
|
|
INIT_74 => X"46F5A55404B36312C27120D07F2EDE8D3CEC9A4AF9A85706B66414C27220D07E",
|
2012 |
|
|
INIT_75 => X"48F9A9590ABA6A1ACA7A2ADA8A3AEA9A4AFAAA5A09B96919C87828D88737E696",
|
2013 |
|
|
INIT_76 => X"36E79849FAAA5B0CBD6E1ECF8030E19242F3A35404B56516C67627D78838E898",
|
2014 |
|
|
INIT_77 => X"0EC07223D48638E99A4CFDAE6011C27425D68838EA9B4CFDAE5F10C27223D485",
|
2015 |
|
|
INIT_78 => X"D28436E89A4CFEB06315C7792BDD8F41F2A45608BA6C1ED08133E49648FAAB5D",
|
2016 |
|
|
INIT_79 => X"7F32E5984AFEB06316C87B2EE09346F8AB5E10C27528DA8C3FF1A45608BA6D1F",
|
2017 |
|
|
INIT_7A => X"18CB7F32E6994D00B4671ACE8134E89B4E01B4681BCE8134E79A4D00B36619CC",
|
2018 |
|
|
INIT_7B => X"9B4F04B86C20D4883CF0A4580CC07428DC9044F8AC5F13C77A2EE29649FDB064",
|
2019 |
|
|
INIT_7C => X"0ABE7328DD9246FBB06419CE8237ECA0550ABE7227DC9044F9AD6216CA7E32E7",
|
2020 |
|
|
INIT_7D => X"6318CE8339EEA4590EC4792EE4994E04B96E23D88E42F8AD6217CC8136EBA054",
|
2021 |
|
|
INITP_0E => X"71C38E1C70E3871C78E3871C78E38F1C71E38E3871C71C78E38E38F1C71C71C7",
|
2022 |
|
|
INIT_FILE => "NONE",
|
2023 |
|
|
RAM_EXTENSION_A => "NONE",
|
2024 |
|
|
RAM_EXTENSION_B => "NONE",
|
2025 |
|
|
READ_WIDTH_A => 9,
|
2026 |
|
|
READ_WIDTH_B => 9,
|
2027 |
|
|
SIM_COLLISION_CHECK => "ALL",
|
2028 |
|
|
SIM_MODE => "SAFE",
|
2029 |
|
|
INIT_A => X"000000000",
|
2030 |
|
|
INIT_B => X"000000000",
|
2031 |
|
|
WRITE_MODE_A => "WRITE_FIRST",
|
2032 |
|
|
WRITE_MODE_B => "WRITE_FIRST",
|
2033 |
|
|
WRITE_WIDTH_A => 9,
|
2034 |
|
|
WRITE_WIDTH_B => 9,
|
2035 |
|
|
INITP_0F => X"E1C3870E1C3870E3C78F1C3871E3C70E1C78E1C78F1C38F1C78E1C78E3C70E38"
|
2036 |
|
|
)
|
2037 |
|
|
port map (
|
2038 |
|
|
ENAU => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_2_cmp_eq0000,
|
2039 |
|
|
ENAL => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_2_cmp_eq0000,
|
2040 |
|
|
ENBU => BU2_doutb(0),
|
2041 |
|
|
ENBL => BU2_doutb(0),
|
2042 |
|
|
SSRAU => BU2_doutb(0),
|
2043 |
|
|
SSRAL => BU2_doutb(0),
|
2044 |
|
|
SSRBU => BU2_doutb(0),
|
2045 |
|
|
SSRBL => BU2_doutb(0),
|
2046 |
|
|
CLKAU => clka,
|
2047 |
|
|
CLKAL => clka,
|
2048 |
|
|
CLKBU => BU2_doutb(0),
|
2049 |
|
|
CLKBL => BU2_doutb(0),
|
2050 |
|
|
REGCLKAU => clka,
|
2051 |
|
|
REGCLKAL => clka,
|
2052 |
|
|
REGCLKBU => BU2_doutb(0),
|
2053 |
|
|
REGCLKBL => BU2_doutb(0),
|
2054 |
|
|
REGCEAU => BU2_doutb(0),
|
2055 |
|
|
REGCEAL => BU2_doutb(0),
|
2056 |
|
|
REGCEBU => BU2_doutb(0),
|
2057 |
|
|
REGCEBL => BU2_doutb(0),
|
2058 |
|
|
CASCADEINLATA => BU2_doutb(0),
|
2059 |
|
|
CASCADEINLATB => BU2_doutb(0),
|
2060 |
|
|
CASCADEINREGA => BU2_doutb(0),
|
2061 |
|
|
CASCADEINREGB => BU2_doutb(0),
|
2062 |
|
|
CASCADEOUTLATA => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATA_UNCONNECTED,
|
2063 |
|
|
CASCADEOUTLATB => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATB_UNCONNECTED,
|
2064 |
|
|
CASCADEOUTREGA => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGA_UNCONNECTED,
|
2065 |
|
|
CASCADEOUTREGB => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGB_UNCONNECTED,
|
2066 |
|
|
DIA(31) => BU2_doutb(0),
|
2067 |
|
|
DIA(30) => BU2_doutb(0),
|
2068 |
|
|
DIA(29) => BU2_doutb(0),
|
2069 |
|
|
DIA(28) => BU2_doutb(0),
|
2070 |
|
|
DIA(27) => BU2_doutb(0),
|
2071 |
|
|
DIA(26) => BU2_doutb(0),
|
2072 |
|
|
DIA(25) => BU2_doutb(0),
|
2073 |
|
|
DIA(24) => BU2_doutb(0),
|
2074 |
|
|
DIA(23) => BU2_doutb(0),
|
2075 |
|
|
DIA(22) => BU2_doutb(0),
|
2076 |
|
|
DIA(21) => BU2_doutb(0),
|
2077 |
|
|
DIA(20) => BU2_doutb(0),
|
2078 |
|
|
DIA(19) => BU2_doutb(0),
|
2079 |
|
|
DIA(18) => BU2_doutb(0),
|
2080 |
|
|
DIA(17) => BU2_doutb(0),
|
2081 |
|
|
DIA(16) => BU2_doutb(0),
|
2082 |
|
|
DIA(15) => BU2_doutb(0),
|
2083 |
|
|
DIA(14) => BU2_doutb(0),
|
2084 |
|
|
DIA(13) => BU2_doutb(0),
|
2085 |
|
|
DIA(12) => BU2_doutb(0),
|
2086 |
|
|
DIA(11) => BU2_doutb(0),
|
2087 |
|
|
DIA(10) => BU2_doutb(0),
|
2088 |
|
|
DIA(9) => BU2_doutb(0),
|
2089 |
|
|
DIA(8) => BU2_doutb(0),
|
2090 |
|
|
DIA(7) => BU2_doutb(0),
|
2091 |
|
|
DIA(6) => BU2_doutb(0),
|
2092 |
|
|
DIA(5) => BU2_doutb(0),
|
2093 |
|
|
DIA(4) => BU2_doutb(0),
|
2094 |
|
|
DIA(3) => BU2_doutb(0),
|
2095 |
|
|
DIA(2) => BU2_doutb(0),
|
2096 |
|
|
DIA(1) => BU2_doutb(0),
|
2097 |
|
|
DIA(0) => BU2_doutb(0),
|
2098 |
|
|
DIPA(3) => BU2_doutb(0),
|
2099 |
|
|
DIPA(2) => BU2_doutb(0),
|
2100 |
|
|
DIPA(1) => BU2_doutb(0),
|
2101 |
|
|
DIPA(0) => BU2_doutb(0),
|
2102 |
|
|
DIB(31) => BU2_doutb(0),
|
2103 |
|
|
DIB(30) => BU2_doutb(0),
|
2104 |
|
|
DIB(29) => BU2_doutb(0),
|
2105 |
|
|
DIB(28) => BU2_doutb(0),
|
2106 |
|
|
DIB(27) => BU2_doutb(0),
|
2107 |
|
|
DIB(26) => BU2_doutb(0),
|
2108 |
|
|
DIB(25) => BU2_doutb(0),
|
2109 |
|
|
DIB(24) => BU2_doutb(0),
|
2110 |
|
|
DIB(23) => BU2_doutb(0),
|
2111 |
|
|
DIB(22) => BU2_doutb(0),
|
2112 |
|
|
DIB(21) => BU2_doutb(0),
|
2113 |
|
|
DIB(20) => BU2_doutb(0),
|
2114 |
|
|
DIB(19) => BU2_doutb(0),
|
2115 |
|
|
DIB(18) => BU2_doutb(0),
|
2116 |
|
|
DIB(17) => BU2_doutb(0),
|
2117 |
|
|
DIB(16) => BU2_doutb(0),
|
2118 |
|
|
DIB(15) => BU2_doutb(0),
|
2119 |
|
|
DIB(14) => BU2_doutb(0),
|
2120 |
|
|
DIB(13) => BU2_doutb(0),
|
2121 |
|
|
DIB(12) => BU2_doutb(0),
|
2122 |
|
|
DIB(11) => BU2_doutb(0),
|
2123 |
|
|
DIB(10) => BU2_doutb(0),
|
2124 |
|
|
DIB(9) => BU2_doutb(0),
|
2125 |
|
|
DIB(8) => BU2_doutb(0),
|
2126 |
|
|
DIB(7) => BU2_doutb(0),
|
2127 |
|
|
DIB(6) => BU2_doutb(0),
|
2128 |
|
|
DIB(5) => BU2_doutb(0),
|
2129 |
|
|
DIB(4) => BU2_doutb(0),
|
2130 |
|
|
DIB(3) => BU2_doutb(0),
|
2131 |
|
|
DIB(2) => BU2_doutb(0),
|
2132 |
|
|
DIB(1) => BU2_doutb(0),
|
2133 |
|
|
DIB(0) => BU2_doutb(0),
|
2134 |
|
|
DIPB(3) => BU2_doutb(0),
|
2135 |
|
|
DIPB(2) => BU2_doutb(0),
|
2136 |
|
|
DIPB(1) => BU2_doutb(0),
|
2137 |
|
|
DIPB(0) => BU2_doutb(0),
|
2138 |
|
|
ADDRAL(15) => BU2_doutb(0),
|
2139 |
|
|
ADDRAL(14) => addra_2(11),
|
2140 |
|
|
ADDRAL(13) => addra_2(10),
|
2141 |
|
|
ADDRAL(12) => addra_2(9),
|
2142 |
|
|
ADDRAL(11) => addra_2(8),
|
2143 |
|
|
ADDRAL(10) => addra_2(7),
|
2144 |
|
|
ADDRAL(9) => addra_2(6),
|
2145 |
|
|
ADDRAL(8) => addra_2(5),
|
2146 |
|
|
ADDRAL(7) => addra_2(4),
|
2147 |
|
|
ADDRAL(6) => addra_2(3),
|
2148 |
|
|
ADDRAL(5) => addra_2(2),
|
2149 |
|
|
ADDRAL(4) => addra_2(1),
|
2150 |
|
|
ADDRAL(3) => addra_2(0),
|
2151 |
|
|
ADDRAL(2) => BU2_doutb(0),
|
2152 |
|
|
ADDRAL(1) => BU2_doutb(0),
|
2153 |
|
|
ADDRAL(0) => BU2_doutb(0),
|
2154 |
|
|
ADDRAU(14) => addra_2(11),
|
2155 |
|
|
ADDRAU(13) => addra_2(10),
|
2156 |
|
|
ADDRAU(12) => addra_2(9),
|
2157 |
|
|
ADDRAU(11) => addra_2(8),
|
2158 |
|
|
ADDRAU(10) => addra_2(7),
|
2159 |
|
|
ADDRAU(9) => addra_2(6),
|
2160 |
|
|
ADDRAU(8) => addra_2(5),
|
2161 |
|
|
ADDRAU(7) => addra_2(4),
|
2162 |
|
|
ADDRAU(6) => addra_2(3),
|
2163 |
|
|
ADDRAU(5) => addra_2(2),
|
2164 |
|
|
ADDRAU(4) => addra_2(1),
|
2165 |
|
|
ADDRAU(3) => addra_2(0),
|
2166 |
|
|
ADDRAU(2) => BU2_doutb(0),
|
2167 |
|
|
ADDRAU(1) => BU2_doutb(0),
|
2168 |
|
|
ADDRAU(0) => BU2_doutb(0),
|
2169 |
|
|
ADDRBL(15) => BU2_doutb(0),
|
2170 |
|
|
ADDRBL(14) => BU2_doutb(0),
|
2171 |
|
|
ADDRBL(13) => BU2_doutb(0),
|
2172 |
|
|
ADDRBL(12) => BU2_doutb(0),
|
2173 |
|
|
ADDRBL(11) => BU2_doutb(0),
|
2174 |
|
|
ADDRBL(10) => BU2_doutb(0),
|
2175 |
|
|
ADDRBL(9) => BU2_doutb(0),
|
2176 |
|
|
ADDRBL(8) => BU2_doutb(0),
|
2177 |
|
|
ADDRBL(7) => BU2_doutb(0),
|
2178 |
|
|
ADDRBL(6) => BU2_doutb(0),
|
2179 |
|
|
ADDRBL(5) => BU2_doutb(0),
|
2180 |
|
|
ADDRBL(4) => BU2_doutb(0),
|
2181 |
|
|
ADDRBL(3) => BU2_doutb(0),
|
2182 |
|
|
ADDRBL(2) => BU2_doutb(0),
|
2183 |
|
|
ADDRBL(1) => BU2_doutb(0),
|
2184 |
|
|
ADDRBL(0) => BU2_doutb(0),
|
2185 |
|
|
ADDRBU(14) => BU2_doutb(0),
|
2186 |
|
|
ADDRBU(13) => BU2_doutb(0),
|
2187 |
|
|
ADDRBU(12) => BU2_doutb(0),
|
2188 |
|
|
ADDRBU(11) => BU2_doutb(0),
|
2189 |
|
|
ADDRBU(10) => BU2_doutb(0),
|
2190 |
|
|
ADDRBU(9) => BU2_doutb(0),
|
2191 |
|
|
ADDRBU(8) => BU2_doutb(0),
|
2192 |
|
|
ADDRBU(7) => BU2_doutb(0),
|
2193 |
|
|
ADDRBU(6) => BU2_doutb(0),
|
2194 |
|
|
ADDRBU(5) => BU2_doutb(0),
|
2195 |
|
|
ADDRBU(4) => BU2_doutb(0),
|
2196 |
|
|
ADDRBU(3) => BU2_doutb(0),
|
2197 |
|
|
ADDRBU(2) => BU2_doutb(0),
|
2198 |
|
|
ADDRBU(1) => BU2_doutb(0),
|
2199 |
|
|
ADDRBU(0) => BU2_doutb(0),
|
2200 |
|
|
WEAU(3) => BU2_doutb(0),
|
2201 |
|
|
WEAU(2) => BU2_doutb(0),
|
2202 |
|
|
WEAU(1) => BU2_doutb(0),
|
2203 |
|
|
WEAU(0) => BU2_doutb(0),
|
2204 |
|
|
WEAL(3) => BU2_doutb(0),
|
2205 |
|
|
WEAL(2) => BU2_doutb(0),
|
2206 |
|
|
WEAL(1) => BU2_doutb(0),
|
2207 |
|
|
WEAL(0) => BU2_doutb(0),
|
2208 |
|
|
WEBU(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_7_UNCONNECTED,
|
2209 |
|
|
WEBU(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_6_UNCONNECTED,
|
2210 |
|
|
WEBU(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_5_UNCONNECTED,
|
2211 |
|
|
WEBU(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_4_UNCONNECTED,
|
2212 |
|
|
WEBU(3) => BU2_doutb(0),
|
2213 |
|
|
WEBU(2) => BU2_doutb(0),
|
2214 |
|
|
WEBU(1) => BU2_doutb(0),
|
2215 |
|
|
WEBU(0) => BU2_doutb(0),
|
2216 |
|
|
WEBL(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_7_UNCONNECTED,
|
2217 |
|
|
WEBL(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_6_UNCONNECTED,
|
2218 |
|
|
WEBL(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_5_UNCONNECTED,
|
2219 |
|
|
WEBL(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_4_UNCONNECTED,
|
2220 |
|
|
WEBL(3) => BU2_doutb(0),
|
2221 |
|
|
WEBL(2) => BU2_doutb(0),
|
2222 |
|
|
WEBL(1) => BU2_doutb(0),
|
2223 |
|
|
WEBL(0) => BU2_doutb(0),
|
2224 |
|
|
DOA(31) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_31_UNCONNECTED,
|
2225 |
|
|
DOA(30) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_30_UNCONNECTED,
|
2226 |
|
|
DOA(29) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_29_UNCONNECTED,
|
2227 |
|
|
DOA(28) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_28_UNCONNECTED,
|
2228 |
|
|
DOA(27) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_27_UNCONNECTED,
|
2229 |
|
|
DOA(26) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_26_UNCONNECTED,
|
2230 |
|
|
DOA(25) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_25_UNCONNECTED,
|
2231 |
|
|
DOA(24) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_24_UNCONNECTED,
|
2232 |
|
|
DOA(23) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_23_UNCONNECTED,
|
2233 |
|
|
DOA(22) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_22_UNCONNECTED,
|
2234 |
|
|
DOA(21) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_21_UNCONNECTED,
|
2235 |
|
|
DOA(20) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_20_UNCONNECTED,
|
2236 |
|
|
DOA(19) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_19_UNCONNECTED,
|
2237 |
|
|
DOA(18) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_18_UNCONNECTED,
|
2238 |
|
|
DOA(17) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_17_UNCONNECTED,
|
2239 |
|
|
DOA(16) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_16_UNCONNECTED,
|
2240 |
|
|
DOA(15) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_15_UNCONNECTED,
|
2241 |
|
|
DOA(14) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_14_UNCONNECTED,
|
2242 |
|
|
DOA(13) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_13_UNCONNECTED,
|
2243 |
|
|
DOA(12) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_12_UNCONNECTED,
|
2244 |
|
|
DOA(11) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_11_UNCONNECTED,
|
2245 |
|
|
DOA(10) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_10_UNCONNECTED,
|
2246 |
|
|
DOA(9) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_9_UNCONNECTED,
|
2247 |
|
|
DOA(8) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_8_UNCONNECTED,
|
2248 |
|
|
DOA(7) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta1(7),
|
2249 |
|
|
DOA(6) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta1(6),
|
2250 |
|
|
DOA(5) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta1(5),
|
2251 |
|
|
DOA(4) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta1(4),
|
2252 |
|
|
DOA(3) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta1(3),
|
2253 |
|
|
DOA(2) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta1(2),
|
2254 |
|
|
DOA(1) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta1(1),
|
2255 |
|
|
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta1(0),
|
2256 |
|
|
DOPA(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_3_UNCONNECTED,
|
2257 |
|
|
DOPA(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_2_UNCONNECTED,
|
2258 |
|
|
DOPA(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_1_UNCONNECTED,
|
2259 |
|
|
DOPA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta1(8),
|
2260 |
|
|
DOB(31) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_31_UNCONNECTED,
|
2261 |
|
|
DOB(30) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_30_UNCONNECTED,
|
2262 |
|
|
DOB(29) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_29_UNCONNECTED,
|
2263 |
|
|
DOB(28) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_28_UNCONNECTED,
|
2264 |
|
|
DOB(27) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_27_UNCONNECTED,
|
2265 |
|
|
DOB(26) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_26_UNCONNECTED,
|
2266 |
|
|
DOB(25) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_25_UNCONNECTED,
|
2267 |
|
|
DOB(24) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_24_UNCONNECTED,
|
2268 |
|
|
DOB(23) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_23_UNCONNECTED,
|
2269 |
|
|
DOB(22) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_22_UNCONNECTED,
|
2270 |
|
|
DOB(21) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_21_UNCONNECTED,
|
2271 |
|
|
DOB(20) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_20_UNCONNECTED,
|
2272 |
|
|
DOB(19) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_19_UNCONNECTED,
|
2273 |
|
|
DOB(18) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_18_UNCONNECTED,
|
2274 |
|
|
DOB(17) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_17_UNCONNECTED,
|
2275 |
|
|
DOB(16) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_16_UNCONNECTED,
|
2276 |
|
|
DOB(15) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_15_UNCONNECTED,
|
2277 |
|
|
DOB(14) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_14_UNCONNECTED,
|
2278 |
|
|
DOB(13) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_13_UNCONNECTED,
|
2279 |
|
|
DOB(12) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_12_UNCONNECTED,
|
2280 |
|
|
DOB(11) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_11_UNCONNECTED,
|
2281 |
|
|
DOB(10) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_10_UNCONNECTED,
|
2282 |
|
|
DOB(9) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_9_UNCONNECTED,
|
2283 |
|
|
DOB(8) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_8_UNCONNECTED,
|
2284 |
|
|
DOB(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_7_UNCONNECTED,
|
2285 |
|
|
DOB(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_6_UNCONNECTED,
|
2286 |
|
|
DOB(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_5_UNCONNECTED,
|
2287 |
|
|
DOB(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_4_UNCONNECTED,
|
2288 |
|
|
DOB(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_3_UNCONNECTED,
|
2289 |
|
|
DOB(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_2_UNCONNECTED,
|
2290 |
|
|
DOB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_1_UNCONNECTED,
|
2291 |
|
|
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_0_UNCONNECTED,
|
2292 |
|
|
DOPB(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_3_UNCONNECTED,
|
2293 |
|
|
DOPB(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_2_UNCONNECTED,
|
2294 |
|
|
DOPB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_1_UNCONNECTED,
|
2295 |
|
|
DOPB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_0_UNCONNECTED
|
2296 |
|
|
);
|
2297 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP : RAMB36_EXP
|
2298 |
|
|
generic map(
|
2299 |
|
|
DOA_REG => 0,
|
2300 |
|
|
DOB_REG => 0,
|
2301 |
|
|
INIT_7E => X"100F0F0E0E0D0C0C0B0B0A09080807060605040302020100FFFEFDFCFBFAF9F8",
|
2302 |
|
|
INIT_7F => X"1818181818181818171717171717161616161515151414141313121212111110",
|
2303 |
|
|
INITP_00 => X"3C387870F1E1E3C3878F0E1E3C3878F0E1E3C7870E1E3C78F1E1C3870E1C3870",
|
2304 |
|
|
INITP_01 => X"F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F1E1E1E1E1E3C3C3C38787870F0F1E1E3C",
|
2305 |
|
|
INITP_02 => X"7C3E1E0F0787C3C1E1F0F078783C3C1E1E0F0F07878783C3C3C1E1E1E1E1F0F0",
|
2306 |
|
|
INITP_03 => X"F0F83E0F07C1E0F83C1F0F83C1F0F83C1F0F87C3E0F0783C1E0F0783C1E0F078",
|
2307 |
|
|
INITP_04 => X"7E0F81F07C0F83E0FC1F07C1F83E0F83E0F83E0F83E0F83E0F83E0F83C1F07C1",
|
2308 |
|
|
INITP_05 => X"FC0FC0F81F81F83F03F07E07C0FC1F81F03E07C0F81F03E07C0F81F07E0F81F0",
|
2309 |
|
|
INITP_06 => X"81FC0FE07F03F81FC0FC07E07F03F01F81F81FC0FC0FC0FC0FC0FE0FC0FC0FC0",
|
2310 |
|
|
INITP_07 => X"F01FE03F807F01FE03F80FF01FC07F01FC07F01FC07F01F80FE03F01FC07E03F",
|
2311 |
|
|
INITP_08 => X"E00FF007F803FC01FE01FE00FF00FF00FF00FF00FF00FE01FE01FC03FC07F80F",
|
2312 |
|
|
INITP_09 => X"00FFC00FFC00FF801FF801FF003FE00FFC01FF007FE00FF803FE01FF007FC01F",
|
2313 |
|
|
INITP_0A => X"FF8007FF8007FF8007FF000FFE001FFC007FF001FFC00FFE003FF001FF801FFC",
|
2314 |
|
|
INITP_0B => X"03FFFC0007FFF0003FFF8001FFF8001FFF0003FFE0007FFC001FFE000FFF8007",
|
2315 |
|
|
INITP_0C => X"00007FFFF80000FFFFF00003FFFF80003FFFF00007FFFC0001FFFE0001FFFE00",
|
2316 |
|
|
INITP_0D => X"00000001FFFFFFF0000001FFFFFFC000001FFFFFE000003FFFFF800001FFFFF0",
|
2317 |
|
|
SRVAL_A => X"000000000",
|
2318 |
|
|
SRVAL_B => X"000000000",
|
2319 |
|
|
INIT_00 => X"F1A86017CF863EF5AC641BD28940F8AF661ED48C43FAB1681FD68D44FBB26920",
|
2320 |
|
|
INIT_01 => X"F6AE671FD78F47FFB76F27DF974F06BE762EE69E560DC57C34ECA45B13CA8239",
|
2321 |
|
|
INIT_02 => X"E7A05912CA833CF4AD661ED7904800B9722AE29B530CC47C34EDA55E16CE863E",
|
2322 |
|
|
INIT_03 => X"C37D36F0A9621CD58E4801BA732CE69F5811CA833CF5AE6720D9924B04BD762E",
|
2323 |
|
|
INIT_04 => X"8A45FFB9732DE7A15B15CE8842FCB6702AE39D5710CA843EF7B16A24DD97500A",
|
2324 |
|
|
INIT_05 => X"3DF8B36E28E39D5812CD8842FDB7722CE6A15B16D08A45FFB9742EE8A25C16D0",
|
2325 |
|
|
INIT_06 => X"DB97520DC9843FFAB6712CE7A25E19D48F4A05C07B36F1AC6722DC97520DC882",
|
2326 |
|
|
INIT_07 => X"6521DD995511CC884400BC7834F0AB6722DE9A5611CD884400BB7732EEA96420",
|
2327 |
|
|
INIT_08 => X"DA965310CC894502BE7B37F4B06D29E5A25E1AD7934F0CC88440FCB87431EDA9",
|
2328 |
|
|
INIT_09 => X"3AF7B5722FECAA6724E19E5B18D592500CCA864300BD7A37F4B06D2AE7A4601D",
|
2329 |
|
|
INIT_0A => X"864402C07E3CFAB77533F1AE6C2AE7A56320DE9C5917D4924F0CCA874502C07D",
|
2330 |
|
|
INIT_0B => X"BE7C3BF9B87635F3B2702EEDAB6A28E6A46321DF9D5C1AD8965412D08E4C0AC8",
|
2331 |
|
|
INIT_0C => X"E1A05F1FDE9D5C1BDA995817D6955413D291500ECD8C4B0AC8874605C38240FF",
|
2332 |
|
|
INIT_0D => X"F0B0702FEFAF6F2EEEAE6E2DEDAC6C2CEBAA6A2AE9A86827E7A66525E4A36222",
|
2333 |
|
|
INIT_0E => X"EBAB6C2CECAD6D2EEEAE6E2FEFAF7030F0B07030F0B07030F0B07030F0B07030",
|
2334 |
|
|
INIT_0F => X"D1925314D5965818D99A5B1CDD9E5F20E0A16223E4A46526E6A76728E9A96A2A",
|
2335 |
|
|
INIT_10 => X"A46527E9AA6C2EEFB17234F5B7783AFBBD7E4001C2844506C8894A0BCC8E4F10",
|
2336 |
|
|
INIT_11 => X"6224E6A96B2DF0B27436F8BA7D3F01C3854709CB8D4F11D3955719DA9C5E20E2",
|
2337 |
|
|
INIT_12 => X"0CCF925518DA9D6023E6A96C2EF1B47639FCBE814406C98C4E10D396581ADD9F",
|
2338 |
|
|
INIT_13 => X"A26529ECB07437FBBE824508CC8F5316D99C6023E6AA6D30F3B6793C00C38649",
|
2339 |
|
|
INIT_14 => X"24E8AC7035F9BD814509CD915519DDA16529EDB17539FDC084480CCF93571ADE",
|
2340 |
|
|
INIT_15 => X"92571CE0A56A2FF4B87D4206CB905419DDA2662BF0B4783D01C68A4E13D79B60",
|
2341 |
|
|
INIT_16 => X"ECB2773C02C78D5218DDA2672DF2B77C4207CC91561BE0A56A2FF4B97E4308CD",
|
2342 |
|
|
INIT_17 => X"32F9BF854B11D79D6329EFB47A4006CC92581DE3A96E34FAC0854B10D69C6127",
|
2343 |
|
|
INIT_18 => X"652CF2B980460DD49A6127EEB47B4108CE955B21E8AE743B01C78E541AE0A66C",
|
2344 |
|
|
INIT_19 => X"844B12DAA16830F7BE854C13DAA26930F7BE854C13DAA1682EF5BC834A11D89E",
|
2345 |
|
|
INIT_1A => X"8F571FE6AE763E06CE965D25EDB57C440CD39B622AF2B9814810D79F662EF5BC",
|
2346 |
|
|
INIT_1B => X"864F17E0A8713902CA925B23ECB47C440DD59D662EF6BE864E16DFA76F37FFC7",
|
2347 |
|
|
INIT_1C => X"6A33FCC58E5720EAB37C450ED7A06831FAC38C551EE6AF78410AD29B642CF5BD",
|
2348 |
|
|
INIT_1D => X"3A04CD97612AF4BE88511BE4AE78410BD49E6730FAC38D5620E9B27C450ED7A0",
|
2349 |
|
|
INIT_1E => X"F6C18B5520EAB47F4913DDA8723C06D09A642EF9C38D5721EBB57E4812DCA670",
|
2350 |
|
|
INIT_1F => X"9F6A3500CB96612CF7C28C5722EDB8824D18E2AD78420DD8A26D3702CC97612C",
|
2351 |
|
|
INIT_20 => X"3500CC97632EFAC6915C28F3BF8A5621ECB8834E1AE5B07B4612DDA8733E09D4",
|
2352 |
|
|
INIT_21 => X"B7834F1BE7B4804C18E4B07C4814E0AC784410DCA8743F0BD7A36E3A06D29D69",
|
2353 |
|
|
INIT_22 => X"25F2BF8C5825F2BF8B5825F1BE8B5724F0BD895622EFBB885420EDB986521EEA",
|
2354 |
|
|
INIT_23 => X"804E1BE9B684511EECB9865320EEBB885522F0BD8A5724F1BE8B5825F2BF8C58",
|
2355 |
|
|
INIT_24 => X"C896643200CE9C6A3806D4A2703E0BD9A7754210DEAB794714E2B07D4A18E6B3",
|
2356 |
|
|
INIT_25 => X"FDCC9A693806D5A372400FDDAC7A4817E5B482501EEDBB895826F4C2905E2CFA",
|
2357 |
|
|
INIT_26 => X"1FEEBD8C5C2BFAC998673605D4A3724110DFAE7D4C1BEAB8875625F4C291602E",
|
2358 |
|
|
INIT_27 => X"2DFDCC9C6C3C0CDBAB7B4A1AEAB9895828F8C797663605D4A4734312E1B1804F",
|
2359 |
|
|
INIT_28 => X"28F8C9996A3A0ADBAB7B4C1CECBC8C5D2DFDCD9D6D3D0DDDAD7D4D1DEDBD8D5D",
|
2360 |
|
|
INIT_29 => X"10E1B2835425F6C798693A0ADBAC7D4E1EEFC090613202D3A4744516E6B68758",
|
2361 |
|
|
INIT_2A => X"E5B6885A2BFDCEA0724314E6B7895A2CFDCEA0714213E4B6875829FACC9D6E3F",
|
2362 |
|
|
INIT_2B => X"A7794B1DF0C29466380ADCAE805224F6C89A6C3E10E2B4855729FBCC9E704213",
|
2363 |
|
|
INIT_2C => X"5628FBCEA1744619ECBE91643609DCAE815326F8CB9D704214E7B98B5E3002D4",
|
2364 |
|
|
INIT_2D => X"F2C5986C3F12E6B98C603306D9AD805326F9CC9F724618ECBE9164370ADDB083",
|
2365 |
|
|
INIT_2E => X"7B4F23F7CB9E72461AEEC2966A3D11E5B88C603407DBAE825629FDD0A4774B1E",
|
2366 |
|
|
INIT_2F => X"F1C69A6F4318ECC1956A3E12E7BB9064380CE1B5895E3206DAAE82562AFFD3A7",
|
2367 |
|
|
INIT_30 => X"542AFFD4A97E5328FDD2A77C5126FBD0A57A4F24F8CDA2774C20F5CA9E73481C",
|
2368 |
|
|
INIT_31 => X"A57B5026FCD2A77D5228FED3A97E5429FFD4AA7F552A00D5AA80552AFFD5AA7F",
|
2369 |
|
|
INIT_32 => X"E3B98F663C12E8BF956B4118EEC49A70461CF2C89E744A20F6CCA2784E24F9CF",
|
2370 |
|
|
INIT_33 => X"0EE5BC92694017EEC59C724920F6CDA47B5128FED5AC82592F06DCB38960360C",
|
2371 |
|
|
INIT_34 => X"26FED5AD845C330AE2B991683F16EEC59C744B22F9D0A77E562D04DBB2896037",
|
2372 |
|
|
INIT_35 => X"2C04DCB48C643C14ECC49C744C24FCD4AC835B330BE2BA92694119F0C8A0774F",
|
2373 |
|
|
INIT_36 => X"1FF8D1A9825A330CE4BD956E461FF7D0A88059310AE2BA926B431BF3CCA47C54",
|
2374 |
|
|
INIT_37 => X"00D9B28C653E17F0CAA37C552E07E0B9926B441DF6CFA88059320BE4BC956E47",
|
2375 |
|
|
INIT_38 => X"CEA8825C350FE9C39C76502903DDB69069431CF6D0A9825C350FE8C19B744D27",
|
2376 |
|
|
INIT_39 => X"8A643F19F3CEA8825D3711EBC6A07A542E08E2BD97714B25FFD9B38D67401AF4",
|
2377 |
|
|
INIT_3A => X"330EE9C49F7A55300AE5C09B76502B06E1BC96714C2601DBB6906B4620FAD5AF",
|
2378 |
|
|
INIT_3B => X"CAA6815D3814EFCAA6815D3814EFCAA6815C3713EEC9A47F5A3611ECC7A27D58",
|
2379 |
|
|
INIT_3C => X"4E2B07E3BF9B77532F0BE7C39F7B57330EEAC6A27E5A3511EDC8A4805C3713EE",
|
2380 |
|
|
INIT_3D => X"C19D7A573310EDC9A6825F3C18F4D1AD8A66431FFBD8B4906D492502DEBA9672",
|
2381 |
|
|
INIT_3E => X"20FEDBB89673502D0AE7C4A27F5C3916F3D0AD8A674420FEDAB794714E2A07E4",
|
2382 |
|
|
INIT_3F => X"6E4C2A08E6C3A17F5C3A18F6D3B18E6C4A2705E2C09D7B583613F0CEAB896643",
|
2383 |
|
|
INIT_40 => X"AA8866452302E0BE9C7B593716F4D2B08E6C4A2807E5C3A17F5D3B19F7D4B290",
|
2384 |
|
|
INIT_41 => X"D3B291704F2E0DECCAA98867462403E2C09F7E5D3B1AF8D7B6947351300EEDCB",
|
2385 |
|
|
INIT_42 => X"EACAA98968482707E6C5A58464432202E1C09F7E5E3D1CFBDABA9978573615F4",
|
2386 |
|
|
INIT_43 => X"EFCFAF8F70503010F0D0B08F6F4F2F0FEFCFAF8E6E4E2E0DEDCDAC8C6C4B2B0A",
|
2387 |
|
|
INIT_44 => X"E2C3A48465452607E7C8A889694A2A0AEBCBAC8C6C4D2D0DEECEAE8E6E4F2F0F",
|
2388 |
|
|
INIT_45 => X"C3A4866748290AECCDAE8F70513213F4D5B69778593A1AFBDCBD9E7E5F402102",
|
2389 |
|
|
INIT_46 => X"9274563819FBDDBEA08263452708EACBAD8E70513314F6D7B99A7B5D3E1F01E2",
|
2390 |
|
|
INIT_47 => X"4F3214F6D9BB9D7F62442608EACDAF9173553719FBDDBFA1836547290BEDCEB0",
|
2391 |
|
|
INIT_48 => X"FADDC0A386694C2E11F4D7BA9C7F6244270AECCFB29477593C1E01E3C6A88A6D",
|
2392 |
|
|
INIT_49 => X"94775B3E2205E8CCAF9276593C2003E6C9AC907356391CFFE2C6A88C6F523418",
|
2393 |
|
|
INIT_4A => X"1BFFE3C7AB8F73573B1F03E7CAAE92765A3D2105E9CCB094775B3E2206E9CDB0",
|
2394 |
|
|
INIT_4B => X"91755A3F2308ECD1B59A7E62472B10F4D8BDA185694E3216FADEC3A78B6F5337",
|
2395 |
|
|
INIT_4C => X"F5DABFA4896E53381D02E7CCB1967B60452A0FF4D8BDA2876C50351AFEE3C8AC",
|
2396 |
|
|
INIT_4D => X"472D12F8DEC3A98E745A3F250AF0D5BBA0866B50361B00E6CBB0967B60452A10",
|
2397 |
|
|
INIT_4E => X"886E543A2007EDD3B99F856B51371D03E9CFB59B81674D3319FFE4CAB0967C61",
|
2398 |
|
|
INIT_4F => X"B69D846B51381F06ECD3BAA0876D543B2108EED5BBA2886E553B2208EED5BBA1",
|
2399 |
|
|
INIT_50 => X"D4BBA28A71583F270EF5DCC4AB927960472E15FCE3CAB1987F664D341B02E9D0",
|
2400 |
|
|
INIT_51 => X"DFC7AF977F674E361E06EED5BDA58C745C432B12FAE2C9B19880674F361D05EC",
|
2401 |
|
|
INIT_52 => X"D9C2AA937B634C341C05EDD5BEA68E765E472F17FFE7CFB79F87705840270FF7",
|
2402 |
|
|
INIT_53 => X"C2AB947D664F38210AF2DBC4AD967E675039210AF3DBC4AD957E664F372008F1",
|
2403 |
|
|
INIT_54 => X"99836C563F2912FCE5CEB8A18A745D46301902ECD5BEA79079634C351E07F0D9",
|
2404 |
|
|
INIT_55 => X"5F49331D07F1DBC5AF99836D57412A14FEE8D2BCA58F79624C362009F3DCC6B0",
|
2405 |
|
|
INIT_56 => X"13FEE8D3BEA8937D68523D2712FCE6D1BBA6907A644F39230EF8E2CCB6A08B75",
|
2406 |
|
|
INIT_57 => X"B6A18C78634E39240FFAE5D0BBA6917C67523D2812FDE8D3BEA8937E68533E29",
|
2407 |
|
|
INIT_58 => X"48341F0BF6E2CEB9A5917C68533F2A1601EDD8C3AF9A86715C48331E09F5E0CB",
|
2408 |
|
|
INIT_59 => X"C8B4A18D7965513E2A1602EEDAC6B29E8A76624E3A2612FEEAD5C1AD9985705C",
|
2409 |
|
|
INIT_5A => X"372411FEEAD7C4B09D8A7663503C291502EEDBC7B4A08D7966523E2B1703F0DC",
|
2410 |
|
|
INIT_5B => X"9582705D4A382512FFECDAC7B4A18E7B6855422F1C09F6E3D0BDAA9784715E4A",
|
2411 |
|
|
INIT_5C => X"E2D0BDAB99877562503E2C1907F5E2D0BEAB998674614F3C2A1705F2E0CDBAA8",
|
2412 |
|
|
INIT_5D => X"1D0CFAE8D7C5B3A2907E6C5B4937251302F0DECCBAA8968472604E3C2A1806F4",
|
2413 |
|
|
INIT_5E => X"4837261403F2E1D0BFAD9C8B7A68574635231200EFDECCBBA99886756352402F",
|
2414 |
|
|
INIT_5F => X"6150402F1F0EFEEDDCCCBBAA99897867564635241302F1E0D0BFAE9D8C7B6A59",
|
2415 |
|
|
INIT_60 => X"69594939291909F9E9D9C8B8A898887767574736261605F5E5D4C4B3A3928271",
|
2416 |
|
|
INIT_61 => X"60514232221303F4E4D5C5B5A696867767574738281808F8E9D9C9B9A9998979",
|
2417 |
|
|
INIT_62 => X"4738291A0BFCEDDECFC0B1A19283746556463728190AFAEBDCCCBDAE9E8F7F70",
|
2418 |
|
|
INIT_63 => X"1C0EFFF1E2D4C5B7A89A8B7D6E5F514234251607F9EADBCCBEAFA09182736556",
|
2419 |
|
|
INIT_64 => X"E0D3C5B7A99B8D7F71635547392B1D0E00F2E4D6C8B9AB9D8F8072645647392A",
|
2420 |
|
|
INIT_65 => X"9487796C5E514436291B0E00F3E5D8CABCAFA19386786A5D4F413326180AFCEE",
|
2421 |
|
|
INIT_66 => X"372A1D1003F6E9DCD0C3B6A99C8F8274675A4D403326190BFEF1E4D6C9BCAFA1",
|
2422 |
|
|
INIT_67 => X"C9BCB0A4978B7E7266594D4034271B0E02F5E9DCCFC3B6A99D9083776A5D5043",
|
2423 |
|
|
INIT_68 => X"4A3E32261A0F03F7EBDFD3C7BBAFA3978B7F73675B4F43372A1E1206FAEDE1D5",
|
2424 |
|
|
INIT_69 => X"BAAFA3988D82766B5F54493D32261B0F04F8EDE1D6CABFB3A79C9084796D6155",
|
2425 |
|
|
INIT_6A => X"1A0F04F9EFE4D9CEC3B8AEA3988D82776C61564B40352A1F1308FDF2E7DCD0C5",
|
2426 |
|
|
INIT_6B => X"695E544A40352B21160C02F7EDE2D8CEC3B9AEA4998F847A6F645A4F443A2F24",
|
2427 |
|
|
INIT_6C => X"A79D948A80766C63594F453B31281E140A00F6ECE2D8CEC4BAB0A69B91877D73",
|
2428 |
|
|
INIT_6D => X"D5CBC2B9B0A79D948B81786F655C534940362D231A1007FDF4EAE1D7CEC4BAB1",
|
2429 |
|
|
INIT_6E => X"F2E9E0D8CFC6BEB5ACA39A928980776E655C534A413830261D140B02F9F0E7DE",
|
2430 |
|
|
INIT_6F => X"FEF6EEE6DED5CDC5BDB4ACA49C938B827A7269615850473F362E251D140C03FA",
|
2431 |
|
|
INIT_70 => X"FAF3EBE3DCD4CCC5BDB5ADA69E968E867E776F675F574F473F372F271F170F06",
|
2432 |
|
|
INIT_71 => X"E6DFD8D1C9C2BBB4ADA59E979088817A726B635C554D463E372F282019110A02",
|
2433 |
|
|
INIT_72 => X"C1BBB4ADA7A099938C857E78716A635C564F48413A332C251E17100902FBF4ED",
|
2434 |
|
|
INIT_73 => X"8C86807A736D67615B544E48423B352F29221C150F0902FCF5EFE8E2DBD5CEC8",
|
2435 |
|
|
INIT_74 => X"46413B35302A241F19130E0802FCF7F1EBE5DFDAD4CEC8C2BCB6B0AAA49E9892",
|
2436 |
|
|
INIT_75 => X"F0EBE6E1DCD7D2CCC7C2BDB8B2ADA8A39D98938D88827D78726D67625C57514C",
|
2437 |
|
|
INIT_76 => X"8A85817C78736E6A65605C57524D49443F3A35312C27221D18130E0904FFFAF5",
|
2438 |
|
|
INIT_77 => X"130F0B0703FFFBF7F2EEEAE6E2DDD9D5D1CCC8C4BFBBB7B2AEA9A5A09C97938E",
|
2439 |
|
|
INIT_78 => X"8C8985827E7B7773706C6865615D5956524E4A46433F3B37332F2B27231F1B17",
|
2440 |
|
|
INIT_79 => X"F5F2EFECE9E6E3E0DDD9D6D3D0CDC9C6C3C0BCB9B6B2AFACA8A5A19E9A979390",
|
2441 |
|
|
INIT_7A => X"4E4C494644413F3C393734312F2C292624211E1B181613100D0A070401FEFBF8",
|
2442 |
|
|
INIT_7B => X"979593918E8C8A88868482807D7B79777472706D6B696664625F5D5A58565351",
|
2443 |
|
|
INIT_7C => X"CFCECCCAC9C7C6C4C2C1BFBDBCBAB8B7B5B3B1B0AEACAAA8A6A4A2A19F9D9B99",
|
2444 |
|
|
INIT_7D => X"F7F6F5F4F3F2F1F0EFEEEDEBEAE9E8E7E5E4E3E1E0DFDDDCDBD9D8D6D5D4D2D1",
|
2445 |
|
|
INITP_0E => X"F800000000000007FFFFFFFFFFF80000000001FFFFFFFFF800000000FFFFFFFF",
|
2446 |
|
|
INIT_FILE => "NONE",
|
2447 |
|
|
RAM_EXTENSION_A => "NONE",
|
2448 |
|
|
RAM_EXTENSION_B => "NONE",
|
2449 |
|
|
READ_WIDTH_A => 9,
|
2450 |
|
|
READ_WIDTH_B => 9,
|
2451 |
|
|
SIM_COLLISION_CHECK => "ALL",
|
2452 |
|
|
SIM_MODE => "SAFE",
|
2453 |
|
|
INIT_A => X"000000000",
|
2454 |
|
|
INIT_B => X"000000000",
|
2455 |
|
|
WRITE_MODE_A => "WRITE_FIRST",
|
2456 |
|
|
WRITE_MODE_B => "WRITE_FIRST",
|
2457 |
|
|
WRITE_WIDTH_A => 9,
|
2458 |
|
|
WRITE_WIDTH_B => 9,
|
2459 |
|
|
INITP_0F => X"FFFFFFFFFFFFFF0000000000000000000000000000000007FFFFFFFFFFFFFFFF"
|
2460 |
|
|
)
|
2461 |
|
|
port map (
|
2462 |
|
|
ENAU => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_3_cmp_eq0000,
|
2463 |
|
|
ENAL => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_3_cmp_eq0000,
|
2464 |
|
|
ENBU => BU2_doutb(0),
|
2465 |
|
|
ENBL => BU2_doutb(0),
|
2466 |
|
|
SSRAU => BU2_doutb(0),
|
2467 |
|
|
SSRAL => BU2_doutb(0),
|
2468 |
|
|
SSRBU => BU2_doutb(0),
|
2469 |
|
|
SSRBL => BU2_doutb(0),
|
2470 |
|
|
CLKAU => clka,
|
2471 |
|
|
CLKAL => clka,
|
2472 |
|
|
CLKBU => BU2_doutb(0),
|
2473 |
|
|
CLKBL => BU2_doutb(0),
|
2474 |
|
|
REGCLKAU => clka,
|
2475 |
|
|
REGCLKAL => clka,
|
2476 |
|
|
REGCLKBU => BU2_doutb(0),
|
2477 |
|
|
REGCLKBL => BU2_doutb(0),
|
2478 |
|
|
REGCEAU => BU2_doutb(0),
|
2479 |
|
|
REGCEAL => BU2_doutb(0),
|
2480 |
|
|
REGCEBU => BU2_doutb(0),
|
2481 |
|
|
REGCEBL => BU2_doutb(0),
|
2482 |
|
|
CASCADEINLATA => BU2_doutb(0),
|
2483 |
|
|
CASCADEINLATB => BU2_doutb(0),
|
2484 |
|
|
CASCADEINREGA => BU2_doutb(0),
|
2485 |
|
|
CASCADEINREGB => BU2_doutb(0),
|
2486 |
|
|
CASCADEOUTLATA => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATA_UNCONNECTED,
|
2487 |
|
|
CASCADEOUTLATB => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATB_UNCONNECTED,
|
2488 |
|
|
CASCADEOUTREGA => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGA_UNCONNECTED,
|
2489 |
|
|
CASCADEOUTREGB => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGB_UNCONNECTED,
|
2490 |
|
|
DIA(31) => BU2_doutb(0),
|
2491 |
|
|
DIA(30) => BU2_doutb(0),
|
2492 |
|
|
DIA(29) => BU2_doutb(0),
|
2493 |
|
|
DIA(28) => BU2_doutb(0),
|
2494 |
|
|
DIA(27) => BU2_doutb(0),
|
2495 |
|
|
DIA(26) => BU2_doutb(0),
|
2496 |
|
|
DIA(25) => BU2_doutb(0),
|
2497 |
|
|
DIA(24) => BU2_doutb(0),
|
2498 |
|
|
DIA(23) => BU2_doutb(0),
|
2499 |
|
|
DIA(22) => BU2_doutb(0),
|
2500 |
|
|
DIA(21) => BU2_doutb(0),
|
2501 |
|
|
DIA(20) => BU2_doutb(0),
|
2502 |
|
|
DIA(19) => BU2_doutb(0),
|
2503 |
|
|
DIA(18) => BU2_doutb(0),
|
2504 |
|
|
DIA(17) => BU2_doutb(0),
|
2505 |
|
|
DIA(16) => BU2_doutb(0),
|
2506 |
|
|
DIA(15) => BU2_doutb(0),
|
2507 |
|
|
DIA(14) => BU2_doutb(0),
|
2508 |
|
|
DIA(13) => BU2_doutb(0),
|
2509 |
|
|
DIA(12) => BU2_doutb(0),
|
2510 |
|
|
DIA(11) => BU2_doutb(0),
|
2511 |
|
|
DIA(10) => BU2_doutb(0),
|
2512 |
|
|
DIA(9) => BU2_doutb(0),
|
2513 |
|
|
DIA(8) => BU2_doutb(0),
|
2514 |
|
|
DIA(7) => BU2_doutb(0),
|
2515 |
|
|
DIA(6) => BU2_doutb(0),
|
2516 |
|
|
DIA(5) => BU2_doutb(0),
|
2517 |
|
|
DIA(4) => BU2_doutb(0),
|
2518 |
|
|
DIA(3) => BU2_doutb(0),
|
2519 |
|
|
DIA(2) => BU2_doutb(0),
|
2520 |
|
|
DIA(1) => BU2_doutb(0),
|
2521 |
|
|
DIA(0) => BU2_doutb(0),
|
2522 |
|
|
DIPA(3) => BU2_doutb(0),
|
2523 |
|
|
DIPA(2) => BU2_doutb(0),
|
2524 |
|
|
DIPA(1) => BU2_doutb(0),
|
2525 |
|
|
DIPA(0) => BU2_doutb(0),
|
2526 |
|
|
DIB(31) => BU2_doutb(0),
|
2527 |
|
|
DIB(30) => BU2_doutb(0),
|
2528 |
|
|
DIB(29) => BU2_doutb(0),
|
2529 |
|
|
DIB(28) => BU2_doutb(0),
|
2530 |
|
|
DIB(27) => BU2_doutb(0),
|
2531 |
|
|
DIB(26) => BU2_doutb(0),
|
2532 |
|
|
DIB(25) => BU2_doutb(0),
|
2533 |
|
|
DIB(24) => BU2_doutb(0),
|
2534 |
|
|
DIB(23) => BU2_doutb(0),
|
2535 |
|
|
DIB(22) => BU2_doutb(0),
|
2536 |
|
|
DIB(21) => BU2_doutb(0),
|
2537 |
|
|
DIB(20) => BU2_doutb(0),
|
2538 |
|
|
DIB(19) => BU2_doutb(0),
|
2539 |
|
|
DIB(18) => BU2_doutb(0),
|
2540 |
|
|
DIB(17) => BU2_doutb(0),
|
2541 |
|
|
DIB(16) => BU2_doutb(0),
|
2542 |
|
|
DIB(15) => BU2_doutb(0),
|
2543 |
|
|
DIB(14) => BU2_doutb(0),
|
2544 |
|
|
DIB(13) => BU2_doutb(0),
|
2545 |
|
|
DIB(12) => BU2_doutb(0),
|
2546 |
|
|
DIB(11) => BU2_doutb(0),
|
2547 |
|
|
DIB(10) => BU2_doutb(0),
|
2548 |
|
|
DIB(9) => BU2_doutb(0),
|
2549 |
|
|
DIB(8) => BU2_doutb(0),
|
2550 |
|
|
DIB(7) => BU2_doutb(0),
|
2551 |
|
|
DIB(6) => BU2_doutb(0),
|
2552 |
|
|
DIB(5) => BU2_doutb(0),
|
2553 |
|
|
DIB(4) => BU2_doutb(0),
|
2554 |
|
|
DIB(3) => BU2_doutb(0),
|
2555 |
|
|
DIB(2) => BU2_doutb(0),
|
2556 |
|
|
DIB(1) => BU2_doutb(0),
|
2557 |
|
|
DIB(0) => BU2_doutb(0),
|
2558 |
|
|
DIPB(3) => BU2_doutb(0),
|
2559 |
|
|
DIPB(2) => BU2_doutb(0),
|
2560 |
|
|
DIPB(1) => BU2_doutb(0),
|
2561 |
|
|
DIPB(0) => BU2_doutb(0),
|
2562 |
|
|
ADDRAL(15) => BU2_doutb(0),
|
2563 |
|
|
ADDRAL(14) => addra_2(11),
|
2564 |
|
|
ADDRAL(13) => addra_2(10),
|
2565 |
|
|
ADDRAL(12) => addra_2(9),
|
2566 |
|
|
ADDRAL(11) => addra_2(8),
|
2567 |
|
|
ADDRAL(10) => addra_2(7),
|
2568 |
|
|
ADDRAL(9) => addra_2(6),
|
2569 |
|
|
ADDRAL(8) => addra_2(5),
|
2570 |
|
|
ADDRAL(7) => addra_2(4),
|
2571 |
|
|
ADDRAL(6) => addra_2(3),
|
2572 |
|
|
ADDRAL(5) => addra_2(2),
|
2573 |
|
|
ADDRAL(4) => addra_2(1),
|
2574 |
|
|
ADDRAL(3) => addra_2(0),
|
2575 |
|
|
ADDRAL(2) => BU2_doutb(0),
|
2576 |
|
|
ADDRAL(1) => BU2_doutb(0),
|
2577 |
|
|
ADDRAL(0) => BU2_doutb(0),
|
2578 |
|
|
ADDRAU(14) => addra_2(11),
|
2579 |
|
|
ADDRAU(13) => addra_2(10),
|
2580 |
|
|
ADDRAU(12) => addra_2(9),
|
2581 |
|
|
ADDRAU(11) => addra_2(8),
|
2582 |
|
|
ADDRAU(10) => addra_2(7),
|
2583 |
|
|
ADDRAU(9) => addra_2(6),
|
2584 |
|
|
ADDRAU(8) => addra_2(5),
|
2585 |
|
|
ADDRAU(7) => addra_2(4),
|
2586 |
|
|
ADDRAU(6) => addra_2(3),
|
2587 |
|
|
ADDRAU(5) => addra_2(2),
|
2588 |
|
|
ADDRAU(4) => addra_2(1),
|
2589 |
|
|
ADDRAU(3) => addra_2(0),
|
2590 |
|
|
ADDRAU(2) => BU2_doutb(0),
|
2591 |
|
|
ADDRAU(1) => BU2_doutb(0),
|
2592 |
|
|
ADDRAU(0) => BU2_doutb(0),
|
2593 |
|
|
ADDRBL(15) => BU2_doutb(0),
|
2594 |
|
|
ADDRBL(14) => BU2_doutb(0),
|
2595 |
|
|
ADDRBL(13) => BU2_doutb(0),
|
2596 |
|
|
ADDRBL(12) => BU2_doutb(0),
|
2597 |
|
|
ADDRBL(11) => BU2_doutb(0),
|
2598 |
|
|
ADDRBL(10) => BU2_doutb(0),
|
2599 |
|
|
ADDRBL(9) => BU2_doutb(0),
|
2600 |
|
|
ADDRBL(8) => BU2_doutb(0),
|
2601 |
|
|
ADDRBL(7) => BU2_doutb(0),
|
2602 |
|
|
ADDRBL(6) => BU2_doutb(0),
|
2603 |
|
|
ADDRBL(5) => BU2_doutb(0),
|
2604 |
|
|
ADDRBL(4) => BU2_doutb(0),
|
2605 |
|
|
ADDRBL(3) => BU2_doutb(0),
|
2606 |
|
|
ADDRBL(2) => BU2_doutb(0),
|
2607 |
|
|
ADDRBL(1) => BU2_doutb(0),
|
2608 |
|
|
ADDRBL(0) => BU2_doutb(0),
|
2609 |
|
|
ADDRBU(14) => BU2_doutb(0),
|
2610 |
|
|
ADDRBU(13) => BU2_doutb(0),
|
2611 |
|
|
ADDRBU(12) => BU2_doutb(0),
|
2612 |
|
|
ADDRBU(11) => BU2_doutb(0),
|
2613 |
|
|
ADDRBU(10) => BU2_doutb(0),
|
2614 |
|
|
ADDRBU(9) => BU2_doutb(0),
|
2615 |
|
|
ADDRBU(8) => BU2_doutb(0),
|
2616 |
|
|
ADDRBU(7) => BU2_doutb(0),
|
2617 |
|
|
ADDRBU(6) => BU2_doutb(0),
|
2618 |
|
|
ADDRBU(5) => BU2_doutb(0),
|
2619 |
|
|
ADDRBU(4) => BU2_doutb(0),
|
2620 |
|
|
ADDRBU(3) => BU2_doutb(0),
|
2621 |
|
|
ADDRBU(2) => BU2_doutb(0),
|
2622 |
|
|
ADDRBU(1) => BU2_doutb(0),
|
2623 |
|
|
ADDRBU(0) => BU2_doutb(0),
|
2624 |
|
|
WEAU(3) => BU2_doutb(0),
|
2625 |
|
|
WEAU(2) => BU2_doutb(0),
|
2626 |
|
|
WEAU(1) => BU2_doutb(0),
|
2627 |
|
|
WEAU(0) => BU2_doutb(0),
|
2628 |
|
|
WEAL(3) => BU2_doutb(0),
|
2629 |
|
|
WEAL(2) => BU2_doutb(0),
|
2630 |
|
|
WEAL(1) => BU2_doutb(0),
|
2631 |
|
|
WEAL(0) => BU2_doutb(0),
|
2632 |
|
|
WEBU(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_7_UNCONNECTED,
|
2633 |
|
|
WEBU(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_6_UNCONNECTED,
|
2634 |
|
|
WEBU(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_5_UNCONNECTED,
|
2635 |
|
|
WEBU(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_4_UNCONNECTED,
|
2636 |
|
|
WEBU(3) => BU2_doutb(0),
|
2637 |
|
|
WEBU(2) => BU2_doutb(0),
|
2638 |
|
|
WEBU(1) => BU2_doutb(0),
|
2639 |
|
|
WEBU(0) => BU2_doutb(0),
|
2640 |
|
|
WEBL(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_7_UNCONNECTED,
|
2641 |
|
|
WEBL(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_6_UNCONNECTED,
|
2642 |
|
|
WEBL(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_5_UNCONNECTED,
|
2643 |
|
|
WEBL(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_4_UNCONNECTED,
|
2644 |
|
|
WEBL(3) => BU2_doutb(0),
|
2645 |
|
|
WEBL(2) => BU2_doutb(0),
|
2646 |
|
|
WEBL(1) => BU2_doutb(0),
|
2647 |
|
|
WEBL(0) => BU2_doutb(0),
|
2648 |
|
|
DOA(31) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_31_UNCONNECTED,
|
2649 |
|
|
DOA(30) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_30_UNCONNECTED,
|
2650 |
|
|
DOA(29) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_29_UNCONNECTED,
|
2651 |
|
|
DOA(28) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_28_UNCONNECTED,
|
2652 |
|
|
DOA(27) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_27_UNCONNECTED,
|
2653 |
|
|
DOA(26) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_26_UNCONNECTED,
|
2654 |
|
|
DOA(25) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_25_UNCONNECTED,
|
2655 |
|
|
DOA(24) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_24_UNCONNECTED,
|
2656 |
|
|
DOA(23) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_23_UNCONNECTED,
|
2657 |
|
|
DOA(22) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_22_UNCONNECTED,
|
2658 |
|
|
DOA(21) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_21_UNCONNECTED,
|
2659 |
|
|
DOA(20) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_20_UNCONNECTED,
|
2660 |
|
|
DOA(19) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_19_UNCONNECTED,
|
2661 |
|
|
DOA(18) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_18_UNCONNECTED,
|
2662 |
|
|
DOA(17) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_17_UNCONNECTED,
|
2663 |
|
|
DOA(16) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_16_UNCONNECTED,
|
2664 |
|
|
DOA(15) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_15_UNCONNECTED,
|
2665 |
|
|
DOA(14) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_14_UNCONNECTED,
|
2666 |
|
|
DOA(13) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_13_UNCONNECTED,
|
2667 |
|
|
DOA(12) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_12_UNCONNECTED,
|
2668 |
|
|
DOA(11) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_11_UNCONNECTED,
|
2669 |
|
|
DOA(10) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_10_UNCONNECTED,
|
2670 |
|
|
DOA(9) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_9_UNCONNECTED,
|
2671 |
|
|
DOA(8) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_8_UNCONNECTED,
|
2672 |
|
|
DOA(7) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta2(7),
|
2673 |
|
|
DOA(6) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta2(6),
|
2674 |
|
|
DOA(5) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta2(5),
|
2675 |
|
|
DOA(4) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta2(4),
|
2676 |
|
|
DOA(3) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta2(3),
|
2677 |
|
|
DOA(2) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta2(2),
|
2678 |
|
|
DOA(1) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta2(1),
|
2679 |
|
|
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta2(0),
|
2680 |
|
|
DOPA(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_3_UNCONNECTED,
|
2681 |
|
|
DOPA(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_2_UNCONNECTED,
|
2682 |
|
|
DOPA(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_1_UNCONNECTED,
|
2683 |
|
|
DOPA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta2(8),
|
2684 |
|
|
DOB(31) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_31_UNCONNECTED,
|
2685 |
|
|
DOB(30) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_30_UNCONNECTED,
|
2686 |
|
|
DOB(29) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_29_UNCONNECTED,
|
2687 |
|
|
DOB(28) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_28_UNCONNECTED,
|
2688 |
|
|
DOB(27) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_27_UNCONNECTED,
|
2689 |
|
|
DOB(26) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_26_UNCONNECTED,
|
2690 |
|
|
DOB(25) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_25_UNCONNECTED,
|
2691 |
|
|
DOB(24) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_24_UNCONNECTED,
|
2692 |
|
|
DOB(23) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_23_UNCONNECTED,
|
2693 |
|
|
DOB(22) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_22_UNCONNECTED,
|
2694 |
|
|
DOB(21) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_21_UNCONNECTED,
|
2695 |
|
|
DOB(20) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_20_UNCONNECTED,
|
2696 |
|
|
DOB(19) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_19_UNCONNECTED,
|
2697 |
|
|
DOB(18) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_18_UNCONNECTED,
|
2698 |
|
|
DOB(17) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_17_UNCONNECTED,
|
2699 |
|
|
DOB(16) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_16_UNCONNECTED,
|
2700 |
|
|
DOB(15) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_15_UNCONNECTED,
|
2701 |
|
|
DOB(14) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_14_UNCONNECTED,
|
2702 |
|
|
DOB(13) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_13_UNCONNECTED,
|
2703 |
|
|
DOB(12) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_12_UNCONNECTED,
|
2704 |
|
|
DOB(11) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_11_UNCONNECTED,
|
2705 |
|
|
DOB(10) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_10_UNCONNECTED,
|
2706 |
|
|
DOB(9) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_9_UNCONNECTED,
|
2707 |
|
|
DOB(8) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_8_UNCONNECTED,
|
2708 |
|
|
DOB(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_7_UNCONNECTED,
|
2709 |
|
|
DOB(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_6_UNCONNECTED,
|
2710 |
|
|
DOB(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_5_UNCONNECTED,
|
2711 |
|
|
DOB(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_4_UNCONNECTED,
|
2712 |
|
|
DOB(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_3_UNCONNECTED,
|
2713 |
|
|
DOB(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_2_UNCONNECTED,
|
2714 |
|
|
DOB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_1_UNCONNECTED,
|
2715 |
|
|
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_0_UNCONNECTED,
|
2716 |
|
|
DOPB(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_3_UNCONNECTED,
|
2717 |
|
|
DOPB(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_2_UNCONNECTED,
|
2718 |
|
|
DOPB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_1_UNCONNECTED,
|
2719 |
|
|
DOPB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_0_UNCONNECTED
|
2720 |
|
|
);
|
2721 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP : RAMB36_EXP
|
2722 |
|
|
generic map(
|
2723 |
|
|
DOA_REG => 0,
|
2724 |
|
|
DOB_REG => 0,
|
2725 |
|
|
INIT_7E => X"6F69625C564F49423C362F29221C150F0902FCF5EFE9E2DCD5CFC8C2BCB5AFA8",
|
2726 |
|
|
INIT_7F => X"3C362F29231C160F0903FCF6EFE9E3DCD6CFC9C3BCB6AFA9A29C968F89827C76",
|
2727 |
|
|
INITP_00 => X"33333333199999999999999999999999AAAAAAAAAAAAAAAA00000000FFFFFFFF",
|
2728 |
|
|
INITP_01 => X"F0F8787878783C3C3C3C3E1E1E1E1E1F0F0F0F0F0F07878787878787C3C3C3C3",
|
2729 |
|
|
INITP_02 => X"FE01FF00FF007F807FC03FC01FE01FF00FF007F807F803FC03FE01FE01FF00F0",
|
2730 |
|
|
INITP_03 => X"7FC03FE01FF00FF807FC03FE01FE00FF007F803FC01FE01FF00FF807F803FC03",
|
2731 |
|
|
INITP_04 => X"00003FFFE0000FFFF80001FFFF00007FFFC0001FFFF00007FFFC0001FF00FF80",
|
2732 |
|
|
INITP_05 => X"FFF80001FFFF00003FFFE00007FFFC0001FFFF80003FFFE00007FFFC0001FFFF",
|
2733 |
|
|
INITP_06 => X"07FFFE00007FFFC0000FFFFC0001FFFF80001FFFF00003FFFE00007FFFC0000F",
|
2734 |
|
|
INITP_07 => X"001FFFF80001FFFF80001FFFF80001FFFF00003FFFF00003FFFF00003FFFE000",
|
2735 |
|
|
INITP_08 => X"FFF8000000003FFFFFFFFC000000003FFFF80001FFFF80001FFFF80001FFFF80",
|
2736 |
|
|
INITP_09 => X"000FFFFFFFFF8000000003FFFFFFFFE000000000FFFFFFFFF0000000007FFFFF",
|
2737 |
|
|
INITP_0A => X"FF0000000007FFFFFFFFE000000000FFFFFFFFF8000000003FFFFFFFFE000000",
|
2738 |
|
|
INITP_0B => X"FFFFFFFFF8000000001FFFFFFFFF8000000001FFFFFFFFF8000000003FFFFFFF",
|
2739 |
|
|
INITP_0C => X"0000003FFFFFFFFF8000000001FFFFFFFFF8000000001FFFFFFFFF8000000000",
|
2740 |
|
|
INITP_0D => X"FFE0000000003FFFFFFFFF8000000000FFFFFFFFFC0000000007FFFFFFFFF000",
|
2741 |
|
|
SRVAL_A => X"000000000",
|
2742 |
|
|
SRVAL_B => X"000000000",
|
2743 |
|
|
INIT_00 => X"E1E2E4E6E8EAEBEDEEF0F1F2F4F5F6F7F0F2F4F6F7F9FAFBF8FAFCFDFCFEFEFF",
|
2744 |
|
|
INIT_01 => X"C1C3C5C6C8CACCCECFD1D3D5D6D8D9DBDCDEDFE1E2E3E5E6E7E8EAEBECEDEEEF",
|
2745 |
|
|
INIT_02 => X"393A3B3D3E40414344454748494B4C4D4E5051525354555758595A5B5C5D5E5F",
|
2746 |
|
|
INIT_03 => X"01030507090B0D0F10121416181A1B1D1F2122242627292B2C2E2F3132343637",
|
2747 |
|
|
INIT_04 => X"5DDE5FE062E364E566E869EA6BEC6DEE70F172F374F576F778F97AFB7CFD7EFF",
|
2748 |
|
|
INIT_05 => X"31B334B637B93ABC3DBE40C143C445C748C94BCC4DCF50D153D455D658D95ADC",
|
2749 |
|
|
INIT_06 => X"FE8002830587088A0C8D0F9112941697199A1C9D1FA122A425A728AA2BAD2EB0",
|
2750 |
|
|
INIT_07 => X"C345C749CB4DCF51D355D658DA5CDE60E263E567E96BED6EF072F475F779FB7C",
|
2751 |
|
|
INIT_08 => X"4001C2834405C688490ACB8C4D0ECF905112D3945516D798591ADB9C5D1EBF41",
|
2752 |
|
|
INIT_09 => X"1BDC9D5E20E1A26324E6A76829EAAB6D2EEFB07132F4B57637F8B97A3BFDBE7F",
|
2753 |
|
|
INIT_0A => X"F2B37436F7B87A3BFCBE7F4001C3844507C8894A0CCD8E5011D2935516D79859",
|
2754 |
|
|
INIT_0B => X"C5864809CA8C4D0FD0925315D697591ADC9D5E20E1A36425E7A8692BECAE6F30",
|
2755 |
|
|
INIT_0C => X"945517D99A5C1DDFA06224E5A7682AEBAD6E30F1B37436F7B97A3CFDBF804203",
|
2756 |
|
|
INIT_0D => X"5F21E3A46628E9AB6D2FF0B27435F7B87A3CFDBF814204C687490ACC8E4F11D2",
|
2757 |
|
|
INIT_0E => X"27E9AB6C2EF0B27435F7B97B3DFEC0824405C7894B0CCE905213D597591ADC9E",
|
2758 |
|
|
INIT_0F => X"EBAD6F31F3B57638FABC7E4002C4864809CB8D4F11D3955618DA9C5E20E2A365",
|
2759 |
|
|
INIT_10 => X"D5B69778593A1BFCDDBE9F8061422304E5C6A788694A2B0CDB9D5F21E3A56729",
|
2760 |
|
|
INIT_11 => X"B39576573819FADBBC9D7E5F402102E4C5A68768492A0BECCDAE8F70513213F4",
|
2761 |
|
|
INIT_12 => X"9071523314F5D7B8997A5B3C1DFEE0C1A28364452607E8CAAB8C6D4E2F10F1D2",
|
2762 |
|
|
INIT_13 => X"6A4B2D0EEFD0B19374553617F9DABB9C7D5E402102E3C4A58768492A0BECCDAF",
|
2763 |
|
|
INIT_14 => X"432405E7C8A98A6C4D2E0FF1D2B39476573819FADCBD9E7F61422304E5C7A889",
|
2764 |
|
|
INIT_15 => X"1AFBDCBE9F8061432405E7C8A98B6C4D2E10F1D2B4957657391AFBDDBE9F8062",
|
2765 |
|
|
INIT_16 => X"EFD0B19374553718F9DBBC9E7F60422304E6C7A88A6B4C2E0FF0D2B394765738",
|
2766 |
|
|
INIT_17 => X"C2A3846647290AECCDAE9071533415F7D8BA9B7C5E3F2102E3C5A688694A2C0D",
|
2767 |
|
|
INIT_18 => X"9374563719FADCBD9F8062432506E8C9AA8C6D4F3012F3D5B698795A3C1DFFE0",
|
2768 |
|
|
INIT_19 => X"62442507E8CAAC8D6F503213F5D6B8997B5C3E1F01E2C4A587684A2B0DEED0B1",
|
2769 |
|
|
INIT_1A => X"3012F3D5B6987A5B3D1E00E1C3A58668492B0DEED0B19374563719FBDCBE9F81",
|
2770 |
|
|
INIT_1B => X"FCDDBFA18264462709EBCCAE9071533416F8D9BB9D7E60412305E6C8AA8B6D4E",
|
2771 |
|
|
INIT_1C => X"C6A8896B4D2E10F2D3B597795A3C1EFFE1C3A48668492B0DEED0B2937557381A",
|
2772 |
|
|
INIT_1D => X"8E70523315F7D9BA9C7E60412305E7C8AA8C6E4F3113F5D6B89A7C5D3F2102E4",
|
2773 |
|
|
INIT_1E => X"553618FADCBE9F8163452709EACCAE9072533517F9DABC9E8062432507E9CBAC",
|
2774 |
|
|
INIT_1F => X"19FBDDBFA1836446280AECCEB09273553719FBDDBEA0826446280AEBCDAF9173",
|
2775 |
|
|
INIT_20 => X"DCBEA0826446280AECCDAF9173553719FBDDBFA1836446280AECCEB092745537",
|
2776 |
|
|
INIT_21 => X"CEBFB0A192837465564738291A0BFCEDDECFC0B1A2938475665748392A1B0CFA",
|
2777 |
|
|
INIT_22 => X"AE9F90817263544536271809FAEBDCCDBEAFA09182736455463728190AFBECDD",
|
2778 |
|
|
INIT_23 => X"8D7E6F60514233241506F7E8D9CABCAD9E8F807162534435261708F9EADBCCBD",
|
2779 |
|
|
INIT_24 => X"6B5C4D3E2F201102F3E4D6C7B8A99A8B7C6D5E4F4031221304F6E7D8C9BAAB9C",
|
2780 |
|
|
INIT_25 => X"48392A1B0CFDEFE0D1C2B3A495867768594B3C2D1E0F00F1E2D3C4B5A798897A",
|
2781 |
|
|
INIT_26 => X"241506F7E9DACBBCAD9E8F817263544536271809FBECDDCEBFB0A19283756657",
|
2782 |
|
|
INIT_27 => X"FFF1E2D3C4B5A698897A6B5C4D3E30211203F4E5D6C8B9AA9B8C7D6E60514233",
|
2783 |
|
|
INIT_28 => X"DACBBCAD9F9081726355463728190AFCEDDECFC0B1A394857667584A3B2C1D0E",
|
2784 |
|
|
INIT_29 => X"B4A59687786A5B4C3D2E201102F3E4D6C7B8A99A8C7D6E5F504233241506F8E9",
|
2785 |
|
|
INIT_2A => X"8C7E6F60514334251607F9EADBCCBEAFA0918274655647392A1B0CFDEFE0D1C2",
|
2786 |
|
|
INIT_2B => X"64564738291B0CFDEEE0D1C2B3A59687786A5B4C3D2F201102F4E5D6C7B9AA9B",
|
2787 |
|
|
INIT_2C => X"3B2D1E0F00F2E3D4C6B7A8998B7C6D5F504132241506F8E9DACBBDAE9F908273",
|
2788 |
|
|
INIT_2D => X"1203F4E5D7C8B9AB9C8D7F7061534435271809FAECDDCEC0B1A294857667594A",
|
2789 |
|
|
INIT_2E => X"E7D8CABBAC9E8F807263544637281A0BFCEEDFD0C2B3A49687786A5B4C3E2F20",
|
2790 |
|
|
INIT_2F => X"BBAD9E90817264554638291B0CFDEFE0D1C3B4A59788796B5C4D3F30221304F6",
|
2791 |
|
|
INIT_30 => X"8F817263554638291A0CFDEFE0D1C3B4A597887A6B5C4E3F30221305F6E7D9CA",
|
2792 |
|
|
INIT_31 => X"6253453628190BFCEDDFD0C2B3A49687796A5C4D3E30211304F5E7D8CABBAC9E",
|
2793 |
|
|
INIT_32 => X"34261708FAEBDDCEC0B1A3948577685A4B3D2E1F1102F4E5D7C8BAAB9C8E7F71",
|
2794 |
|
|
INIT_33 => X"05F7E8DACBBDAEA09183746657483A2B1D0E00F1E3D4C6B7A89A8B7D6E605143",
|
2795 |
|
|
INIT_34 => X"D6C7B9AA9C8D7F706253453628190BFCEEDFD1C2B4A597887A6B5C4E3F312214",
|
2796 |
|
|
INIT_35 => X"A597887A6B5D4E4031231506F8E9DBCCBEAFA192847567584A3B2D1E1001F3E4",
|
2797 |
|
|
INIT_36 => X"746657493A2C1D0F00F2E4D5C7B8AA9B8D7E706153443628190BFCEEDFD1C2B4",
|
2798 |
|
|
INIT_37 => X"4234251708FAEBDDCFC0B2A39586786A5B4D3E30211304F6E8D9CBBCAE9F9183",
|
2799 |
|
|
INIT_38 => X"0F01F2E4D6C7B9AA9C8E7F7162544537291A0CFDEFE1D2C4B5A7998A7C6D5F50",
|
2800 |
|
|
INIT_39 => X"DBCDBFB0A2948577685A4C3D2F211204F5E7D9CABCAD9F9182746557493A2C1E",
|
2801 |
|
|
INIT_3A => X"A7998A7C6E5F514334261709FBECDED0C1B3A59688796B5D4E4032231507F8EA",
|
2802 |
|
|
INIT_3B => X"72635547382A1C0DFFF1E2D4C6B7A99B8C7E7061534536281A0BFDEFE0D2C4B5",
|
2803 |
|
|
INIT_3C => X"3C2D1F1102F4E6D7C9BBAD9E9082736557483A2C1D0F01F3E4D6C8B9AB9D8E80",
|
2804 |
|
|
INIT_3D => X"05F6E8DACCBDAFA192847668594B3D2F201204F5E7D9CABCAEA091837566584A",
|
2805 |
|
|
INIT_3E => X"CDBFB0A2948677695B4D3E30221405F7E9DBCCBEB0A2938577695A4C3E2F2113",
|
2806 |
|
|
INIT_3F => X"9586786A5C4D3F31231406F8EADCCDBFB1A39486786A5B4D3F31221406F8E9DB",
|
2807 |
|
|
INIT_40 => X"5B4D3F31221406F8EADBCDBFB1A39486786A5C4D3F31231406F8EADCCDBFB1A3",
|
2808 |
|
|
INIT_41 => X"211305F7E8DACCBEB0A2938577695B4C3E30221406F7E9DBCDBFB0A294867869",
|
2809 |
|
|
INIT_42 => X"E6D8CABCAEA091837567594B3C2E201204F6E8D9CBBDAFA1938476685A4C3E2F",
|
2810 |
|
|
INIT_43 => X"AB9D8E80726456483A2C1D0F01F3E5D7C9BAAC9E9082746657493B2D1F1103F4",
|
2811 |
|
|
INIT_44 => X"B7B0A9A29B948D867E777069625B544D463F38312A231C150E07FFF1E3D5C7B9",
|
2812 |
|
|
INIT_45 => X"98918A837C756E676059524B443D362F28211A130B04FDF6EFE8E1DAD3CCC5BE",
|
2813 |
|
|
INIT_46 => X"79726B645D564F48413A332C251E17100902FBF4EDE6DFD8D1CAC3BBB4ADA69F",
|
2814 |
|
|
INIT_47 => X"5A534C453E373029221B140D06FFF8F1EAE3DCD5CEC7C0B9B2ABA39C958E8780",
|
2815 |
|
|
INIT_48 => X"3A332C251E17100902FBF4EDE6DFD8D1CAC3BCB5AEA7A099928B847D766F6861",
|
2816 |
|
|
INIT_49 => X"1A130C05FEF7F0E9E2DBD4CDC6BFB8B1AAA39C958E878079726B645D564F4841",
|
2817 |
|
|
INIT_4A => X"FAF3ECE5DED7D0C9C2BBB4ADA69F98918A837C756E676059524B443D362F2821",
|
2818 |
|
|
INIT_4B => X"D9D2CBC4BDB6AFA8A19A938C857E777069625B544D463F38312A231C150F0801",
|
2819 |
|
|
INIT_4C => X"B7B0AAA39C958E878079726B645D564F48413A332C251E17100902FCF5EEE7E0",
|
2820 |
|
|
INIT_4D => X"968F88817A736C655E575049423B352E272019120B04FDF6EFE8E1DAD3CCC5BE",
|
2821 |
|
|
INIT_4E => X"746D665F58514A433C352E27211A130C05FEF7F0E9E2DBD4CDC6BFB8B2ABA49D",
|
2822 |
|
|
INIT_4F => X"514A433D362F28211A130C05FEF7F0EAE3DCD5CEC7C0B9B2ABA49D968F89827B",
|
2823 |
|
|
INIT_50 => X"2F28211A130C05FEF7F0E9E3DCD5CEC7C0B9B2ABA49D979089827B746D665F58",
|
2824 |
|
|
INIT_51 => X"0B05FEF7F0E9E2DBD4CDC6C0B9B2ABA49D968F88817B746D665F58514A433C35",
|
2825 |
|
|
INIT_52 => X"E8E1DAD3CCC5BFB8B1AAA39C958E87817A736C655E575049433C352E27201912",
|
2826 |
|
|
INIT_53 => X"C4BDB6AFA9A29B948D867F78726B645D564F48413A342D261F18110A03FDF6EF",
|
2827 |
|
|
INIT_54 => X"A099928B847D777069625B544D474039322B241D16100902FBF4EDE6DFD9D2CB",
|
2828 |
|
|
INIT_55 => X"7B746D676059524B443D373029221B140D0700F9F2EBE4DDD7D0C9C2BBB4ADA7",
|
2829 |
|
|
INIT_56 => X"564F48423B342D261F19120B04FDF6F0E9E2DBD4CDC6C0B9B2ABA49D97908982",
|
2830 |
|
|
INIT_57 => X"312A231C150F0801FAF3ECE6DFD8D1CAC3BDB6AFA8A19A948D867F78716B645D",
|
2831 |
|
|
INIT_58 => X"0B04FDF7F0E9E2DBD5CEC7C0B9B2ACA59E979089837C756E67615A534C453E38",
|
2832 |
|
|
INIT_59 => X"E5DED7D1CAC3BCB5AFA8A19A938C867F78716A645D564F48423B342D261F1912",
|
2833 |
|
|
INIT_5A => X"BFB8B1AAA39D968F88817B746D665F59524B443D373029221B150E0700F9F3EC",
|
2834 |
|
|
INIT_5B => X"98918A837D766F68615B544D464039322B241E17100902FCF5EEE7E0DAD3CCC5",
|
2835 |
|
|
INIT_5C => X"716A635C554F48413A342D261F18120B04FDF7F0E9E2DCD5CEC7C0BAB3ACA59E",
|
2836 |
|
|
INIT_5D => X"49423B352E27201A130C05FFF8F1EAE4DDD6CFC9C2BBB4ADA7A099928C857E77",
|
2837 |
|
|
INIT_5E => X"211A140D06FFF9F2EBE4DED7D0C9C3BCB5AEA8A19A938D867F78726B645D5750",
|
2838 |
|
|
INIT_5F => X"F9F2EBE5DED7D0CAC3BCB6AFA8A19B948D868079726B655E57504A433C352F28",
|
2839 |
|
|
INIT_60 => X"D0CAC3BCB5AFA8A19A948D868079726B655E57504A433C362F28211B140D0600",
|
2840 |
|
|
INIT_61 => X"A7A19A938C867F78726B645D575049433C352E28211A140D06FFF9F2EBE4DED7",
|
2841 |
|
|
INIT_62 => X"7E77716A635D564F48423B342E272019130C05FFF8F1EAE4DDD6D0C9C2BBB5AE",
|
2842 |
|
|
INIT_63 => X"544E47403A332C261F18110B04FDF7F0E9E3DCD5CEC8C1BAB4ADA6A099928B85",
|
2843 |
|
|
INIT_64 => X"2A241D16100902FCF5EEE8E1DAD4CDC6BFB9B2ABA59E97918A837D766F68625B",
|
2844 |
|
|
INIT_65 => X"00F9F3ECE5DFD8D1CBC4BDB7B0A9A39C958F88817B746D676059524C453E3831",
|
2845 |
|
|
INIT_66 => X"D5CFC8C1BBB4ADA7A099938C857F78716B645D575049433C352F28211B140D07",
|
2846 |
|
|
INIT_67 => X"AAA49D969089827C756E68615A544D474039332C251F18110B04FDF7F0E9E3DC",
|
2847 |
|
|
INIT_68 => X"7F78726B645E57504A433D362F29221B150E0701FAF3EDE6E0D9D2CCC5BEB8B1",
|
2848 |
|
|
INIT_69 => X"534D463F39322B251E18110A04FDF6F0E9E2DCD5CFC8C1BBB4ADA7A099938C86",
|
2849 |
|
|
INIT_6A => X"27211A130D06FFF9F2ECE5DED8D1CAC4BDB7B0A9A39C958F88827B746E67605A",
|
2850 |
|
|
INIT_6B => X"FBF4EDE7E0DAD3CCC6BFB9B2ABA59E98918A847D777069635C554F48423B342E",
|
2851 |
|
|
INIT_6C => X"CEC7C1BAB4ADA6A099938C857F78726B645E57514A433D363029221C150F0801",
|
2852 |
|
|
INIT_6D => X"A19A948D878079736C665F58524B453E37312A241D16100903FCF6EFE8E2DBD5",
|
2853 |
|
|
INIT_6E => X"736D666059534C453F38322B241E17110A04FDF6F0E9E3DCD6CFC8C2BBB5AEA7",
|
2854 |
|
|
INIT_6F => X"463F39322B251E18110B04FDF7F0EAE3DDD6CFC9C2BCB5AFA8A19B948E87817A",
|
2855 |
|
|
INIT_70 => X"18110A04FDF7F0EAE3DDD6CFC9C2BCB5AFA8A29B948E87817A746D666059534C",
|
2856 |
|
|
INIT_71 => X"E9E3DCD5CFC8C2BBB5AEA8A19B948D87807A736D666059524C453F38322B251E",
|
2857 |
|
|
INIT_72 => X"BAB4ADA7A09A938D867F79726C655F58524B453E38312A241D17100A03FDF6F0",
|
2858 |
|
|
INIT_73 => X"8B857E78716B645E57504A433D363029231C160F0902FCF5EFE8E1DBD4CEC7C1",
|
2859 |
|
|
INIT_74 => X"5C554F48423B352E28211B140E0701FAF3EDE6E0D9D3CCC6BFB9B2ACA59F9892",
|
2860 |
|
|
INIT_75 => X"2C251F18120B05FEF8F1EBE4DED7D1CAC4BDB7B0AAA39D969089837C766F6962",
|
2861 |
|
|
INIT_76 => X"FCF5EFE8E2DBD5CEC8C1BBB4AEA7A19A948D87807A736D666059534C463F3932",
|
2862 |
|
|
INIT_77 => X"CBC5BEB8B1ABA59E98918B847E77716A645D57504A433D363029231C160F0902",
|
2863 |
|
|
INIT_78 => X"9B948E87817A746D67605A534D46403A332D262019130C06FFF9F2ECE5DFD8D2",
|
2864 |
|
|
INIT_79 => X"6A635D565049433C362F29221C160F0902FCF5EFE8E2DBD5CEC8C1BBB5AEA8A1",
|
2865 |
|
|
INIT_7A => X"38322B251E18110B05FEF8F1EBE4DED7D1CAC4BEB7B1AAA49D97908A837D7670",
|
2866 |
|
|
INIT_7B => X"0600FAF3EDE6E0D9D3CCC6C0B9B3ACA69F99928C867F79726C655F58524B453F",
|
2867 |
|
|
INIT_7C => X"D4CEC7C1BBB4AEA7A19A948E87817A746D67615A544D47403A332D27201A130D",
|
2868 |
|
|
INIT_7D => X"A29C958F88827B756F68625B554E48423B352E28211B150E0801FBF4EEE8E1DB",
|
2869 |
|
|
INITP_0E => X"FFFFFFFF0000000001FFFFFFFFFE0000000003FFFFFFFFF8000000000FFFFFFF",
|
2870 |
|
|
INIT_FILE => "NONE",
|
2871 |
|
|
RAM_EXTENSION_A => "NONE",
|
2872 |
|
|
RAM_EXTENSION_B => "NONE",
|
2873 |
|
|
READ_WIDTH_A => 9,
|
2874 |
|
|
READ_WIDTH_B => 9,
|
2875 |
|
|
SIM_COLLISION_CHECK => "ALL",
|
2876 |
|
|
SIM_MODE => "SAFE",
|
2877 |
|
|
INIT_A => X"000000000",
|
2878 |
|
|
INIT_B => X"000000000",
|
2879 |
|
|
WRITE_MODE_A => "WRITE_FIRST",
|
2880 |
|
|
WRITE_MODE_B => "WRITE_FIRST",
|
2881 |
|
|
WRITE_WIDTH_A => 9,
|
2882 |
|
|
WRITE_WIDTH_B => 9,
|
2883 |
|
|
INITP_0F => X"003FFFFFFFFFC0000000003FFFFFFFFFC0000000007FFFFFFFFF8000000000FF"
|
2884 |
|
|
)
|
2885 |
|
|
port map (
|
2886 |
|
|
ENAU => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_0_cmp_eq0000,
|
2887 |
|
|
ENAL => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_0_cmp_eq0000,
|
2888 |
|
|
ENBU => BU2_doutb(0),
|
2889 |
|
|
ENBL => BU2_doutb(0),
|
2890 |
|
|
SSRAU => BU2_doutb(0),
|
2891 |
|
|
SSRAL => BU2_doutb(0),
|
2892 |
|
|
SSRBU => BU2_doutb(0),
|
2893 |
|
|
SSRBL => BU2_doutb(0),
|
2894 |
|
|
CLKAU => clka,
|
2895 |
|
|
CLKAL => clka,
|
2896 |
|
|
CLKBU => BU2_doutb(0),
|
2897 |
|
|
CLKBL => BU2_doutb(0),
|
2898 |
|
|
REGCLKAU => clka,
|
2899 |
|
|
REGCLKAL => clka,
|
2900 |
|
|
REGCLKBU => BU2_doutb(0),
|
2901 |
|
|
REGCLKBL => BU2_doutb(0),
|
2902 |
|
|
REGCEAU => BU2_doutb(0),
|
2903 |
|
|
REGCEAL => BU2_doutb(0),
|
2904 |
|
|
REGCEBU => BU2_doutb(0),
|
2905 |
|
|
REGCEBL => BU2_doutb(0),
|
2906 |
|
|
CASCADEINLATA => BU2_doutb(0),
|
2907 |
|
|
CASCADEINLATB => BU2_doutb(0),
|
2908 |
|
|
CASCADEINREGA => BU2_doutb(0),
|
2909 |
|
|
CASCADEINREGB => BU2_doutb(0),
|
2910 |
|
|
CASCADEOUTLATA => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATA_UNCONNECTED,
|
2911 |
|
|
CASCADEOUTLATB => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATB_UNCONNECTED,
|
2912 |
|
|
CASCADEOUTREGA => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGA_UNCONNECTED,
|
2913 |
|
|
CASCADEOUTREGB => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGB_UNCONNECTED,
|
2914 |
|
|
DIA(31) => BU2_doutb(0),
|
2915 |
|
|
DIA(30) => BU2_doutb(0),
|
2916 |
|
|
DIA(29) => BU2_doutb(0),
|
2917 |
|
|
DIA(28) => BU2_doutb(0),
|
2918 |
|
|
DIA(27) => BU2_doutb(0),
|
2919 |
|
|
DIA(26) => BU2_doutb(0),
|
2920 |
|
|
DIA(25) => BU2_doutb(0),
|
2921 |
|
|
DIA(24) => BU2_doutb(0),
|
2922 |
|
|
DIA(23) => BU2_doutb(0),
|
2923 |
|
|
DIA(22) => BU2_doutb(0),
|
2924 |
|
|
DIA(21) => BU2_doutb(0),
|
2925 |
|
|
DIA(20) => BU2_doutb(0),
|
2926 |
|
|
DIA(19) => BU2_doutb(0),
|
2927 |
|
|
DIA(18) => BU2_doutb(0),
|
2928 |
|
|
DIA(17) => BU2_doutb(0),
|
2929 |
|
|
DIA(16) => BU2_doutb(0),
|
2930 |
|
|
DIA(15) => BU2_doutb(0),
|
2931 |
|
|
DIA(14) => BU2_doutb(0),
|
2932 |
|
|
DIA(13) => BU2_doutb(0),
|
2933 |
|
|
DIA(12) => BU2_doutb(0),
|
2934 |
|
|
DIA(11) => BU2_doutb(0),
|
2935 |
|
|
DIA(10) => BU2_doutb(0),
|
2936 |
|
|
DIA(9) => BU2_doutb(0),
|
2937 |
|
|
DIA(8) => BU2_doutb(0),
|
2938 |
|
|
DIA(7) => BU2_doutb(0),
|
2939 |
|
|
DIA(6) => BU2_doutb(0),
|
2940 |
|
|
DIA(5) => BU2_doutb(0),
|
2941 |
|
|
DIA(4) => BU2_doutb(0),
|
2942 |
|
|
DIA(3) => BU2_doutb(0),
|
2943 |
|
|
DIA(2) => BU2_doutb(0),
|
2944 |
|
|
DIA(1) => BU2_doutb(0),
|
2945 |
|
|
DIA(0) => BU2_doutb(0),
|
2946 |
|
|
DIPA(3) => BU2_doutb(0),
|
2947 |
|
|
DIPA(2) => BU2_doutb(0),
|
2948 |
|
|
DIPA(1) => BU2_doutb(0),
|
2949 |
|
|
DIPA(0) => BU2_doutb(0),
|
2950 |
|
|
DIB(31) => BU2_doutb(0),
|
2951 |
|
|
DIB(30) => BU2_doutb(0),
|
2952 |
|
|
DIB(29) => BU2_doutb(0),
|
2953 |
|
|
DIB(28) => BU2_doutb(0),
|
2954 |
|
|
DIB(27) => BU2_doutb(0),
|
2955 |
|
|
DIB(26) => BU2_doutb(0),
|
2956 |
|
|
DIB(25) => BU2_doutb(0),
|
2957 |
|
|
DIB(24) => BU2_doutb(0),
|
2958 |
|
|
DIB(23) => BU2_doutb(0),
|
2959 |
|
|
DIB(22) => BU2_doutb(0),
|
2960 |
|
|
DIB(21) => BU2_doutb(0),
|
2961 |
|
|
DIB(20) => BU2_doutb(0),
|
2962 |
|
|
DIB(19) => BU2_doutb(0),
|
2963 |
|
|
DIB(18) => BU2_doutb(0),
|
2964 |
|
|
DIB(17) => BU2_doutb(0),
|
2965 |
|
|
DIB(16) => BU2_doutb(0),
|
2966 |
|
|
DIB(15) => BU2_doutb(0),
|
2967 |
|
|
DIB(14) => BU2_doutb(0),
|
2968 |
|
|
DIB(13) => BU2_doutb(0),
|
2969 |
|
|
DIB(12) => BU2_doutb(0),
|
2970 |
|
|
DIB(11) => BU2_doutb(0),
|
2971 |
|
|
DIB(10) => BU2_doutb(0),
|
2972 |
|
|
DIB(9) => BU2_doutb(0),
|
2973 |
|
|
DIB(8) => BU2_doutb(0),
|
2974 |
|
|
DIB(7) => BU2_doutb(0),
|
2975 |
|
|
DIB(6) => BU2_doutb(0),
|
2976 |
|
|
DIB(5) => BU2_doutb(0),
|
2977 |
|
|
DIB(4) => BU2_doutb(0),
|
2978 |
|
|
DIB(3) => BU2_doutb(0),
|
2979 |
|
|
DIB(2) => BU2_doutb(0),
|
2980 |
|
|
DIB(1) => BU2_doutb(0),
|
2981 |
|
|
DIB(0) => BU2_doutb(0),
|
2982 |
|
|
DIPB(3) => BU2_doutb(0),
|
2983 |
|
|
DIPB(2) => BU2_doutb(0),
|
2984 |
|
|
DIPB(1) => BU2_doutb(0),
|
2985 |
|
|
DIPB(0) => BU2_doutb(0),
|
2986 |
|
|
ADDRAL(15) => BU2_doutb(0),
|
2987 |
|
|
ADDRAL(14) => addra_2(11),
|
2988 |
|
|
ADDRAL(13) => addra_2(10),
|
2989 |
|
|
ADDRAL(12) => addra_2(9),
|
2990 |
|
|
ADDRAL(11) => addra_2(8),
|
2991 |
|
|
ADDRAL(10) => addra_2(7),
|
2992 |
|
|
ADDRAL(9) => addra_2(6),
|
2993 |
|
|
ADDRAL(8) => addra_2(5),
|
2994 |
|
|
ADDRAL(7) => addra_2(4),
|
2995 |
|
|
ADDRAL(6) => addra_2(3),
|
2996 |
|
|
ADDRAL(5) => addra_2(2),
|
2997 |
|
|
ADDRAL(4) => addra_2(1),
|
2998 |
|
|
ADDRAL(3) => addra_2(0),
|
2999 |
|
|
ADDRAL(2) => BU2_doutb(0),
|
3000 |
|
|
ADDRAL(1) => BU2_doutb(0),
|
3001 |
|
|
ADDRAL(0) => BU2_doutb(0),
|
3002 |
|
|
ADDRAU(14) => addra_2(11),
|
3003 |
|
|
ADDRAU(13) => addra_2(10),
|
3004 |
|
|
ADDRAU(12) => addra_2(9),
|
3005 |
|
|
ADDRAU(11) => addra_2(8),
|
3006 |
|
|
ADDRAU(10) => addra_2(7),
|
3007 |
|
|
ADDRAU(9) => addra_2(6),
|
3008 |
|
|
ADDRAU(8) => addra_2(5),
|
3009 |
|
|
ADDRAU(7) => addra_2(4),
|
3010 |
|
|
ADDRAU(6) => addra_2(3),
|
3011 |
|
|
ADDRAU(5) => addra_2(2),
|
3012 |
|
|
ADDRAU(4) => addra_2(1),
|
3013 |
|
|
ADDRAU(3) => addra_2(0),
|
3014 |
|
|
ADDRAU(2) => BU2_doutb(0),
|
3015 |
|
|
ADDRAU(1) => BU2_doutb(0),
|
3016 |
|
|
ADDRAU(0) => BU2_doutb(0),
|
3017 |
|
|
ADDRBL(15) => BU2_doutb(0),
|
3018 |
|
|
ADDRBL(14) => BU2_doutb(0),
|
3019 |
|
|
ADDRBL(13) => BU2_doutb(0),
|
3020 |
|
|
ADDRBL(12) => BU2_doutb(0),
|
3021 |
|
|
ADDRBL(11) => BU2_doutb(0),
|
3022 |
|
|
ADDRBL(10) => BU2_doutb(0),
|
3023 |
|
|
ADDRBL(9) => BU2_doutb(0),
|
3024 |
|
|
ADDRBL(8) => BU2_doutb(0),
|
3025 |
|
|
ADDRBL(7) => BU2_doutb(0),
|
3026 |
|
|
ADDRBL(6) => BU2_doutb(0),
|
3027 |
|
|
ADDRBL(5) => BU2_doutb(0),
|
3028 |
|
|
ADDRBL(4) => BU2_doutb(0),
|
3029 |
|
|
ADDRBL(3) => BU2_doutb(0),
|
3030 |
|
|
ADDRBL(2) => BU2_doutb(0),
|
3031 |
|
|
ADDRBL(1) => BU2_doutb(0),
|
3032 |
|
|
ADDRBL(0) => BU2_doutb(0),
|
3033 |
|
|
ADDRBU(14) => BU2_doutb(0),
|
3034 |
|
|
ADDRBU(13) => BU2_doutb(0),
|
3035 |
|
|
ADDRBU(12) => BU2_doutb(0),
|
3036 |
|
|
ADDRBU(11) => BU2_doutb(0),
|
3037 |
|
|
ADDRBU(10) => BU2_doutb(0),
|
3038 |
|
|
ADDRBU(9) => BU2_doutb(0),
|
3039 |
|
|
ADDRBU(8) => BU2_doutb(0),
|
3040 |
|
|
ADDRBU(7) => BU2_doutb(0),
|
3041 |
|
|
ADDRBU(6) => BU2_doutb(0),
|
3042 |
|
|
ADDRBU(5) => BU2_doutb(0),
|
3043 |
|
|
ADDRBU(4) => BU2_doutb(0),
|
3044 |
|
|
ADDRBU(3) => BU2_doutb(0),
|
3045 |
|
|
ADDRBU(2) => BU2_doutb(0),
|
3046 |
|
|
ADDRBU(1) => BU2_doutb(0),
|
3047 |
|
|
ADDRBU(0) => BU2_doutb(0),
|
3048 |
|
|
WEAU(3) => BU2_doutb(0),
|
3049 |
|
|
WEAU(2) => BU2_doutb(0),
|
3050 |
|
|
WEAU(1) => BU2_doutb(0),
|
3051 |
|
|
WEAU(0) => BU2_doutb(0),
|
3052 |
|
|
WEAL(3) => BU2_doutb(0),
|
3053 |
|
|
WEAL(2) => BU2_doutb(0),
|
3054 |
|
|
WEAL(1) => BU2_doutb(0),
|
3055 |
|
|
WEAL(0) => BU2_doutb(0),
|
3056 |
|
|
WEBU(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_7_UNCONNECTED,
|
3057 |
|
|
WEBU(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_6_UNCONNECTED,
|
3058 |
|
|
WEBU(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_5_UNCONNECTED,
|
3059 |
|
|
WEBU(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_4_UNCONNECTED,
|
3060 |
|
|
WEBU(3) => BU2_doutb(0),
|
3061 |
|
|
WEBU(2) => BU2_doutb(0),
|
3062 |
|
|
WEBU(1) => BU2_doutb(0),
|
3063 |
|
|
WEBU(0) => BU2_doutb(0),
|
3064 |
|
|
WEBL(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_7_UNCONNECTED,
|
3065 |
|
|
WEBL(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_6_UNCONNECTED,
|
3066 |
|
|
WEBL(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_5_UNCONNECTED,
|
3067 |
|
|
WEBL(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_4_UNCONNECTED,
|
3068 |
|
|
WEBL(3) => BU2_doutb(0),
|
3069 |
|
|
WEBL(2) => BU2_doutb(0),
|
3070 |
|
|
WEBL(1) => BU2_doutb(0),
|
3071 |
|
|
WEBL(0) => BU2_doutb(0),
|
3072 |
|
|
DOA(31) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_31_UNCONNECTED,
|
3073 |
|
|
DOA(30) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_30_UNCONNECTED,
|
3074 |
|
|
DOA(29) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_29_UNCONNECTED,
|
3075 |
|
|
DOA(28) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_28_UNCONNECTED,
|
3076 |
|
|
DOA(27) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_27_UNCONNECTED,
|
3077 |
|
|
DOA(26) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_26_UNCONNECTED,
|
3078 |
|
|
DOA(25) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_25_UNCONNECTED,
|
3079 |
|
|
DOA(24) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_24_UNCONNECTED,
|
3080 |
|
|
DOA(23) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_23_UNCONNECTED,
|
3081 |
|
|
DOA(22) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_22_UNCONNECTED,
|
3082 |
|
|
DOA(21) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_21_UNCONNECTED,
|
3083 |
|
|
DOA(20) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_20_UNCONNECTED,
|
3084 |
|
|
DOA(19) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_19_UNCONNECTED,
|
3085 |
|
|
DOA(18) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_18_UNCONNECTED,
|
3086 |
|
|
DOA(17) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_17_UNCONNECTED,
|
3087 |
|
|
DOA(16) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_16_UNCONNECTED,
|
3088 |
|
|
DOA(15) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_15_UNCONNECTED,
|
3089 |
|
|
DOA(14) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_14_UNCONNECTED,
|
3090 |
|
|
DOA(13) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_13_UNCONNECTED,
|
3091 |
|
|
DOA(12) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_12_UNCONNECTED,
|
3092 |
|
|
DOA(11) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_11_UNCONNECTED,
|
3093 |
|
|
DOA(10) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_10_UNCONNECTED,
|
3094 |
|
|
DOA(9) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_9_UNCONNECTED,
|
3095 |
|
|
DOA(8) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_8_UNCONNECTED,
|
3096 |
|
|
DOA(7) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta3(7),
|
3097 |
|
|
DOA(6) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta3(6),
|
3098 |
|
|
DOA(5) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta3(5),
|
3099 |
|
|
DOA(4) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta3(4),
|
3100 |
|
|
DOA(3) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta3(3),
|
3101 |
|
|
DOA(2) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta3(2),
|
3102 |
|
|
DOA(1) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta3(1),
|
3103 |
|
|
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta3(0),
|
3104 |
|
|
DOPA(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_3_UNCONNECTED,
|
3105 |
|
|
DOPA(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_2_UNCONNECTED,
|
3106 |
|
|
DOPA(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_1_UNCONNECTED,
|
3107 |
|
|
DOPA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta3(8),
|
3108 |
|
|
DOB(31) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_31_UNCONNECTED,
|
3109 |
|
|
DOB(30) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_30_UNCONNECTED,
|
3110 |
|
|
DOB(29) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_29_UNCONNECTED,
|
3111 |
|
|
DOB(28) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_28_UNCONNECTED,
|
3112 |
|
|
DOB(27) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_27_UNCONNECTED,
|
3113 |
|
|
DOB(26) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_26_UNCONNECTED,
|
3114 |
|
|
DOB(25) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_25_UNCONNECTED,
|
3115 |
|
|
DOB(24) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_24_UNCONNECTED,
|
3116 |
|
|
DOB(23) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_23_UNCONNECTED,
|
3117 |
|
|
DOB(22) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_22_UNCONNECTED,
|
3118 |
|
|
DOB(21) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_21_UNCONNECTED,
|
3119 |
|
|
DOB(20) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_20_UNCONNECTED,
|
3120 |
|
|
DOB(19) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_19_UNCONNECTED,
|
3121 |
|
|
DOB(18) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_18_UNCONNECTED,
|
3122 |
|
|
DOB(17) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_17_UNCONNECTED,
|
3123 |
|
|
DOB(16) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_16_UNCONNECTED,
|
3124 |
|
|
DOB(15) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_15_UNCONNECTED,
|
3125 |
|
|
DOB(14) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_14_UNCONNECTED,
|
3126 |
|
|
DOB(13) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_13_UNCONNECTED,
|
3127 |
|
|
DOB(12) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_12_UNCONNECTED,
|
3128 |
|
|
DOB(11) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_11_UNCONNECTED,
|
3129 |
|
|
DOB(10) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_10_UNCONNECTED,
|
3130 |
|
|
DOB(9) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_9_UNCONNECTED,
|
3131 |
|
|
DOB(8) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_8_UNCONNECTED,
|
3132 |
|
|
DOB(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_7_UNCONNECTED,
|
3133 |
|
|
DOB(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_6_UNCONNECTED,
|
3134 |
|
|
DOB(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_5_UNCONNECTED,
|
3135 |
|
|
DOB(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_4_UNCONNECTED,
|
3136 |
|
|
DOB(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_3_UNCONNECTED,
|
3137 |
|
|
DOB(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_2_UNCONNECTED,
|
3138 |
|
|
DOB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_1_UNCONNECTED,
|
3139 |
|
|
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_0_UNCONNECTED,
|
3140 |
|
|
DOPB(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_3_UNCONNECTED,
|
3141 |
|
|
DOPB(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_2_UNCONNECTED,
|
3142 |
|
|
DOPB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_1_UNCONNECTED,
|
3143 |
|
|
DOPB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_0_UNCONNECTED
|
3144 |
|
|
);
|
3145 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP : RAMB36_EXP
|
3146 |
|
|
generic map(
|
3147 |
|
|
DOA_REG => 0,
|
3148 |
|
|
DOB_REG => 0,
|
3149 |
|
|
INIT_7E => X"7573706D6B686563605D5B585553504D4B484543403D3B383533302D2B282523",
|
3150 |
|
|
INIT_7F => X"CBC8C5C3C0BDBBB8B5B3B0ADABA8A5A3A09D9B989593908D8B888583807D7B78",
|
3151 |
|
|
INITP_00 => X"0000007FFFFFFFFF80000000007FFFFFFFFFC0000000003FFFFFFFFFC0000000",
|
3152 |
|
|
INITP_01 => X"0000000007FFFFFFFFF80000000003FFFFFFFFFE0000000000FFFFFFFFFF0000",
|
3153 |
|
|
INITP_02 => X"000000000003FFFFFFFFFFFFFFFFFFFF000000000000000000001FFFFFFFFFF0",
|
3154 |
|
|
INITP_03 => X"FFFFFFFFFFFFF000000000000000000001FFFFFFFFFFFFFFFFFFFFE000000000",
|
3155 |
|
|
INITP_04 => X"00000000000001FFFFFFFFFFFFFFFFFFFFE000000000000000000000FFFFFFFF",
|
3156 |
|
|
INITP_05 => X"FFFFFFFFFFFFFE000000000000000000000FFFFFFFFFFFFFFFFFFFFFC0000000",
|
3157 |
|
|
INITP_06 => X"0000000000000FFFFFFFFFFFFFFFFFFFFFE0000000000000000000007FFFFFFF",
|
3158 |
|
|
INITP_07 => X"FFFFFFFFFFFC0000000000000000000003FFFFFFFFFFFFFFFFFFFFF800000000",
|
3159 |
|
|
INITP_08 => X"0000000007FFFFFFFFFFFFFFFFFFFFFC0000000000000000000003FFFFFFFFFF",
|
3160 |
|
|
INITP_09 => X"FFFFFF80000000000000000000001FFFFFFFFFFFFFFFFFFFFFF0000000000000",
|
3161 |
|
|
INITP_0A => X"003FFFFFFFFFFFFFFFFFFFFFF00000000000000000000001FFFFFFFFFFFFFFFF",
|
3162 |
|
|
INITP_0B => X"000000000000000000001FFFFFFFFFFFFFFFFFFFFFFE00000000000000000000",
|
3163 |
|
|
INITP_0C => X"FFFFFFFFFFFFFFFC00000000000000000000001FFFFFFFFFFFFFFFFFFFFFFE00",
|
3164 |
|
|
INITP_0D => X"0000000003FFFFFFFFFFFFFFFFFFFFFFF000000000000000000000007FFFFFFF",
|
3165 |
|
|
SRVAL_A => X"000000000",
|
3166 |
|
|
SRVAL_B => X"000000000",
|
3167 |
|
|
INIT_00 => X"0902FCF6EFE9E2DCD6CFC9C3BCB6AFA9A39C968F89837C766F69635C564F4943",
|
3168 |
|
|
INIT_01 => X"D5CFC8C2BCB5AFA8A29C958F89827C756F69625C554F49423C362F29221C160F",
|
3169 |
|
|
INIT_02 => X"A19B948E88817B756E68615B554E48423B352E28221B150F0802FBF5EFE8E2DC",
|
3170 |
|
|
INIT_03 => X"6D66605A534D47403A342D27201A140D0701FAF4EEE7E1DAD4CEC7C1BBB4AEA8",
|
3171 |
|
|
INIT_04 => X"38322C251F18120C05FFF9F2ECE6DFD9D3CCC6C0B9B3ACA6A099938D86807A73",
|
3172 |
|
|
INIT_05 => X"03FDF7F0EAE4DDD7D1CAC4BEB7B1AAA49E97918B847E78716B655E58524B453F",
|
3173 |
|
|
INIT_06 => X"CEC8C1BBB5AEA8A29B958F88827C756F69625C564F49433C363029231D16100A",
|
3174 |
|
|
INIT_07 => X"98928C857F79736C666059534D46403A332D27201A140D0701FAF4EEE7E1DBD4",
|
3175 |
|
|
INIT_08 => X"635C565049433D36302A231D17110A04FEF7F1EBE4DED8D1CBC5BEB8B2ABA59F",
|
3176 |
|
|
INIT_09 => X"2C262019130D0700FAF4EDE7E1DAD4CEC8C1BBB5AEA8A29B958F88827C766F69",
|
3177 |
|
|
INIT_0A => X"F6F0E9E3DDD6D0CAC4BDB7B1AAA49E97918B857E78726B655F58524C463F3933",
|
3178 |
|
|
INIT_0B => X"BFB9B3ACA6A099938D87807A746D67615B544E48413B352F28221C150F0902FC",
|
3179 |
|
|
INIT_0C => X"88827B756F69625C564F49433D36302A241D17110A04FEF8F1EBE5DED8D2CCC5",
|
3180 |
|
|
INIT_0D => X"514A443E37312B251E18120C05FFF9F3ECE6E0D9D3CDC7C0BAB4AEA7A19B958E",
|
3181 |
|
|
INIT_0E => X"19130C0600FAF3EDE7E1DAD4CEC7C1BBB5AEA8A29C958F89837C76706A635D57",
|
3182 |
|
|
INIT_0F => X"E1DBD4CEC8C2BBB5AFA9A29C969089837D77706A645E57514B453E38322C251F",
|
3183 |
|
|
INIT_10 => X"A8A29C968F89837D77706A645E57514B453E38322C251F19130C0600FAF3EDE7",
|
3184 |
|
|
INIT_11 => X"3835312E2B2825221F1C1915120F0C09060300F9F3EDE7E1DAD4CEC8C1BBB5AF",
|
3185 |
|
|
INIT_12 => X"9B9895928F8C8985827F7C797673706D696663605D5A5754514D4A4744413E3B",
|
3186 |
|
|
INIT_13 => X"FFFBF8F5F2EFECE9E6E3DFDCD9D6D3D0CDCAC7C4C0BDBAB7B4B1AEABA8A4A19E",
|
3187 |
|
|
INIT_14 => X"625F5C5855524F4C494643403D393633302D2A2724211E1A1714110E0B080502",
|
3188 |
|
|
INIT_15 => X"C5C2BFBCB8B5B2AFACA9A6A3A09D9A9693908D8A8784817E7B7774716E6B6865",
|
3189 |
|
|
INIT_16 => X"2825221E1B1815120F0C09060300FCF9F6F3F0EDEAE7E4E1DEDAD7D4D1CECBC8",
|
3190 |
|
|
INIT_17 => X"8B8784817E7B7875726F6C6966625F5C595653504D4A4744403D3A3734312E2B",
|
3191 |
|
|
INIT_18 => X"EDEAE7E4E1DEDBD8D5D1CECBC8C5C2BFBCB9B6B3B0ACA9A6A3A09D9A9794918E",
|
3192 |
|
|
INIT_19 => X"504D494643403D3A3734312E2B2825211E1B1815120F0C09060300FDF9F6F3F0",
|
3193 |
|
|
INIT_1A => X"B2AFACA9A6A3A09C999693908D8A8784817E7B7875716E6B6865625F5C595653",
|
3194 |
|
|
INIT_1B => X"14110E0B080502FFFCF9F5F2EFECE9E6E3E0DDDAD7D4D1CECBC7C4C1BEBBB8B5",
|
3195 |
|
|
INIT_1C => X"7673706D6A6764615E5B5855514E4B4845423F3C393633302D2A2723201D1A17",
|
3196 |
|
|
INIT_1D => X"D8D5D2CFCCC9C6C3C0BDBAB6B3B0ADAAA7A4A19E9B9895928F8C8985827F7C79",
|
3197 |
|
|
INIT_1E => X"3A3734312E2B2824211E1B1815120F0C09060300FDFAF7F4F1EDEAE7E4E1DEDB",
|
3198 |
|
|
INIT_1F => X"9B9895928F8C898683807D7A7774716E6B6865615E5B5855524F4C494643403D",
|
3199 |
|
|
INIT_20 => X"FDFAF7F4F1EEEBE8E5E1DEDBD8D5D2CFCCC9C6C3C0BDBAB7B4B1AEABA8A5A29E",
|
3200 |
|
|
INIT_21 => X"5E5B5855524F4C494643403D3A3734312E2B2724211E1B1815120F0C09060300",
|
3201 |
|
|
INIT_22 => X"BFBCB9B6B3B0ADAAA7A4A19E9B9895928F8C898683807D7A7673706D6A676461",
|
3202 |
|
|
INIT_23 => X"201D1A1714110E0B080502FFFCF9F6F3F0EDEAE7E4E1DEDBD8D5D2CFCBC8C5C2",
|
3203 |
|
|
INIT_24 => X"817E7B7875726F6C696663605D5A5754514E4B4845423F3C393633302C292623",
|
3204 |
|
|
INIT_25 => X"E2DFDCD9D6D3D0CDCAC7C4C1BEBBB8B5B2AFACA9A6A39F9C999693908D8A8784",
|
3205 |
|
|
INIT_26 => X"43403D3A3733302D2A2724211E1B1815120F0C09060300FDFAF7F4F1EEEBE8E5",
|
3206 |
|
|
INIT_27 => X"A3A09D9A9794918E8B8885827F7C797673706D6A6764615E5B5855524F4C4946",
|
3207 |
|
|
INIT_28 => X"0300FDFAF7F4F1EEEBE8E5E2DFDCD9D6D3D0CDCAC7C4C1BEBBB8B5B2AFACA9A6",
|
3208 |
|
|
INIT_29 => X"64605D5A5754514E4B4845423F3C393633302D2A2724211E1B1815120F0C0906",
|
3209 |
|
|
INIT_2A => X"C4C1BEBBB8B5B2AFACA9A6A3A09D9A9794918E8B8885827F7C797673706D6A67",
|
3210 |
|
|
INIT_2B => X"23201D1A1714110E0B080502FFFCF9F6F3F0EDEAE7E5E2DFDCD9D6D3D0CDCAC7",
|
3211 |
|
|
INIT_2C => X"83807D7A7774716E6B6865625F5C595653504D4A4744413E3B3835322F2C2926",
|
3212 |
|
|
INIT_2D => X"E3E0DDDAD7D4D1CECBC8C5C2BFBCB9B6B3B0ADAAA7A4A19E9B9895928F8C8986",
|
3213 |
|
|
INIT_2E => X"423F3C393633302D2A2724211E1B181513100D0A070401FEFBF8F5F2EFECE9E6",
|
3214 |
|
|
INIT_2F => X"A29F9C999693908D8A8784817E7B7875726F6C696663605D5A5754514E4B4845",
|
3215 |
|
|
INIT_30 => X"01FEFBF8F5F2EFECE9E6E3E0DDDAD7D4D1CECBC8C5C2BFBCB9B6B3B0ADAAA8A5",
|
3216 |
|
|
INIT_31 => X"605D5A5754514E4B4845423F3C393633302D2A2724211E1B191613100D0A0704",
|
3217 |
|
|
INIT_32 => X"BFBCB9B6B3B0ADAAA7A4A19E9B9895928F8C898683807D7B7875726F6C696663",
|
3218 |
|
|
INIT_33 => X"1D1B1815120F0C09060300FDFAF7F4F1EEEBE8E5E2DFDCD9D6D3D0CECBC8C5C2",
|
3219 |
|
|
INIT_34 => X"7C797673706D6A6764625F5C595653504D4A4744413E3B3835322F2C29262320",
|
3220 |
|
|
INIT_35 => X"DBD8D5D2CFCCC9C6C3C0BDBAB7B4B1AEABA8A5A3A09D9A9794918E8B8885827F",
|
3221 |
|
|
INIT_36 => X"393633302D2A2724211E1C191613100D0A070401FEFBF8F5F2EFECE9E6E3E1DE",
|
3222 |
|
|
INIT_37 => X"9794918E8B898683807D7A7774716E6B6865625F5C595654514E4B4845423F3C",
|
3223 |
|
|
INIT_38 => X"F5F2EFEDEAE7E4E1DEDBD8D5D2CFCCC9C6C3C0BDBBB8B5B2AFACA9A6A3A09D9A",
|
3224 |
|
|
INIT_39 => X"53504D4A4845423F3C393633302D2A2724211E1C191613100D0A070401FEFBF8",
|
3225 |
|
|
INIT_3A => X"B1AEABA8A5A2A09D9A9794918E8B8885827F7C797674716E6B6865625F5C5956",
|
3226 |
|
|
INIT_3B => X"0F0C09060300FDFAF7F4F2EFECE9E6E3E0DDDAD7D4D1CECBC9C6C3C0BDBAB7B4",
|
3227 |
|
|
INIT_3C => X"6C696764615E5B5855524F4C494643413E3B3835322F2C292623201D1A181512",
|
3228 |
|
|
INIT_3D => X"CAC7C4C1BEBBB8B5B2B0ADAAA7A4A19E9B9895928F8C8A8784817E7B7875726F",
|
3229 |
|
|
INIT_3E => X"2724211E1B191613100D0A070401FEFBF8F6F3F0EDEAE7E4E1DEDBD8D5D3D0CD",
|
3230 |
|
|
INIT_3F => X"84817E7C797673706D6A6764615E5B595653504D4A4744413E3B393633302D2A",
|
3231 |
|
|
INIT_40 => X"E1DEDBD9D6D3D0CDCAC7C4C1BEBBB9B6B3B0ADAAA7A4A19E9B999693908D8A87",
|
3232 |
|
|
INIT_41 => X"3E3B383533302D2A2724211E1B181613100D0A070401FEFBF8F6F3F0EDEAE7E4",
|
3233 |
|
|
INIT_42 => X"9B9895928F8C8A8784817E7B7875726F6D6A6764615E5B585552504D4A474441",
|
3234 |
|
|
INIT_43 => X"F8F5F2EFECE9E6E3E0DEDBD8D5D2CFCCC9C6C3C1BEBBB8B5B2AFACA9A7A4A19E",
|
3235 |
|
|
INIT_44 => X"54514E4B484643403D3A3734312E2C292623201D1A1714120F0C09060300FDFA",
|
3236 |
|
|
INIT_45 => X"B0AEABA8A5A29F9C999694918E8B8885827F7C7A7774716E6B686562605D5A57",
|
3237 |
|
|
INIT_46 => X"0D0A070401FEFBF8F6F3F0EDEAE7E4E1DFDCD9D6D3D0CDCAC7C5C2BFBCB9B6B3",
|
3238 |
|
|
INIT_47 => X"696663605D5A5855524F4C494643403E3B3835322F2C292724211E1B18151210",
|
3239 |
|
|
INIT_48 => X"C5C2BFBCB9B6B4B1AEABA8A5A29F9D9A9794918E8B888683807D7A7774716F6C",
|
3240 |
|
|
INIT_49 => X"211E1B1815120F0D0A070401FEFBF8F6F3F0EDEAE7E4E1DFDCD9D6D3D0CDCBC8",
|
3241 |
|
|
INIT_4A => X"7C797774716E6B686563605D5A5754514E4C494643403D3A3835322F2C292623",
|
3242 |
|
|
INIT_4B => X"D8D5D2CFCCCAC7C4C1BEBBB8B6B3B0ADAAA7A4A29F9C999693908E8B8885827F",
|
3243 |
|
|
INIT_4C => X"33312E2B2825221F1D1A1714110E0B09060300FDFAF7F5F2EFECE9E6E3E1DEDB",
|
3244 |
|
|
INIT_4D => X"8F8C898683807E7B7875726F6D6A6764615E5B595653504D4A4745423F3C3936",
|
3245 |
|
|
INIT_4E => X"EAE7E4E1DFDCD9D6D3D0CDCBC8C5C2BFBCBAB7B4B1AEABA8A6A3A09D9A979492",
|
3246 |
|
|
INIT_4F => X"45423F3D3A3734312E2B292623201D1A1815120F0C09060401FEFBF8F5F3F0ED",
|
3247 |
|
|
INIT_50 => X"A09D9A9795928F8C898684817E7B787573706D6A6764615F5C595653504E4B48",
|
3248 |
|
|
INIT_51 => X"FBF8F5F2EFEDEAE7E4E1DEDCD9D6D3D0CDCBC8C5C2BFBCBAB7B4B1AEABA9A6A3",
|
3249 |
|
|
INIT_52 => X"5653504D4A4745423F3C393634312E2B282523201D1A1714120F0C09060301FE",
|
3250 |
|
|
INIT_53 => X"B0ADAAA8A5A29F9C999794918E8B898683807D7A7875726F6C696764615E5B58",
|
3251 |
|
|
INIT_54 => X"0B080502FFFCFAF7F4F1EEECE9E6E3E0DDDBD8D5D2CFCCCAC7C4C1BEBBB9B6B3",
|
3252 |
|
|
INIT_55 => X"65625F5C5A5754514E4C494643403D3B3835322F2C2A2724211E1C191613100D",
|
3253 |
|
|
INIT_56 => X"BFBCBAB7B4B1AEABA9A6A3A09D9B9895928F8C8A8784817E7B797673706D6B68",
|
3254 |
|
|
INIT_57 => X"191614110E0B08060300FDFAF7F5F2EFECE9E7E4E1DEDBD8D6D3D0CDCAC8C5C2",
|
3255 |
|
|
INIT_58 => X"73706E6B686562605D5A5754514F4C494643413E3B383533302D2A2724221F1C",
|
3256 |
|
|
INIT_59 => X"CDCAC7C5C2BFBCB9B7B4B1AEABA9A6A3A09D9B9895928F8C8A8784817E7C7976",
|
3257 |
|
|
INIT_5A => X"2724211E1C191613100E0B08050200FDFAF7F4F1EFECE9E6E3E1DEDBD8D5D3D0",
|
3258 |
|
|
INIT_5B => X"807E7B787572706D6A6764625F5C595654514E4B484643403D3A3835322F2C2A",
|
3259 |
|
|
INIT_5C => X"DAD7D4D1CFCCC9C6C3C1BEBBB8B5B3B0ADAAA7A5A29F9C9A9794918E8C898683",
|
3260 |
|
|
INIT_5D => X"33302E2B282522201D1A1714120F0C09060401FEFBF9F6F3F0EDEBE8E5E2DFDD",
|
3261 |
|
|
INIT_5E => X"8C8A8784817E7C797673716E6B686563605D5A5755524F4C494744413E3C3936",
|
3262 |
|
|
INIT_5F => X"E5E3E0DDDAD8D5D2CFCCCAC7C4C1BFBCB9B6B3B1AEABA8A5A3A09D9A9895928F",
|
3263 |
|
|
INIT_60 => X"3E3C393633312E2B282523201D1A1815120F0C0A070401FFFCF9F6F3F1EEEBE8",
|
3264 |
|
|
INIT_61 => X"9795928F8C898784817E7C797673706E6B686563605D5A5755524F4C4A474441",
|
3265 |
|
|
INIT_62 => X"F0EDEBE8E5E2DFDDDAD7D4D2CFCCC9C6C4C1BEBBB9B6B3B0AEABA8A5A2A09D9A",
|
3266 |
|
|
INIT_63 => X"494643403E3B383533302D2A2725221F1C1A1714110F0C09060301FEFBF8F6F3",
|
3267 |
|
|
INIT_64 => X"A19E9C999693918E8B888683807D7A7875726F6D6A6764625F5C595754514E4B",
|
3268 |
|
|
INIT_65 => X"FAF7F4F1EFECE9E6E4E1DEDBD8D6D3D0CDCBC8C5C2C0BDBAB7B5B2AFACA9A7A4",
|
3269 |
|
|
INIT_66 => X"524F4C4A4744413F3C393634312E2B282623201D1B181512100D0A070502FFFC",
|
3270 |
|
|
INIT_67 => X"AAA7A4A29F9C999794918E8C898683817E7B787673706D6B686562605D5A5755",
|
3271 |
|
|
INIT_68 => X"02FFFDFAF7F4F2EFECE9E7E4E1DEDCD9D6D3D1CECBC8C6C3C0BDBBB8B5B2B0AD",
|
3272 |
|
|
INIT_69 => X"5A5754524F4C494744413E3C393633312E2B292623201E1B181513100D0A0805",
|
3273 |
|
|
INIT_6A => X"B2AFACAAA7A4A19F9C999694918E8B898683807E7B787573706D6A6865625F5D",
|
3274 |
|
|
INIT_6B => X"09070401FEFCF9F6F4F1EEEBE9E6E3E0DEDBD8D5D3D0CDCAC8C5C2BFBDBAB7B4",
|
3275 |
|
|
INIT_6C => X"615E5C595653514E4B484643403D3B383532302D2A2825221F1D1A1714120F0C",
|
3276 |
|
|
INIT_6D => X"B8B6B3B0ADABA8A5A3A09D9A9895928F8D8A8785827F7C7A7774716F6C696664",
|
3277 |
|
|
INIT_6E => X"100D0A080502FFFDFAF7F4F2EFECEAE7E4E1DFDCD9D6D4D1CECCC9C6C3C1BEBB",
|
3278 |
|
|
INIT_6F => X"6764615F5C595754514E4C494644413E3B393633302E2B282623201D1B181512",
|
3279 |
|
|
INIT_70 => X"BEBBB9B6B3B0AEABA8A6A3A09D9B989593908D8A8885827F7D7A7775726F6C6A",
|
3280 |
|
|
INIT_71 => X"1512100D0A070502FFFDFAF7F4F2EFECEAE7E4E1DFDCD9D7D4D1CECCC9C6C3C1",
|
3281 |
|
|
INIT_72 => X"6C696664615E5C595653514E4B494643403E3B383633302D2B282523201D1A18",
|
3282 |
|
|
INIT_73 => X"C3C0BDBAB8B5B2B0ADAAA8A5A29F9D9A9795928F8C8A8784827F7C797774716F",
|
3283 |
|
|
INIT_74 => X"191714110E0C09060401FEFBF9F6F3F1EEEBE9E6E3E0DEDBD8D6D3D0CDCBC8C5",
|
3284 |
|
|
INIT_75 => X"706D6A686562605D5A5755524F4D4A4745423F3C3A3734322F2C292724211F1C",
|
3285 |
|
|
INIT_76 => X"C6C3C1BEBBB9B6B3B1AEABA8A6A3A09E9B989693908D8B888583807D7B787572",
|
3286 |
|
|
INIT_77 => X"1C1A1714120F0C0A070402FFFCF9F7F4F1EFECE9E7E4E1DEDCD9D6D4D1CECCC9",
|
3287 |
|
|
INIT_78 => X"73706D6B686562605D5A585552504D4A4845423F3D3A3735322F2D2A2725221F",
|
3288 |
|
|
INIT_79 => X"C9C6C3C1BEBBB9B6B3B1AEABA8A6A3A09E9B989693908E8B888583807D7B7875",
|
3289 |
|
|
INIT_7A => X"1F1C191714110F0C09060401FEFCF9F6F4F1EEECE9E6E4E1DEDCD9D6D3D1CECB",
|
3290 |
|
|
INIT_7B => X"74726F6C6A6764625F5C5A5754524F4C4A4744423F3C393734312F2C29272421",
|
3291 |
|
|
INIT_7C => X"CAC8C5C2C0BDBAB7B5B2AFADAAA7A5A29F9D9A9795928F8D8A8785827F7D7A77",
|
3292 |
|
|
INIT_7D => X"201D1A181512100D0A08050200FDFAF8F5F2F0EDEAE8E5E2E0DDDAD8D5D2D0CD",
|
3293 |
|
|
INITP_0E => X"FFE000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFF00000000000000",
|
3294 |
|
|
INIT_FILE => "NONE",
|
3295 |
|
|
RAM_EXTENSION_A => "NONE",
|
3296 |
|
|
RAM_EXTENSION_B => "NONE",
|
3297 |
|
|
READ_WIDTH_A => 9,
|
3298 |
|
|
READ_WIDTH_B => 9,
|
3299 |
|
|
SIM_COLLISION_CHECK => "ALL",
|
3300 |
|
|
SIM_MODE => "SAFE",
|
3301 |
|
|
INIT_A => X"000000000",
|
3302 |
|
|
INIT_B => X"000000000",
|
3303 |
|
|
WRITE_MODE_A => "WRITE_FIRST",
|
3304 |
|
|
WRITE_MODE_B => "WRITE_FIRST",
|
3305 |
|
|
WRITE_WIDTH_A => 9,
|
3306 |
|
|
WRITE_WIDTH_B => 9,
|
3307 |
|
|
INITP_0F => X"FFFFFFFFFFFFFFFFFFF800000000000000000000000FFFFFFFFFFFFFFFFFFFFF"
|
3308 |
|
|
)
|
3309 |
|
|
port map (
|
3310 |
|
|
ENAU => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_1_cmp_eq0000,
|
3311 |
|
|
ENAL => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_1_cmp_eq0000,
|
3312 |
|
|
ENBU => BU2_doutb(0),
|
3313 |
|
|
ENBL => BU2_doutb(0),
|
3314 |
|
|
SSRAU => BU2_doutb(0),
|
3315 |
|
|
SSRAL => BU2_doutb(0),
|
3316 |
|
|
SSRBU => BU2_doutb(0),
|
3317 |
|
|
SSRBL => BU2_doutb(0),
|
3318 |
|
|
CLKAU => clka,
|
3319 |
|
|
CLKAL => clka,
|
3320 |
|
|
CLKBU => BU2_doutb(0),
|
3321 |
|
|
CLKBL => BU2_doutb(0),
|
3322 |
|
|
REGCLKAU => clka,
|
3323 |
|
|
REGCLKAL => clka,
|
3324 |
|
|
REGCLKBU => BU2_doutb(0),
|
3325 |
|
|
REGCLKBL => BU2_doutb(0),
|
3326 |
|
|
REGCEAU => BU2_doutb(0),
|
3327 |
|
|
REGCEAL => BU2_doutb(0),
|
3328 |
|
|
REGCEBU => BU2_doutb(0),
|
3329 |
|
|
REGCEBL => BU2_doutb(0),
|
3330 |
|
|
CASCADEINLATA => BU2_doutb(0),
|
3331 |
|
|
CASCADEINLATB => BU2_doutb(0),
|
3332 |
|
|
CASCADEINREGA => BU2_doutb(0),
|
3333 |
|
|
CASCADEINREGB => BU2_doutb(0),
|
3334 |
|
|
CASCADEOUTLATA => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATA_UNCONNECTED,
|
3335 |
|
|
CASCADEOUTLATB => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATB_UNCONNECTED,
|
3336 |
|
|
CASCADEOUTREGA => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGA_UNCONNECTED,
|
3337 |
|
|
CASCADEOUTREGB => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGB_UNCONNECTED,
|
3338 |
|
|
DIA(31) => BU2_doutb(0),
|
3339 |
|
|
DIA(30) => BU2_doutb(0),
|
3340 |
|
|
DIA(29) => BU2_doutb(0),
|
3341 |
|
|
DIA(28) => BU2_doutb(0),
|
3342 |
|
|
DIA(27) => BU2_doutb(0),
|
3343 |
|
|
DIA(26) => BU2_doutb(0),
|
3344 |
|
|
DIA(25) => BU2_doutb(0),
|
3345 |
|
|
DIA(24) => BU2_doutb(0),
|
3346 |
|
|
DIA(23) => BU2_doutb(0),
|
3347 |
|
|
DIA(22) => BU2_doutb(0),
|
3348 |
|
|
DIA(21) => BU2_doutb(0),
|
3349 |
|
|
DIA(20) => BU2_doutb(0),
|
3350 |
|
|
DIA(19) => BU2_doutb(0),
|
3351 |
|
|
DIA(18) => BU2_doutb(0),
|
3352 |
|
|
DIA(17) => BU2_doutb(0),
|
3353 |
|
|
DIA(16) => BU2_doutb(0),
|
3354 |
|
|
DIA(15) => BU2_doutb(0),
|
3355 |
|
|
DIA(14) => BU2_doutb(0),
|
3356 |
|
|
DIA(13) => BU2_doutb(0),
|
3357 |
|
|
DIA(12) => BU2_doutb(0),
|
3358 |
|
|
DIA(11) => BU2_doutb(0),
|
3359 |
|
|
DIA(10) => BU2_doutb(0),
|
3360 |
|
|
DIA(9) => BU2_doutb(0),
|
3361 |
|
|
DIA(8) => BU2_doutb(0),
|
3362 |
|
|
DIA(7) => BU2_doutb(0),
|
3363 |
|
|
DIA(6) => BU2_doutb(0),
|
3364 |
|
|
DIA(5) => BU2_doutb(0),
|
3365 |
|
|
DIA(4) => BU2_doutb(0),
|
3366 |
|
|
DIA(3) => BU2_doutb(0),
|
3367 |
|
|
DIA(2) => BU2_doutb(0),
|
3368 |
|
|
DIA(1) => BU2_doutb(0),
|
3369 |
|
|
DIA(0) => BU2_doutb(0),
|
3370 |
|
|
DIPA(3) => BU2_doutb(0),
|
3371 |
|
|
DIPA(2) => BU2_doutb(0),
|
3372 |
|
|
DIPA(1) => BU2_doutb(0),
|
3373 |
|
|
DIPA(0) => BU2_doutb(0),
|
3374 |
|
|
DIB(31) => BU2_doutb(0),
|
3375 |
|
|
DIB(30) => BU2_doutb(0),
|
3376 |
|
|
DIB(29) => BU2_doutb(0),
|
3377 |
|
|
DIB(28) => BU2_doutb(0),
|
3378 |
|
|
DIB(27) => BU2_doutb(0),
|
3379 |
|
|
DIB(26) => BU2_doutb(0),
|
3380 |
|
|
DIB(25) => BU2_doutb(0),
|
3381 |
|
|
DIB(24) => BU2_doutb(0),
|
3382 |
|
|
DIB(23) => BU2_doutb(0),
|
3383 |
|
|
DIB(22) => BU2_doutb(0),
|
3384 |
|
|
DIB(21) => BU2_doutb(0),
|
3385 |
|
|
DIB(20) => BU2_doutb(0),
|
3386 |
|
|
DIB(19) => BU2_doutb(0),
|
3387 |
|
|
DIB(18) => BU2_doutb(0),
|
3388 |
|
|
DIB(17) => BU2_doutb(0),
|
3389 |
|
|
DIB(16) => BU2_doutb(0),
|
3390 |
|
|
DIB(15) => BU2_doutb(0),
|
3391 |
|
|
DIB(14) => BU2_doutb(0),
|
3392 |
|
|
DIB(13) => BU2_doutb(0),
|
3393 |
|
|
DIB(12) => BU2_doutb(0),
|
3394 |
|
|
DIB(11) => BU2_doutb(0),
|
3395 |
|
|
DIB(10) => BU2_doutb(0),
|
3396 |
|
|
DIB(9) => BU2_doutb(0),
|
3397 |
|
|
DIB(8) => BU2_doutb(0),
|
3398 |
|
|
DIB(7) => BU2_doutb(0),
|
3399 |
|
|
DIB(6) => BU2_doutb(0),
|
3400 |
|
|
DIB(5) => BU2_doutb(0),
|
3401 |
|
|
DIB(4) => BU2_doutb(0),
|
3402 |
|
|
DIB(3) => BU2_doutb(0),
|
3403 |
|
|
DIB(2) => BU2_doutb(0),
|
3404 |
|
|
DIB(1) => BU2_doutb(0),
|
3405 |
|
|
DIB(0) => BU2_doutb(0),
|
3406 |
|
|
DIPB(3) => BU2_doutb(0),
|
3407 |
|
|
DIPB(2) => BU2_doutb(0),
|
3408 |
|
|
DIPB(1) => BU2_doutb(0),
|
3409 |
|
|
DIPB(0) => BU2_doutb(0),
|
3410 |
|
|
ADDRAL(15) => BU2_doutb(0),
|
3411 |
|
|
ADDRAL(14) => addra_2(11),
|
3412 |
|
|
ADDRAL(13) => addra_2(10),
|
3413 |
|
|
ADDRAL(12) => addra_2(9),
|
3414 |
|
|
ADDRAL(11) => addra_2(8),
|
3415 |
|
|
ADDRAL(10) => addra_2(7),
|
3416 |
|
|
ADDRAL(9) => addra_2(6),
|
3417 |
|
|
ADDRAL(8) => addra_2(5),
|
3418 |
|
|
ADDRAL(7) => addra_2(4),
|
3419 |
|
|
ADDRAL(6) => addra_2(3),
|
3420 |
|
|
ADDRAL(5) => addra_2(2),
|
3421 |
|
|
ADDRAL(4) => addra_2(1),
|
3422 |
|
|
ADDRAL(3) => addra_2(0),
|
3423 |
|
|
ADDRAL(2) => BU2_doutb(0),
|
3424 |
|
|
ADDRAL(1) => BU2_doutb(0),
|
3425 |
|
|
ADDRAL(0) => BU2_doutb(0),
|
3426 |
|
|
ADDRAU(14) => addra_2(11),
|
3427 |
|
|
ADDRAU(13) => addra_2(10),
|
3428 |
|
|
ADDRAU(12) => addra_2(9),
|
3429 |
|
|
ADDRAU(11) => addra_2(8),
|
3430 |
|
|
ADDRAU(10) => addra_2(7),
|
3431 |
|
|
ADDRAU(9) => addra_2(6),
|
3432 |
|
|
ADDRAU(8) => addra_2(5),
|
3433 |
|
|
ADDRAU(7) => addra_2(4),
|
3434 |
|
|
ADDRAU(6) => addra_2(3),
|
3435 |
|
|
ADDRAU(5) => addra_2(2),
|
3436 |
|
|
ADDRAU(4) => addra_2(1),
|
3437 |
|
|
ADDRAU(3) => addra_2(0),
|
3438 |
|
|
ADDRAU(2) => BU2_doutb(0),
|
3439 |
|
|
ADDRAU(1) => BU2_doutb(0),
|
3440 |
|
|
ADDRAU(0) => BU2_doutb(0),
|
3441 |
|
|
ADDRBL(15) => BU2_doutb(0),
|
3442 |
|
|
ADDRBL(14) => BU2_doutb(0),
|
3443 |
|
|
ADDRBL(13) => BU2_doutb(0),
|
3444 |
|
|
ADDRBL(12) => BU2_doutb(0),
|
3445 |
|
|
ADDRBL(11) => BU2_doutb(0),
|
3446 |
|
|
ADDRBL(10) => BU2_doutb(0),
|
3447 |
|
|
ADDRBL(9) => BU2_doutb(0),
|
3448 |
|
|
ADDRBL(8) => BU2_doutb(0),
|
3449 |
|
|
ADDRBL(7) => BU2_doutb(0),
|
3450 |
|
|
ADDRBL(6) => BU2_doutb(0),
|
3451 |
|
|
ADDRBL(5) => BU2_doutb(0),
|
3452 |
|
|
ADDRBL(4) => BU2_doutb(0),
|
3453 |
|
|
ADDRBL(3) => BU2_doutb(0),
|
3454 |
|
|
ADDRBL(2) => BU2_doutb(0),
|
3455 |
|
|
ADDRBL(1) => BU2_doutb(0),
|
3456 |
|
|
ADDRBL(0) => BU2_doutb(0),
|
3457 |
|
|
ADDRBU(14) => BU2_doutb(0),
|
3458 |
|
|
ADDRBU(13) => BU2_doutb(0),
|
3459 |
|
|
ADDRBU(12) => BU2_doutb(0),
|
3460 |
|
|
ADDRBU(11) => BU2_doutb(0),
|
3461 |
|
|
ADDRBU(10) => BU2_doutb(0),
|
3462 |
|
|
ADDRBU(9) => BU2_doutb(0),
|
3463 |
|
|
ADDRBU(8) => BU2_doutb(0),
|
3464 |
|
|
ADDRBU(7) => BU2_doutb(0),
|
3465 |
|
|
ADDRBU(6) => BU2_doutb(0),
|
3466 |
|
|
ADDRBU(5) => BU2_doutb(0),
|
3467 |
|
|
ADDRBU(4) => BU2_doutb(0),
|
3468 |
|
|
ADDRBU(3) => BU2_doutb(0),
|
3469 |
|
|
ADDRBU(2) => BU2_doutb(0),
|
3470 |
|
|
ADDRBU(1) => BU2_doutb(0),
|
3471 |
|
|
ADDRBU(0) => BU2_doutb(0),
|
3472 |
|
|
WEAU(3) => BU2_doutb(0),
|
3473 |
|
|
WEAU(2) => BU2_doutb(0),
|
3474 |
|
|
WEAU(1) => BU2_doutb(0),
|
3475 |
|
|
WEAU(0) => BU2_doutb(0),
|
3476 |
|
|
WEAL(3) => BU2_doutb(0),
|
3477 |
|
|
WEAL(2) => BU2_doutb(0),
|
3478 |
|
|
WEAL(1) => BU2_doutb(0),
|
3479 |
|
|
WEAL(0) => BU2_doutb(0),
|
3480 |
|
|
WEBU(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_7_UNCONNECTED,
|
3481 |
|
|
WEBU(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_6_UNCONNECTED,
|
3482 |
|
|
WEBU(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_5_UNCONNECTED,
|
3483 |
|
|
WEBU(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_4_UNCONNECTED,
|
3484 |
|
|
WEBU(3) => BU2_doutb(0),
|
3485 |
|
|
WEBU(2) => BU2_doutb(0),
|
3486 |
|
|
WEBU(1) => BU2_doutb(0),
|
3487 |
|
|
WEBU(0) => BU2_doutb(0),
|
3488 |
|
|
WEBL(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_7_UNCONNECTED,
|
3489 |
|
|
WEBL(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_6_UNCONNECTED,
|
3490 |
|
|
WEBL(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_5_UNCONNECTED,
|
3491 |
|
|
WEBL(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_4_UNCONNECTED,
|
3492 |
|
|
WEBL(3) => BU2_doutb(0),
|
3493 |
|
|
WEBL(2) => BU2_doutb(0),
|
3494 |
|
|
WEBL(1) => BU2_doutb(0),
|
3495 |
|
|
WEBL(0) => BU2_doutb(0),
|
3496 |
|
|
DOA(31) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_31_UNCONNECTED,
|
3497 |
|
|
DOA(30) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_30_UNCONNECTED,
|
3498 |
|
|
DOA(29) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_29_UNCONNECTED,
|
3499 |
|
|
DOA(28) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_28_UNCONNECTED,
|
3500 |
|
|
DOA(27) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_27_UNCONNECTED,
|
3501 |
|
|
DOA(26) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_26_UNCONNECTED,
|
3502 |
|
|
DOA(25) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_25_UNCONNECTED,
|
3503 |
|
|
DOA(24) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_24_UNCONNECTED,
|
3504 |
|
|
DOA(23) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_23_UNCONNECTED,
|
3505 |
|
|
DOA(22) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_22_UNCONNECTED,
|
3506 |
|
|
DOA(21) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_21_UNCONNECTED,
|
3507 |
|
|
DOA(20) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_20_UNCONNECTED,
|
3508 |
|
|
DOA(19) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_19_UNCONNECTED,
|
3509 |
|
|
DOA(18) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_18_UNCONNECTED,
|
3510 |
|
|
DOA(17) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_17_UNCONNECTED,
|
3511 |
|
|
DOA(16) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_16_UNCONNECTED,
|
3512 |
|
|
DOA(15) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_15_UNCONNECTED,
|
3513 |
|
|
DOA(14) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_14_UNCONNECTED,
|
3514 |
|
|
DOA(13) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_13_UNCONNECTED,
|
3515 |
|
|
DOA(12) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_12_UNCONNECTED,
|
3516 |
|
|
DOA(11) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_11_UNCONNECTED,
|
3517 |
|
|
DOA(10) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_10_UNCONNECTED,
|
3518 |
|
|
DOA(9) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_9_UNCONNECTED,
|
3519 |
|
|
DOA(8) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_8_UNCONNECTED,
|
3520 |
|
|
DOA(7) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta4(7),
|
3521 |
|
|
DOA(6) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta4(6),
|
3522 |
|
|
DOA(5) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta4(5),
|
3523 |
|
|
DOA(4) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta4(4),
|
3524 |
|
|
DOA(3) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta4(3),
|
3525 |
|
|
DOA(2) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta4(2),
|
3526 |
|
|
DOA(1) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta4(1),
|
3527 |
|
|
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta4(0),
|
3528 |
|
|
DOPA(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_3_UNCONNECTED,
|
3529 |
|
|
DOPA(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_2_UNCONNECTED,
|
3530 |
|
|
DOPA(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_1_UNCONNECTED,
|
3531 |
|
|
DOPA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta4(8),
|
3532 |
|
|
DOB(31) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_31_UNCONNECTED,
|
3533 |
|
|
DOB(30) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_30_UNCONNECTED,
|
3534 |
|
|
DOB(29) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_29_UNCONNECTED,
|
3535 |
|
|
DOB(28) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_28_UNCONNECTED,
|
3536 |
|
|
DOB(27) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_27_UNCONNECTED,
|
3537 |
|
|
DOB(26) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_26_UNCONNECTED,
|
3538 |
|
|
DOB(25) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_25_UNCONNECTED,
|
3539 |
|
|
DOB(24) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_24_UNCONNECTED,
|
3540 |
|
|
DOB(23) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_23_UNCONNECTED,
|
3541 |
|
|
DOB(22) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_22_UNCONNECTED,
|
3542 |
|
|
DOB(21) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_21_UNCONNECTED,
|
3543 |
|
|
DOB(20) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_20_UNCONNECTED,
|
3544 |
|
|
DOB(19) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_19_UNCONNECTED,
|
3545 |
|
|
DOB(18) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_18_UNCONNECTED,
|
3546 |
|
|
DOB(17) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_17_UNCONNECTED,
|
3547 |
|
|
DOB(16) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_16_UNCONNECTED,
|
3548 |
|
|
DOB(15) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_15_UNCONNECTED,
|
3549 |
|
|
DOB(14) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_14_UNCONNECTED,
|
3550 |
|
|
DOB(13) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_13_UNCONNECTED,
|
3551 |
|
|
DOB(12) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_12_UNCONNECTED,
|
3552 |
|
|
DOB(11) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_11_UNCONNECTED,
|
3553 |
|
|
DOB(10) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_10_UNCONNECTED,
|
3554 |
|
|
DOB(9) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_9_UNCONNECTED,
|
3555 |
|
|
DOB(8) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_8_UNCONNECTED,
|
3556 |
|
|
DOB(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_7_UNCONNECTED,
|
3557 |
|
|
DOB(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_6_UNCONNECTED,
|
3558 |
|
|
DOB(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_5_UNCONNECTED,
|
3559 |
|
|
DOB(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_4_UNCONNECTED,
|
3560 |
|
|
DOB(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_3_UNCONNECTED,
|
3561 |
|
|
DOB(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_2_UNCONNECTED,
|
3562 |
|
|
DOB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_1_UNCONNECTED,
|
3563 |
|
|
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_0_UNCONNECTED,
|
3564 |
|
|
DOPB(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_3_UNCONNECTED,
|
3565 |
|
|
DOPB(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_2_UNCONNECTED,
|
3566 |
|
|
DOPB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_1_UNCONNECTED,
|
3567 |
|
|
DOPB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_0_UNCONNECTED
|
3568 |
|
|
);
|
3569 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP : RAMB36_EXP
|
3570 |
|
|
generic map(
|
3571 |
|
|
DOA_REG => 0,
|
3572 |
|
|
DOB_REG => 0,
|
3573 |
|
|
INIT_7E => X"7C7B7A78777675747372706F6E6D6C6B6A68676665646362605F5E5D5C5B5958",
|
3574 |
|
|
INIT_7F => X"A09F9E9D9C9B9A98979695949392908F8E8D8C8B8A88878685848382807F7E7D",
|
3575 |
|
|
INITP_00 => X"00000000000FFFFFFFFFFFFFFFFFFFFFFFF0000000000000000000000007FFFF",
|
3576 |
|
|
INITP_01 => X"FF0000000000000000000000007FFFFFFFFFFFFFFFFFFFFFFFE0000000000000",
|
3577 |
|
|
INITP_02 => X"FFFFFFFFFFFFFFFFE0000000000000000000000007FFFFFFFFFFFFFFFFFFFFFF",
|
3578 |
|
|
INITP_03 => X"0000007FFFFFFFFFFFFFFFFFFFFFFFF8000000000000000000000000FFFFFFFF",
|
3579 |
|
|
INITP_04 => X"00000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFF8000000000000000000",
|
3580 |
|
|
INITP_05 => X"FFFFFFFF80000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFE00000",
|
3581 |
|
|
INITP_06 => X"FFFFFFFFFFFFFFFFFFFFF00000000000000000000000003FFFFFFFFFFFFFFFFF",
|
3582 |
|
|
INITP_07 => X"00000003FFFFFFFFFFFFFFFFFFFFFFFFFC00000000000000000000000007FFFF",
|
3583 |
|
|
INITP_08 => X"00000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFC000000000000000000",
|
3584 |
|
|
INITP_09 => X"0000000000000000000000000000001FFFFFFFFFFFFFFFFFFFFFFFFFF8000000",
|
3585 |
|
|
INITP_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE0000000000000000000000",
|
3586 |
|
|
INITP_0B => X"00000000000000000000000000000000000000000000000000003FFFFFFFFFFF",
|
3587 |
|
|
INITP_0C => X"000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE0",
|
3588 |
|
|
INITP_0D => X"FFFFFFFFFFFFFFFFFE0000000000000000000000000000000000000000000000",
|
3589 |
|
|
SRVAL_A => X"000000000",
|
3590 |
|
|
SRVAL_B => X"000000000",
|
3591 |
|
|
INIT_00 => X"201D1B181513100D0B08050300FDFBF8F5F3F0EDEBE8E5E3E0DDDBD8D5D3D0CD",
|
3592 |
|
|
INIT_01 => X"7573706D6B686563605D5B585553504D4B484543403D3B383533302D2B282523",
|
3593 |
|
|
INIT_02 => X"CAC8C5C2C0BDBAB8B5B2B0ADAAA8A5A2A09D9A989592908D8A888582807D7A78",
|
3594 |
|
|
INIT_03 => X"1F1D1A1715120F0D0A070502FFFDFAF7F5F2EFEDEAE7E5E2DFDDDAD8D5D2D0CD",
|
3595 |
|
|
INIT_04 => X"74716F6C696764615F5C5A5754524F4C4A4744423F3C3A3734322F2C2A272422",
|
3596 |
|
|
INIT_05 => X"C9C6C3C1BEBCB9B6B4B1AEACA9A6A4A19E9C999694918F8C898784817F7C7977",
|
3597 |
|
|
INIT_06 => X"1D1B181513100E0B08060300FEFBF8F6F3F0EEEBE8E6E3E1DEDBD9D6D3D1CECB",
|
3598 |
|
|
INIT_07 => X"726F6D6A6765625F5D5A575552504D4A484542403D3A383533302D2B28252320",
|
3599 |
|
|
INIT_08 => X"C6C4C1BEBCB9B6B4B1AFACA9A7A4A19F9C999794928F8C8A8784827F7C7A7775",
|
3600 |
|
|
INIT_09 => X"1B181513100D0B08060300FEFBF8F6F3F0EEEBE9E6E3E1DEDBD9D6D3D1CECCC9",
|
3601 |
|
|
INIT_0A => X"6F6C696764625F5C5A5754524F4D4A4745423F3D3A383532302D2A282522201D",
|
3602 |
|
|
INIT_0B => X"C3C0BEBBB8B6B3B0AEABA9A6A3A19E9B999694918E8C898684817F7C79777471",
|
3603 |
|
|
INIT_0C => X"1714120F0C0A070402FFFDFAF7F5F2EFEDEAE8E5E2E0DDDAD8D5D3D0CDCBC8C5",
|
3604 |
|
|
INIT_0D => X"6B686563605E5B585653504E4B494643413E3C393634312E2C292724211F1C19",
|
3605 |
|
|
INIT_0E => X"BEBCB9B7B4B1AFACA9A7A4A29F9C9A9795928F8D8A878582807D7A787573706D",
|
3606 |
|
|
INIT_0F => X"120F0D0A08050200FDFBF8F5F3F0EDEBE8E6E3E0DEDBD9D6D3D1CECBC9C6C4C1",
|
3607 |
|
|
INIT_10 => X"6663605E5B595653514E4C494644413E3C393734312F2C2A2724221F1D1A1715",
|
3608 |
|
|
INIT_11 => X"B9B6B4B1AFACA9A7A4A29F9C9A9795928F8D8A888582807D7A787573706D6B68",
|
3609 |
|
|
INIT_12 => X"0C0A070502FFFDFAF8F5F2F0EDEBE8E5E3E0DEDBD8D6D3D0CECBC9C6C3C1BEBC",
|
3610 |
|
|
INIT_13 => X"605D5A585553504D4B484643403E3B393633312E2C292624211F1C191714120F",
|
3611 |
|
|
INIT_14 => X"B3B0AEABA8A6A3A19E9B999694918E8C898784817F7C7A7774726F6D6A676562",
|
3612 |
|
|
INIT_15 => X"060301FEFBF9F6F4F1EEECE9E7E4E1DFDCDAD7D4D2CFCDCAC7C5C2C0BDBAB8B5",
|
3613 |
|
|
INIT_16 => X"595653514E4C494644413F3C3A3734322F2D2A272522201D1A181513100D0B08",
|
3614 |
|
|
INIT_17 => X"ABA9A6A4A19E9C999794928F8C8A8785827F7D7A787573706D6B686663605E5B",
|
3615 |
|
|
INIT_18 => X"FEFCF9F6F4F1EFECE9E7E4E2DFDDDAD7D5D2D0CDCAC8C5C3C0BEBBB8B6B3B1AE",
|
3616 |
|
|
INIT_19 => X"514E4C494644413F3C393734322F2D2A272522201D1B181513100E0B08060301",
|
3617 |
|
|
INIT_1A => X"A3A19E9B999694918F8C898784827F7D7A777572706D6A686563605E5B585653",
|
3618 |
|
|
INIT_1B => X"F6F3F0EEEBE9E6E4E1DEDCD9D7D4D2CFCCCAC7C5C2C0BDBAB8B5B3B0AEABA8A6",
|
3619 |
|
|
INIT_1C => X"484543403E3B383633312E2C292624211F1C1A1714120F0D0A08050200FDFBF8",
|
3620 |
|
|
INIT_1D => X"9A979592908D8B888683807E7B797674716E6C696764625F5C5A575552504D4A",
|
3621 |
|
|
INIT_1E => X"ECEAE7E4E2DFDDDAD8D5D2D0CDCBC8C6C3C1BEBBB9B6B4B1AFACA9A7A4A29F9D",
|
3622 |
|
|
INIT_1F => X"3E3C393634312F2C2A2724221F1D1A181513100D0B08060301FEFBF9F6F4F1EF",
|
3623 |
|
|
INIT_20 => X"908D8B888683817E7C797674716F6C6A6764625F5D5A585553504D4B48464341",
|
3624 |
|
|
INIT_21 => X"E2DFDDDAD8D5D2D0CDCBC8C6C3C1BEBBB9B6B4B1AFACAAA7A4A29F9D9A989593",
|
3625 |
|
|
INIT_22 => X"33312E2C292724221F1C1A171512100D0B08050300FEFBF9F6F4F1EEECE9E7E4",
|
3626 |
|
|
INIT_23 => X"8582807D7B787673716E6B696664615F5C5A5755524F4D4A484543403E3B3836",
|
3627 |
|
|
INIT_24 => X"D6D4D1CFCCCAC7C5C2C0BDBAB8B5B3B0AEABA9A6A4A19E9C999794928F8D8A88",
|
3628 |
|
|
INIT_25 => X"282523201E1B191613110E0C09070402FFFDFAF7F5F2F0EDEBE8E6E3E1DEDCD9",
|
3629 |
|
|
INIT_26 => X"797774716F6C6A676562605D5B585653504E4B494644413F3C3A3734322F2D2A",
|
3630 |
|
|
INIT_27 => X"CAC8C5C3C0BEBBB8B6B3B1AEACA9A7A4A29F9D9A979592908D8B888683817E7C",
|
3631 |
|
|
INIT_28 => X"1B191614110F0C0A070402FFFDFAF8F5F3F0EEEBE9E6E4E1DEDCD9D7D4D2CFCD",
|
3632 |
|
|
INIT_29 => X"6C6A676562605D5B585553504E4B494644413F3C3A373532302D2A282523201E",
|
3633 |
|
|
INIT_2A => X"BDBBB8B6B3B0AEABA9A6A4A19F9C9A979592908D8B888683807E7B797674716F",
|
3634 |
|
|
INIT_2B => X"0E0B09060401FFFCFAF7F5F2F0EDEBE8E5E3E0DEDBD9D6D4D1CFCCCAC7C5C2C0",
|
3635 |
|
|
INIT_2C => X"5F5C595754524F4D4A484543403E3B393634312F2C2A272522201D1A18151310",
|
3636 |
|
|
INIT_2D => X"AFADAAA8A5A2A09D9B989693918E8C898784827F7D7A787573706E6B69666461",
|
3637 |
|
|
INIT_2E => X"00FDFBF8F5F3F0EEEBE9E6E4E1DFDCDAD7D5D2D0CDCBC8C6C3C1BEBCB9B7B4B2",
|
3638 |
|
|
INIT_2F => X"504D4B484643413E3C393734322F2D2A282523201E1B191614110F0C0A070502",
|
3639 |
|
|
INIT_30 => X"A09E9B999694918F8C8A878582807D7B787673716E6C696664615F5C5A575552",
|
3640 |
|
|
INIT_31 => X"F0EEEBE9E6E4E1DFDCDAD7D5D2D0CDCBC8C6C3C1BEBCB9B7B4B2AFADAAA8A5A3",
|
3641 |
|
|
INIT_32 => X"403E3B393634312F2C2A272522201D1B181613110E0C09070402FFFDFAF8F5F3",
|
3642 |
|
|
INIT_33 => X"908E8B898684817F7C7A777572706D6B686663615E5C595754524F4D4A484543",
|
3643 |
|
|
INIT_34 => X"E0DEDBD9D6D4D1CFCCCAC7C5C2C0BDBBB8B6B3B1AEACA9A7A4A29F9D9A989593",
|
3644 |
|
|
INIT_35 => X"302E2B292624211F1C1A171512100D0B08060301FEFCF9F7F4F2EFEDEAE8E5E3",
|
3645 |
|
|
INIT_36 => X"807D7B787673716E6C696764625F5D5A585553504E4B494644413F3C3A383533",
|
3646 |
|
|
INIT_37 => X"CFCDCAC8C5C3C0BEBBB9B6B4B1AFACAAA8A5A3A09E9B999694918F8C8A878582",
|
3647 |
|
|
INIT_38 => X"1F1C1A171512100D0B08060301FFFCFAF7F5F2F0EDEBE8E6E3E1DEDCD9D7D4D2",
|
3648 |
|
|
INIT_39 => X"6E6C696764625F5D5A585553504E4B494644423F3D3A383533302E2B29262421",
|
3649 |
|
|
INIT_3A => X"BDBBB9B6B4B1AFACAAA7A5A2A09D9B989693918E8C89878482807D7B78767371",
|
3650 |
|
|
INIT_3B => X"0D0A08050300FEFBF9F6F4F1EFEDEAE8E5E3E0DEDBD9D6D4D1CFCCCAC7C5C2C0",
|
3651 |
|
|
INIT_3C => X"5C595754524F4D4A484643413E3C393734322F2D2A282523201E1C191714120F",
|
3652 |
|
|
INIT_3D => X"ABA8A6A3A19E9C9A979592908D8B888683817E7C79777472706D6B686663615E",
|
3653 |
|
|
INIT_3E => X"FAF7F5F2F0EDEBE8E6E4E1DFDCDAD7D5D2D0CDCBC8C6C3C1BFBCBAB7B5B2B0AD",
|
3654 |
|
|
INIT_3F => X"494644413F3C3A373532302D2B292624211F1C1A171512100D0B08060401FFFC",
|
3655 |
|
|
INIT_40 => X"979592908D8B888684817F7C7A777572706D6B696664615F5C5A575552504D4B",
|
3656 |
|
|
INIT_41 => X"E6E3E1DEDCDAD7D5D2D0CDCBC8C6C3C1BFBCBAB7B5B2B0ADABA8A6A4A19F9C9A",
|
3657 |
|
|
INIT_42 => X"34322F2D2B282623211E1C19171512100D0B08060301FEFCFAF7F5F2F0EDEBE8",
|
3658 |
|
|
INIT_43 => X"83807E7B797774726F6D6A686563615E5C595754524F4D4A484643413E3C3937",
|
3659 |
|
|
INIT_44 => X"D1CFCCCAC7C5C3C0BEBBB9B6B4B1AFACAAA8A5A3A09E9B999694928F8D8A8885",
|
3660 |
|
|
INIT_45 => X"1F1D1B181613110E0C0907050200FDFBF8F6F3F1EFECEAE7E5E2E0DDDBD9D6D4",
|
3661 |
|
|
INIT_46 => X"6E6B696664615F5D5A585553504E4B494744423F3D3A383533312E2C29272422",
|
3662 |
|
|
INIT_47 => X"BCB9B7B4B2AFADABA8A6A3A19E9C9A979592908D8B888684817F7C7A77757270",
|
3663 |
|
|
INIT_48 => X"0A07050200FDFBF9F6F4F1EFECEAE8E5E3E0DEDBD9D6D4D2CFCDCAC8C5C3C1BE",
|
3664 |
|
|
INIT_49 => X"585553504E4B494644423F3D3A383533312E2C29272422201D1B181613110F0C",
|
3665 |
|
|
INIT_4A => X"A5A3A09E9C999794928F8D8B888683817E7C7A777572706D6B696664615F5C5A",
|
3666 |
|
|
INIT_4B => X"F3F1EEECE9E7E4E2E0DDDBD8D6D3D1CFCCCAC7C5C2C0BEBBB9B6B4B1AFADAAA8",
|
3667 |
|
|
INIT_4C => X"201F1E1C1B1A19181615141312100F0E0D0B0A0908070504030201FFFDFAF8F5",
|
3668 |
|
|
INIT_4D => X"474644434241403E3D3C3B3938373635333231302F2D2C2B2A29272625242221",
|
3669 |
|
|
INIT_4E => X"6E6C6B6A69676665646361605F5E5D5B5A59585755545352504F4E4D4C4A4948",
|
3670 |
|
|
INIT_4F => X"949392918F8E8D8C8B8988878684838281807E7D7C7B7A78777675747271706F",
|
3671 |
|
|
INIT_50 => X"BBBAB8B7B6B5B4B2B1B0AFAEACABAAA9A8A6A5A4A3A1A09F9E9D9B9A99989795",
|
3672 |
|
|
INIT_51 => X"E1E0DFDEDDDBDAD9D8D7D5D4D3D2D1CFCECDCCCAC9C8C7C6C4C3C2C1C0BEBDBC",
|
3673 |
|
|
INIT_52 => X"08070604030201FFFEFDFCFBF9F8F7F6F5F3F2F1F0EFEDECEBEAE9E7E6E5E4E3",
|
3674 |
|
|
INIT_53 => X"2E2D2C2B2A28272625242221201F1E1C1B1A19181615141312100F0E0D0C0A09",
|
3675 |
|
|
INIT_54 => X"55545251504F4E4C4B4A49484645444342403F3E3D3C3A393837363433323130",
|
3676 |
|
|
INIT_55 => X"7B7A79787675747372706F6E6D6C6A6968676664636261605E5D5C5B5A585756",
|
3677 |
|
|
INIT_56 => X"A2A09F9E9D9C9A9998979694939291908E8D8C8B8A88878685848281807F7E7C",
|
3678 |
|
|
INIT_57 => X"C8C7C5C4C3C2C1C0BEBDBCBBBAB8B7B6B5B4B2B1B0AFAEACABAAA9A8A6A5A4A3",
|
3679 |
|
|
INIT_58 => X"EEEDECEBE9E8E7E6E5E3E2E1E0DFDDDCDBDAD9D7D6D5D4D3D1D0CFCECDCBCAC9",
|
3680 |
|
|
INIT_59 => X"14131211100E0D0C0B0A0807060504020100FFFEFCFBFAF9F8F6F5F4F3F2F1EF",
|
3681 |
|
|
INIT_5A => X"3B3938373635333231302F2D2C2B2A29272625242321201F1E1D1C1A19181716",
|
3682 |
|
|
INIT_5B => X"615F5E5D5C5B5A58575655545251504F4E4C4B4A49484645444342403F3E3D3C",
|
3683 |
|
|
INIT_5C => X"878684838281807E7D7C7B7A78777675747371706F6E6D6B6A69686765646362",
|
3684 |
|
|
INIT_5D => X"ADACAAA9A8A7A6A4A3A2A1A09F9D9C9B9A99979695949391908F8E8D8B8A8988",
|
3685 |
|
|
INIT_5E => X"D3D2D0CFCECDCCCAC9C8C7C6C5C3C2C1C0BFBDBCBBBAB9B7B6B5B4B3B2B0AFAE",
|
3686 |
|
|
INIT_5F => X"F9F8F6F5F4F3F2F0EFEEEDECEAE9E8E7E6E5E3E2E1E0DFDDDCDBDAD9D8D6D5D4",
|
3687 |
|
|
INIT_60 => X"1F1D1C1B1A19181615141312100F0E0D0C0A090807060503020100FFFDFCFBFA",
|
3688 |
|
|
INIT_61 => X"44434241403F3D3C3B3A39373635343332302F2E2D2C2A292827262523222120",
|
3689 |
|
|
INIT_62 => X"6A6968676664636261605E5D5C5B5A59575655545351504F4E4D4C4A49484746",
|
3690 |
|
|
INIT_63 => X"908F8E8D8B8A8988878584838281807E7D7C7B7A78777675747371706F6E6D6B",
|
3691 |
|
|
INIT_64 => X"B6B5B3B2B1B0AFAEACABAAA9A8A6A5A4A3A2A19F9E9D9C9B9998979695949291",
|
3692 |
|
|
INIT_65 => X"DBDAD9D8D7D6D4D3D2D1D0CFCDCCCBCAC9C7C6C5C4C3C2C0BFBEBDBCBBB9B8B7",
|
3693 |
|
|
INIT_66 => X"0100FFFEFCFBFAF9F8F7F5F4F3F2F1EFEEEDECEBEAE8E7E6E5E4E3E1E0DFDEDD",
|
3694 |
|
|
INIT_67 => X"272624232221201E1D1C1B1A19171615141312100F0E0D0C0B09080706050302",
|
3695 |
|
|
INIT_68 => X"4C4B4A49484645444342413F3E3D3C3B3A38373635343231302F2E2D2B2A2928",
|
3696 |
|
|
INIT_69 => X"72716F6E6D6C6B6A68676665646361605F5E5D5C5A5958575654535251504F4D",
|
3697 |
|
|
INIT_6A => X"979695949391908F8E8D8C8A8988878685838281807F7E7C7B7A797876757473",
|
3698 |
|
|
INIT_6B => X"BDBCBAB9B8B7B6B5B3B2B1B0AFADACABAAA9A8A6A5A4A3A2A19F9E9D9C9B9A98",
|
3699 |
|
|
INIT_6C => X"E2E1E0DFDDDCDBDAD9D8D6D5D4D3D2D1CFCECDCCCBCAC8C7C6C5C4C3C1C0BFBE",
|
3700 |
|
|
INIT_6D => X"07060504030200FFFEFDFCFBF9F8F7F6F5F4F2F1F0EFEEEDEBEAE9E8E7E6E4E3",
|
3701 |
|
|
INIT_6E => X"2D2C2A2928272625232221201F1E1C1B1A1918171514131211100E0D0C0B0A09",
|
3702 |
|
|
INIT_6F => X"5251504E4D4C4B4A49484645444342413F3E3D3C3B3A38373635343331302F2E",
|
3703 |
|
|
INIT_70 => X"777675747371706F6E6D6C6A6968676665636261605F5E5C5B5A595857555453",
|
3704 |
|
|
INIT_71 => X"9C9B9A9998979594939291908E8D8C8B8A89878685848382807F7E7D7C7B7A78",
|
3705 |
|
|
INIT_72 => X"C2C0BFBEBDBCBBB9B8B7B6B5B4B2B1B0AFAEADABAAA9A8A7A6A4A3A2A1A09F9E",
|
3706 |
|
|
INIT_73 => X"E7E5E4E3E2E1E0DEDDDCDBDAD9D8D6D5D4D3D2D1CFCECDCCCBCAC8C7C6C5C4C3",
|
3707 |
|
|
INIT_74 => X"0C0A090807060504020100FFFEFDFBFAF9F8F7F6F4F3F2F1F0EFEEECEBEAE9E8",
|
3708 |
|
|
INIT_75 => X"312F2E2D2C2B2A29272625242322201F1E1D1C1B1A18171615141311100F0E0D",
|
3709 |
|
|
INIT_76 => X"5654535251504F4E4C4B4A4948474544434241403F3D3C3B3A39383635343332",
|
3710 |
|
|
INIT_77 => X"7B7978777675747271706F6E6D6C6A6968676665636261605F5E5D5B5A595857",
|
3711 |
|
|
INIT_78 => X"9F9E9D9C9B9A98979695949392908F8E8D8C8B8A88878685848381807F7E7D7C",
|
3712 |
|
|
INIT_79 => X"C4C3C2C1C0BEBDBCBBBAB9B8B6B5B4B3B2B1B0AEADACABAAA9A7A6A5A4A3A2A1",
|
3713 |
|
|
INIT_7A => X"E9E8E7E6E4E3E2E1E0DFDEDCDBDAD9D8D7D6D4D3D2D1D0CFCDCCCBCAC9C8C7C5",
|
3714 |
|
|
INIT_7B => X"0E0D0C0A090807060503020100FFFEFDFBFAF9F8F7F6F5F3F2F1F0EFEEECEBEA",
|
3715 |
|
|
INIT_7C => X"3331302F2E2D2C2A2928272625242221201F1E1D1C1A1918171615141211100F",
|
3716 |
|
|
INIT_7D => X"575655545351504F4E4D4C4B4948474645444341403F3E3D3C3B393837363534",
|
3717 |
|
|
INITP_0E => X"000000000000000000000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
3718 |
|
|
INIT_FILE => "NONE",
|
3719 |
|
|
RAM_EXTENSION_A => "NONE",
|
3720 |
|
|
RAM_EXTENSION_B => "NONE",
|
3721 |
|
|
READ_WIDTH_A => 9,
|
3722 |
|
|
READ_WIDTH_B => 9,
|
3723 |
|
|
SIM_COLLISION_CHECK => "ALL",
|
3724 |
|
|
SIM_MODE => "SAFE",
|
3725 |
|
|
INIT_A => X"000000000",
|
3726 |
|
|
INIT_B => X"000000000",
|
3727 |
|
|
WRITE_MODE_A => "WRITE_FIRST",
|
3728 |
|
|
WRITE_MODE_B => "WRITE_FIRST",
|
3729 |
|
|
WRITE_WIDTH_A => 9,
|
3730 |
|
|
WRITE_WIDTH_B => 9,
|
3731 |
|
|
INITP_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF80000000000000000000000000000"
|
3732 |
|
|
)
|
3733 |
|
|
port map (
|
3734 |
|
|
ENAU => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_2_cmp_eq0000,
|
3735 |
|
|
ENAL => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_2_cmp_eq0000,
|
3736 |
|
|
ENBU => BU2_doutb(0),
|
3737 |
|
|
ENBL => BU2_doutb(0),
|
3738 |
|
|
SSRAU => BU2_doutb(0),
|
3739 |
|
|
SSRAL => BU2_doutb(0),
|
3740 |
|
|
SSRBU => BU2_doutb(0),
|
3741 |
|
|
SSRBL => BU2_doutb(0),
|
3742 |
|
|
CLKAU => clka,
|
3743 |
|
|
CLKAL => clka,
|
3744 |
|
|
CLKBU => BU2_doutb(0),
|
3745 |
|
|
CLKBL => BU2_doutb(0),
|
3746 |
|
|
REGCLKAU => clka,
|
3747 |
|
|
REGCLKAL => clka,
|
3748 |
|
|
REGCLKBU => BU2_doutb(0),
|
3749 |
|
|
REGCLKBL => BU2_doutb(0),
|
3750 |
|
|
REGCEAU => BU2_doutb(0),
|
3751 |
|
|
REGCEAL => BU2_doutb(0),
|
3752 |
|
|
REGCEBU => BU2_doutb(0),
|
3753 |
|
|
REGCEBL => BU2_doutb(0),
|
3754 |
|
|
CASCADEINLATA => BU2_doutb(0),
|
3755 |
|
|
CASCADEINLATB => BU2_doutb(0),
|
3756 |
|
|
CASCADEINREGA => BU2_doutb(0),
|
3757 |
|
|
CASCADEINREGB => BU2_doutb(0),
|
3758 |
|
|
CASCADEOUTLATA => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATA_UNCONNECTED,
|
3759 |
|
|
CASCADEOUTLATB => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATB_UNCONNECTED,
|
3760 |
|
|
CASCADEOUTREGA => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGA_UNCONNECTED,
|
3761 |
|
|
CASCADEOUTREGB => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGB_UNCONNECTED,
|
3762 |
|
|
DIA(31) => BU2_doutb(0),
|
3763 |
|
|
DIA(30) => BU2_doutb(0),
|
3764 |
|
|
DIA(29) => BU2_doutb(0),
|
3765 |
|
|
DIA(28) => BU2_doutb(0),
|
3766 |
|
|
DIA(27) => BU2_doutb(0),
|
3767 |
|
|
DIA(26) => BU2_doutb(0),
|
3768 |
|
|
DIA(25) => BU2_doutb(0),
|
3769 |
|
|
DIA(24) => BU2_doutb(0),
|
3770 |
|
|
DIA(23) => BU2_doutb(0),
|
3771 |
|
|
DIA(22) => BU2_doutb(0),
|
3772 |
|
|
DIA(21) => BU2_doutb(0),
|
3773 |
|
|
DIA(20) => BU2_doutb(0),
|
3774 |
|
|
DIA(19) => BU2_doutb(0),
|
3775 |
|
|
DIA(18) => BU2_doutb(0),
|
3776 |
|
|
DIA(17) => BU2_doutb(0),
|
3777 |
|
|
DIA(16) => BU2_doutb(0),
|
3778 |
|
|
DIA(15) => BU2_doutb(0),
|
3779 |
|
|
DIA(14) => BU2_doutb(0),
|
3780 |
|
|
DIA(13) => BU2_doutb(0),
|
3781 |
|
|
DIA(12) => BU2_doutb(0),
|
3782 |
|
|
DIA(11) => BU2_doutb(0),
|
3783 |
|
|
DIA(10) => BU2_doutb(0),
|
3784 |
|
|
DIA(9) => BU2_doutb(0),
|
3785 |
|
|
DIA(8) => BU2_doutb(0),
|
3786 |
|
|
DIA(7) => BU2_doutb(0),
|
3787 |
|
|
DIA(6) => BU2_doutb(0),
|
3788 |
|
|
DIA(5) => BU2_doutb(0),
|
3789 |
|
|
DIA(4) => BU2_doutb(0),
|
3790 |
|
|
DIA(3) => BU2_doutb(0),
|
3791 |
|
|
DIA(2) => BU2_doutb(0),
|
3792 |
|
|
DIA(1) => BU2_doutb(0),
|
3793 |
|
|
DIA(0) => BU2_doutb(0),
|
3794 |
|
|
DIPA(3) => BU2_doutb(0),
|
3795 |
|
|
DIPA(2) => BU2_doutb(0),
|
3796 |
|
|
DIPA(1) => BU2_doutb(0),
|
3797 |
|
|
DIPA(0) => BU2_doutb(0),
|
3798 |
|
|
DIB(31) => BU2_doutb(0),
|
3799 |
|
|
DIB(30) => BU2_doutb(0),
|
3800 |
|
|
DIB(29) => BU2_doutb(0),
|
3801 |
|
|
DIB(28) => BU2_doutb(0),
|
3802 |
|
|
DIB(27) => BU2_doutb(0),
|
3803 |
|
|
DIB(26) => BU2_doutb(0),
|
3804 |
|
|
DIB(25) => BU2_doutb(0),
|
3805 |
|
|
DIB(24) => BU2_doutb(0),
|
3806 |
|
|
DIB(23) => BU2_doutb(0),
|
3807 |
|
|
DIB(22) => BU2_doutb(0),
|
3808 |
|
|
DIB(21) => BU2_doutb(0),
|
3809 |
|
|
DIB(20) => BU2_doutb(0),
|
3810 |
|
|
DIB(19) => BU2_doutb(0),
|
3811 |
|
|
DIB(18) => BU2_doutb(0),
|
3812 |
|
|
DIB(17) => BU2_doutb(0),
|
3813 |
|
|
DIB(16) => BU2_doutb(0),
|
3814 |
|
|
DIB(15) => BU2_doutb(0),
|
3815 |
|
|
DIB(14) => BU2_doutb(0),
|
3816 |
|
|
DIB(13) => BU2_doutb(0),
|
3817 |
|
|
DIB(12) => BU2_doutb(0),
|
3818 |
|
|
DIB(11) => BU2_doutb(0),
|
3819 |
|
|
DIB(10) => BU2_doutb(0),
|
3820 |
|
|
DIB(9) => BU2_doutb(0),
|
3821 |
|
|
DIB(8) => BU2_doutb(0),
|
3822 |
|
|
DIB(7) => BU2_doutb(0),
|
3823 |
|
|
DIB(6) => BU2_doutb(0),
|
3824 |
|
|
DIB(5) => BU2_doutb(0),
|
3825 |
|
|
DIB(4) => BU2_doutb(0),
|
3826 |
|
|
DIB(3) => BU2_doutb(0),
|
3827 |
|
|
DIB(2) => BU2_doutb(0),
|
3828 |
|
|
DIB(1) => BU2_doutb(0),
|
3829 |
|
|
DIB(0) => BU2_doutb(0),
|
3830 |
|
|
DIPB(3) => BU2_doutb(0),
|
3831 |
|
|
DIPB(2) => BU2_doutb(0),
|
3832 |
|
|
DIPB(1) => BU2_doutb(0),
|
3833 |
|
|
DIPB(0) => BU2_doutb(0),
|
3834 |
|
|
ADDRAL(15) => BU2_doutb(0),
|
3835 |
|
|
ADDRAL(14) => addra_2(11),
|
3836 |
|
|
ADDRAL(13) => addra_2(10),
|
3837 |
|
|
ADDRAL(12) => addra_2(9),
|
3838 |
|
|
ADDRAL(11) => addra_2(8),
|
3839 |
|
|
ADDRAL(10) => addra_2(7),
|
3840 |
|
|
ADDRAL(9) => addra_2(6),
|
3841 |
|
|
ADDRAL(8) => addra_2(5),
|
3842 |
|
|
ADDRAL(7) => addra_2(4),
|
3843 |
|
|
ADDRAL(6) => addra_2(3),
|
3844 |
|
|
ADDRAL(5) => addra_2(2),
|
3845 |
|
|
ADDRAL(4) => addra_2(1),
|
3846 |
|
|
ADDRAL(3) => addra_2(0),
|
3847 |
|
|
ADDRAL(2) => BU2_doutb(0),
|
3848 |
|
|
ADDRAL(1) => BU2_doutb(0),
|
3849 |
|
|
ADDRAL(0) => BU2_doutb(0),
|
3850 |
|
|
ADDRAU(14) => addra_2(11),
|
3851 |
|
|
ADDRAU(13) => addra_2(10),
|
3852 |
|
|
ADDRAU(12) => addra_2(9),
|
3853 |
|
|
ADDRAU(11) => addra_2(8),
|
3854 |
|
|
ADDRAU(10) => addra_2(7),
|
3855 |
|
|
ADDRAU(9) => addra_2(6),
|
3856 |
|
|
ADDRAU(8) => addra_2(5),
|
3857 |
|
|
ADDRAU(7) => addra_2(4),
|
3858 |
|
|
ADDRAU(6) => addra_2(3),
|
3859 |
|
|
ADDRAU(5) => addra_2(2),
|
3860 |
|
|
ADDRAU(4) => addra_2(1),
|
3861 |
|
|
ADDRAU(3) => addra_2(0),
|
3862 |
|
|
ADDRAU(2) => BU2_doutb(0),
|
3863 |
|
|
ADDRAU(1) => BU2_doutb(0),
|
3864 |
|
|
ADDRAU(0) => BU2_doutb(0),
|
3865 |
|
|
ADDRBL(15) => BU2_doutb(0),
|
3866 |
|
|
ADDRBL(14) => BU2_doutb(0),
|
3867 |
|
|
ADDRBL(13) => BU2_doutb(0),
|
3868 |
|
|
ADDRBL(12) => BU2_doutb(0),
|
3869 |
|
|
ADDRBL(11) => BU2_doutb(0),
|
3870 |
|
|
ADDRBL(10) => BU2_doutb(0),
|
3871 |
|
|
ADDRBL(9) => BU2_doutb(0),
|
3872 |
|
|
ADDRBL(8) => BU2_doutb(0),
|
3873 |
|
|
ADDRBL(7) => BU2_doutb(0),
|
3874 |
|
|
ADDRBL(6) => BU2_doutb(0),
|
3875 |
|
|
ADDRBL(5) => BU2_doutb(0),
|
3876 |
|
|
ADDRBL(4) => BU2_doutb(0),
|
3877 |
|
|
ADDRBL(3) => BU2_doutb(0),
|
3878 |
|
|
ADDRBL(2) => BU2_doutb(0),
|
3879 |
|
|
ADDRBL(1) => BU2_doutb(0),
|
3880 |
|
|
ADDRBL(0) => BU2_doutb(0),
|
3881 |
|
|
ADDRBU(14) => BU2_doutb(0),
|
3882 |
|
|
ADDRBU(13) => BU2_doutb(0),
|
3883 |
|
|
ADDRBU(12) => BU2_doutb(0),
|
3884 |
|
|
ADDRBU(11) => BU2_doutb(0),
|
3885 |
|
|
ADDRBU(10) => BU2_doutb(0),
|
3886 |
|
|
ADDRBU(9) => BU2_doutb(0),
|
3887 |
|
|
ADDRBU(8) => BU2_doutb(0),
|
3888 |
|
|
ADDRBU(7) => BU2_doutb(0),
|
3889 |
|
|
ADDRBU(6) => BU2_doutb(0),
|
3890 |
|
|
ADDRBU(5) => BU2_doutb(0),
|
3891 |
|
|
ADDRBU(4) => BU2_doutb(0),
|
3892 |
|
|
ADDRBU(3) => BU2_doutb(0),
|
3893 |
|
|
ADDRBU(2) => BU2_doutb(0),
|
3894 |
|
|
ADDRBU(1) => BU2_doutb(0),
|
3895 |
|
|
ADDRBU(0) => BU2_doutb(0),
|
3896 |
|
|
WEAU(3) => BU2_doutb(0),
|
3897 |
|
|
WEAU(2) => BU2_doutb(0),
|
3898 |
|
|
WEAU(1) => BU2_doutb(0),
|
3899 |
|
|
WEAU(0) => BU2_doutb(0),
|
3900 |
|
|
WEAL(3) => BU2_doutb(0),
|
3901 |
|
|
WEAL(2) => BU2_doutb(0),
|
3902 |
|
|
WEAL(1) => BU2_doutb(0),
|
3903 |
|
|
WEAL(0) => BU2_doutb(0),
|
3904 |
|
|
WEBU(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_7_UNCONNECTED,
|
3905 |
|
|
WEBU(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_6_UNCONNECTED,
|
3906 |
|
|
WEBU(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_5_UNCONNECTED,
|
3907 |
|
|
WEBU(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_4_UNCONNECTED,
|
3908 |
|
|
WEBU(3) => BU2_doutb(0),
|
3909 |
|
|
WEBU(2) => BU2_doutb(0),
|
3910 |
|
|
WEBU(1) => BU2_doutb(0),
|
3911 |
|
|
WEBU(0) => BU2_doutb(0),
|
3912 |
|
|
WEBL(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_7_UNCONNECTED,
|
3913 |
|
|
WEBL(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_6_UNCONNECTED,
|
3914 |
|
|
WEBL(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_5_UNCONNECTED,
|
3915 |
|
|
WEBL(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_4_UNCONNECTED,
|
3916 |
|
|
WEBL(3) => BU2_doutb(0),
|
3917 |
|
|
WEBL(2) => BU2_doutb(0),
|
3918 |
|
|
WEBL(1) => BU2_doutb(0),
|
3919 |
|
|
WEBL(0) => BU2_doutb(0),
|
3920 |
|
|
DOA(31) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_31_UNCONNECTED,
|
3921 |
|
|
DOA(30) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_30_UNCONNECTED,
|
3922 |
|
|
DOA(29) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_29_UNCONNECTED,
|
3923 |
|
|
DOA(28) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_28_UNCONNECTED,
|
3924 |
|
|
DOA(27) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_27_UNCONNECTED,
|
3925 |
|
|
DOA(26) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_26_UNCONNECTED,
|
3926 |
|
|
DOA(25) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_25_UNCONNECTED,
|
3927 |
|
|
DOA(24) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_24_UNCONNECTED,
|
3928 |
|
|
DOA(23) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_23_UNCONNECTED,
|
3929 |
|
|
DOA(22) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_22_UNCONNECTED,
|
3930 |
|
|
DOA(21) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_21_UNCONNECTED,
|
3931 |
|
|
DOA(20) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_20_UNCONNECTED,
|
3932 |
|
|
DOA(19) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_19_UNCONNECTED,
|
3933 |
|
|
DOA(18) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_18_UNCONNECTED,
|
3934 |
|
|
DOA(17) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_17_UNCONNECTED,
|
3935 |
|
|
DOA(16) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_16_UNCONNECTED,
|
3936 |
|
|
DOA(15) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_15_UNCONNECTED,
|
3937 |
|
|
DOA(14) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_14_UNCONNECTED,
|
3938 |
|
|
DOA(13) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_13_UNCONNECTED,
|
3939 |
|
|
DOA(12) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_12_UNCONNECTED,
|
3940 |
|
|
DOA(11) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_11_UNCONNECTED,
|
3941 |
|
|
DOA(10) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_10_UNCONNECTED,
|
3942 |
|
|
DOA(9) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_9_UNCONNECTED,
|
3943 |
|
|
DOA(8) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_8_UNCONNECTED,
|
3944 |
|
|
DOA(7) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta5(7),
|
3945 |
|
|
DOA(6) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta5(6),
|
3946 |
|
|
DOA(5) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta5(5),
|
3947 |
|
|
DOA(4) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta5(4),
|
3948 |
|
|
DOA(3) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta5(3),
|
3949 |
|
|
DOA(2) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta5(2),
|
3950 |
|
|
DOA(1) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta5(1),
|
3951 |
|
|
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta5(0),
|
3952 |
|
|
DOPA(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_3_UNCONNECTED,
|
3953 |
|
|
DOPA(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_2_UNCONNECTED,
|
3954 |
|
|
DOPA(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_1_UNCONNECTED,
|
3955 |
|
|
DOPA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta5(8),
|
3956 |
|
|
DOB(31) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_31_UNCONNECTED,
|
3957 |
|
|
DOB(30) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_30_UNCONNECTED,
|
3958 |
|
|
DOB(29) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_29_UNCONNECTED,
|
3959 |
|
|
DOB(28) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_28_UNCONNECTED,
|
3960 |
|
|
DOB(27) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_27_UNCONNECTED,
|
3961 |
|
|
DOB(26) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_26_UNCONNECTED,
|
3962 |
|
|
DOB(25) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_25_UNCONNECTED,
|
3963 |
|
|
DOB(24) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_24_UNCONNECTED,
|
3964 |
|
|
DOB(23) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_23_UNCONNECTED,
|
3965 |
|
|
DOB(22) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_22_UNCONNECTED,
|
3966 |
|
|
DOB(21) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_21_UNCONNECTED,
|
3967 |
|
|
DOB(20) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_20_UNCONNECTED,
|
3968 |
|
|
DOB(19) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_19_UNCONNECTED,
|
3969 |
|
|
DOB(18) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_18_UNCONNECTED,
|
3970 |
|
|
DOB(17) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_17_UNCONNECTED,
|
3971 |
|
|
DOB(16) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_16_UNCONNECTED,
|
3972 |
|
|
DOB(15) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_15_UNCONNECTED,
|
3973 |
|
|
DOB(14) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_14_UNCONNECTED,
|
3974 |
|
|
DOB(13) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_13_UNCONNECTED,
|
3975 |
|
|
DOB(12) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_12_UNCONNECTED,
|
3976 |
|
|
DOB(11) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_11_UNCONNECTED,
|
3977 |
|
|
DOB(10) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_10_UNCONNECTED,
|
3978 |
|
|
DOB(9) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_9_UNCONNECTED,
|
3979 |
|
|
DOB(8) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_8_UNCONNECTED,
|
3980 |
|
|
DOB(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_7_UNCONNECTED,
|
3981 |
|
|
DOB(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_6_UNCONNECTED,
|
3982 |
|
|
DOB(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_5_UNCONNECTED,
|
3983 |
|
|
DOB(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_4_UNCONNECTED,
|
3984 |
|
|
DOB(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_3_UNCONNECTED,
|
3985 |
|
|
DOB(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_2_UNCONNECTED,
|
3986 |
|
|
DOB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_1_UNCONNECTED,
|
3987 |
|
|
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_0_UNCONNECTED,
|
3988 |
|
|
DOPB(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_3_UNCONNECTED,
|
3989 |
|
|
DOPB(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_2_UNCONNECTED,
|
3990 |
|
|
DOPB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_1_UNCONNECTED,
|
3991 |
|
|
DOPB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_0_UNCONNECTED
|
3992 |
|
|
);
|
3993 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP : RAMB36_EXP
|
3994 |
|
|
generic map(
|
3995 |
|
|
DOA_REG => 0,
|
3996 |
|
|
DOB_REG => 0,
|
3997 |
|
|
INIT_7E => X"9897969594939291908F8E8D8C8B8A898887868584838281807F7E7D7C7B7A79",
|
3998 |
|
|
INIT_7F => X"B8B7B6B5B4B3B2B1B0AFAEADACABAAA9A8A7A6A5A4A3A2A1A09F9E9D9C9B9A99",
|
3999 |
|
|
INITP_00 => X"00000000000000000000000000000000000000000007FFFFFFFFFFFFFFFFFFFF",
|
4000 |
|
|
INITP_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0000000000000",
|
4001 |
|
|
INITP_02 => X"E000000000000000000000000000000000000000000000000000000000FFFFFF",
|
4002 |
|
|
INITP_03 => X"0000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4003 |
|
|
INITP_04 => X"FFFFFFFFFFFFF000000000000000000000000000000000000000000000000000",
|
4004 |
|
|
INITP_05 => X"0000000000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4005 |
|
|
INITP_06 => X"FFFFFFFFFFFFFFFFFFFFFFF80000000000000000000000000000000000000000",
|
4006 |
|
|
INITP_07 => X"0000000000000000000000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4007 |
|
|
INITP_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000000000000000000000000000000",
|
4008 |
|
|
INITP_09 => X"000000000000000000000000000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4009 |
|
|
INITP_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF80000000000000000000000000",
|
4010 |
|
|
INITP_0B => X"00000000000000000000000000000000000000001FFFFFFFFFFFFFFFFFFFFFFF",
|
4011 |
|
|
INITP_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE000000000000000000000",
|
4012 |
|
|
INITP_0D => X"000000000000000000000000000000000000000000003FFFFFFFFFFFFFFFFFFF",
|
4013 |
|
|
SRVAL_A => X"000000000",
|
4014 |
|
|
SRVAL_B => X"000000000",
|
4015 |
|
|
INIT_00 => X"C5C4C3C2C0BFBEBDBCBBBAB8B7B6B5B4B3B2B0AFAEADACABAAA8A7A6A5A4A3A2",
|
4016 |
|
|
INIT_01 => X"E9E8E7E6E5E4E3E1E0DFDEDDDCDBDAD8D7D6D5D4D3D2D0CFCECDCCCBCAC8C7C6",
|
4017 |
|
|
INIT_02 => X"0E0D0C0B090807060504030100FFFEFDFCFBF9F8F7F6F5F4F3F1F0EFEEEDECEB",
|
4018 |
|
|
INIT_03 => X"3231302F2E2D2C2A2928272625242221201F1E1D1C1A1918171615141311100F",
|
4019 |
|
|
INIT_04 => X"575654535251504F4E4D4B4A4948474645434241403F3E3D3B3A393837363534",
|
4020 |
|
|
INIT_05 => X"7B7A7978777574737271706F6D6C6B6A6968676664636261605F5E5C5B5A5958",
|
4021 |
|
|
INIT_06 => X"9F9E9D9C9B9A9997969594939291908E8D8C8B8A8988868584838281807F7D7C",
|
4022 |
|
|
INIT_07 => X"C4C3C1C0BFBEBDBCBBBAB8B7B6B5B4B3B2B0AFAEADACABAAA9A7A6A5A4A3A2A1",
|
4023 |
|
|
INIT_08 => X"E8E7E6E5E3E2E1E0DFDEDDDBDAD9D8D7D6D5D4D2D1D0CFCECDCCCAC9C8C7C6C5",
|
4024 |
|
|
INIT_09 => X"0C0B0A090806050403020100FFFDFCFBFAF9F8F7F6F4F3F2F1F0EFEEECEBEAE9",
|
4025 |
|
|
INIT_0A => X"302F2E2D2C2B2928272625242322201F1E1D1C1B1A1917161514131211100E0D",
|
4026 |
|
|
INIT_0B => X"54535251504F4E4C4B4A4948474645434241403F3E3D3C3A3938373635343331",
|
4027 |
|
|
INIT_0C => X"78777675747372716F6E6D6C6B6A6968666564636261605F5D5C5B5A59585755",
|
4028 |
|
|
INIT_0D => X"9C9B9A9998979695939291908F8E8D8C8A8988878685848381807F7E7D7C7B7A",
|
4029 |
|
|
INIT_0E => X"C0BFBEBDBCBBBAB9B7B6B5B4B3B2B1B0AEADACABAAA9A8A7A5A4A3A2A1A09F9E",
|
4030 |
|
|
INIT_0F => X"E4E3E2E1E0DFDEDDDBDAD9D8D7D6D5D4D2D1D0CFCECDCCCBC9C8C7C6C5C4C3C2",
|
4031 |
|
|
INIT_10 => X"0807060504030200FFFEFDFCFBFAF9F7F6F5F4F3F2F1F0EFEDECEBEAE9E8E7E6",
|
4032 |
|
|
INIT_11 => X"2C2B2A2928272524232221201F1E1D1B1A1918171615141211100F0E0D0C0B09",
|
4033 |
|
|
INIT_12 => X"504F4E4D4C4A4948474645444341403F3E3D3C3B3A3937363534333231302E2D",
|
4034 |
|
|
INIT_13 => X"747372706F6E6D6C6B6A6968666564636261605F5D5C5B5A5958575655535251",
|
4035 |
|
|
INIT_14 => X"98969594939291908F8E8C8B8A8988878685838281807F7E7D7C7B7978777675",
|
4036 |
|
|
INIT_15 => X"BBBAB9B8B7B6B5B3B2B1B0AFAEADACABA9A8A7A6A5A4A3A2A19F9E9D9C9B9A99",
|
4037 |
|
|
INIT_16 => X"DFDEDDDCDBD9D8D7D6D5D4D3D2D0CFCECDCCCBCAC9C8C6C5C4C3C2C1C0BFBEBC",
|
4038 |
|
|
INIT_17 => X"030100FFFEFDFCFBFAF9F7F6F5F4F3F2F1F0EFEDECEBEAE9E8E7E6E5E3E2E1E0",
|
4039 |
|
|
INIT_18 => X"262524232221201E1D1C1B1A1918171614131211100F0E0D0C0A090807060504",
|
4040 |
|
|
INIT_19 => X"4A4948464544434241403F3E3C3B3A3938373635343231302F2E2D2C2B2A2827",
|
4041 |
|
|
INIT_1A => X"6D6C6B6A6968676664636261605F5E5D5C5A5958575655545352504F4E4D4C4B",
|
4042 |
|
|
INIT_1B => X"91908F8D8C8B8A8988878685838281807F7E7D7C7B7978777675747372716F6E",
|
4043 |
|
|
INIT_1C => X"B4B3B2B1B0AFAEACABAAA9A8A7A6A5A4A2A1A09F9E9D9C9B9A99979695949392",
|
4044 |
|
|
INIT_1D => X"D8D7D5D4D3D2D1D0CFCECDCBCAC9C8C7C6C5C4C3C1C0BFBEBDBCBBBAB9B8B6B5",
|
4045 |
|
|
INIT_1E => X"FBFAF9F8F7F5F4F3F2F1F0EFEEEDECEAE9E8E7E6E5E4E3E2E0DFDEDDDCDBDAD9",
|
4046 |
|
|
INIT_1F => X"1E1D1C1B1A1918171514131211100F0E0D0C0A090807060504030201FFFEFDFC",
|
4047 |
|
|
INIT_20 => X"42413F3E3D3C3B3A3938373534333231302F2E2D2C2A2928272625242322211F",
|
4048 |
|
|
INIT_21 => X"65646362605F5E5D5C5B5A5958575554535251504F4E4D4C4A49484746454443",
|
4049 |
|
|
INIT_22 => X"88878685848381807F7E7D7C7B7A7978767574737271706F6E6D6B6A69686766",
|
4050 |
|
|
INIT_23 => X"ABAAA9A8A7A6A5A4A2A1A09F9E9D9C9B9A9997969594939291908F8E8C8B8A89",
|
4051 |
|
|
INIT_24 => X"CECDCCCBCAC9C8C7C6C5C3C2C1C0BFBEBDBCBBBAB8B7B6B5B4B3B2B1B0AFADAC",
|
4052 |
|
|
INIT_25 => X"F1F0EFEEEDECEBEAE9E8E7E5E4E3E2E1E0DFDEDDDCDAD9D8D7D6D5D4D3D2D1CF",
|
4053 |
|
|
INIT_26 => X"15131211100F0E0D0C0B0A090706050403020100FFFEFCFBFAF9F8F7F6F5F4F3",
|
4054 |
|
|
INIT_27 => X"38363534333231302F2E2D2C2A292827262524232221201E1D1C1B1A19181716",
|
4055 |
|
|
INIT_28 => X"5B595857565554535251504F4D4C4B4A4948474645444341403F3E3D3C3B3A39",
|
4056 |
|
|
INIT_29 => X"7E7C7B7A7978777675747372706F6E6D6C6B6A6968676664636261605F5E5D5C",
|
4057 |
|
|
INIT_2A => X"A09F9E9D9C9B9A9998979694939291908F8E8D8C8B8A8887868584838281807F",
|
4058 |
|
|
INIT_2B => X"C3C2C1C0BFBEBDBCBBBAB8B7B6B5B4B3B2B1B0AFAEACABAAA9A8A7A6A5A4A3A2",
|
4059 |
|
|
INIT_2C => X"E6E5E4E3E2E1E0DFDDDCDBDAD9D8D7D6D5D4D3D1D0CFCECDCCCBCAC9C8C7C6C4",
|
4060 |
|
|
INIT_2D => X"090807060504020100FFFEFDFCFBFAF9F8F6F5F4F3F2F1F0EFEEEDECEBE9E8E7",
|
4061 |
|
|
INIT_2E => X"2C2B2A2827262524232221201F1E1D1B1A1918171615141312110F0E0D0C0B0A",
|
4062 |
|
|
INIT_2F => X"4E4D4C4B4A4948474645444341403F3E3D3C3B3A3938373634333231302F2E2D",
|
4063 |
|
|
INIT_30 => X"71706F6E6D6C6B6A6867666564636261605F5E5D5B5A59585756555453525150",
|
4064 |
|
|
INIT_31 => X"949392918F8E8D8C8B8A8988878685848281807F7E7D7C7B7A79787775747372",
|
4065 |
|
|
INIT_32 => X"B6B5B4B3B2B1B0AFAEADACABA9A8A7A6A5A4A3A2A1A09F9E9C9B9A9998979695",
|
4066 |
|
|
INIT_33 => X"D9D8D7D6D5D4D3D1D0CFCECDCCCBCAC9C8C7C6C4C3C2C1C0BFBEBDBCBBBAB9B8",
|
4067 |
|
|
INIT_34 => X"FCFAF9F8F7F6F5F4F3F2F1F0EFEEECEBEAE9E8E7E6E5E4E3E2E1E0DEDDDCDBDA",
|
4068 |
|
|
INIT_35 => X"1E1D1C1B1A1918171514131211100F0E0D0C0B0A090706050403020100FFFEFD",
|
4069 |
|
|
INIT_36 => X"413F3E3D3C3B3A3938373635343331302F2E2D2C2B2A2928272625232221201F",
|
4070 |
|
|
INIT_37 => X"636261605F5E5D5B5A595857565554535251504F4D4C4B4A4948474645444342",
|
4071 |
|
|
INIT_38 => X"8584838281807F7E7D7C7B7A7977767574737271706F6E6D6C6B696867666564",
|
4072 |
|
|
INIT_39 => X"A8A7A6A5A3A2A1A09F9E9D9C9B9A9998979694939291908F8E8D8C8B8A898886",
|
4073 |
|
|
INIT_3A => X"CAC9C8C7C6C5C4C3C2C0BFBEBDBCBBBAB9B8B7B6B5B4B3B1B0AFAEADACABAAA9",
|
4074 |
|
|
INIT_3B => X"ECEBEAE9E8E7E6E5E4E3E2E1E0DEDDDCDBDAD9D8D7D6D5D4D3D2D1CFCECDCCCB",
|
4075 |
|
|
INIT_3C => X"0F0E0D0B0A09080706050403020100FFFEFCFBFAF9F8F7F6F5F4F3F2F1F0EFED",
|
4076 |
|
|
INIT_3D => X"31302F2E2D2C2A292827262524232221201F1E1D1B1A19181716151413121110",
|
4077 |
|
|
INIT_3E => X"535251504F4E4D4C4B494847464544434241403F3E3D3C3A3938373635343332",
|
4078 |
|
|
INIT_3F => X"7574737271706F6E6D6C6B696867666564636261605F5E5D5C5B595857565554",
|
4079 |
|
|
INIT_40 => X"97969594939291908F8E8D8C8B898887868584838281807F7E7D7C7B79787776",
|
4080 |
|
|
INIT_41 => X"B9B8B7B6B5B4B3B2B1B0AFAEADACABA9A8A7A6A5A4A3A2A1A09F9E9D9C9B9998",
|
4081 |
|
|
INIT_42 => X"DBDAD9D8D7D6D5D4D3D2D1D0CFCECDCCCAC9C8C7C6C5C4C3C2C1C0BFBEBDBCBA",
|
4082 |
|
|
INIT_43 => X"FDFCFBFAF9F8F7F6F5F4F3F2F1F0EFEEECEBEAE9E8E7E6E5E4E3E2E1E0DFDEDD",
|
4083 |
|
|
INIT_44 => X"1F1E1D1C1B1A191817161514131211100E0D0C0B0A09080706050403020100FF",
|
4084 |
|
|
INIT_45 => X"41403F3E3D3C3B3A3938373635343331302F2E2D2C2B2A292827262524232221",
|
4085 |
|
|
INIT_46 => X"636261605F5E5D5C5B5A5958575654535251504F4E4D4C4B4A49484746454442",
|
4086 |
|
|
INIT_47 => X"8584838281807F7E7D7C7B7A7877767574737271706F6E6D6C6B6A6968666564",
|
4087 |
|
|
INIT_48 => X"A7A6A5A4A3A2A1A09F9D9C9B9A999897969594939291908F8E8D8C8A89888786",
|
4088 |
|
|
INIT_49 => X"C9C8C7C6C5C4C2C1C0BFBEBDBCBBBAB9B8B7B6B5B4B3B2B0AFAEADACABAAA9A8",
|
4089 |
|
|
INIT_4A => X"EBE9E8E7E6E5E4E3E2E1E0DFDEDDDCDBDAD9D8D7D5D4D3D2D1D0CFCECDCCCBCA",
|
4090 |
|
|
INIT_4B => X"0C0B0A09080706050403020100FFFEFCFBFAF9F8F7F6F5F4F3F2F1F0EFEEEDEC",
|
4091 |
|
|
INIT_4C => X"2E2D2C2B2A2928272625232221201F1E1D1C1B1A1918171615141312100F0E0D",
|
4092 |
|
|
INIT_4D => X"504F4E4C4B4A494847464544434241403F3E3D3C3B3A3937363534333231302F",
|
4093 |
|
|
INIT_4E => X"71706F6E6D6C6B6A6968676665646362605F5E5D5C5B5A595857565554535251",
|
4094 |
|
|
INIT_4F => X"939291908F8E8D8C8A898887868584838281807F7E7D7C7B7A79787775747372",
|
4095 |
|
|
INIT_50 => X"B4B3B2B1B0AFAEADACABAAA9A8A7A6A5A4A3A2A09F9E9D9C9B9A999897969594",
|
4096 |
|
|
INIT_51 => X"D6D5D4D3D2D1D0CFCECDCBCAC9C8C7C6C5C4C3C2C1C0BFBEBDBCBBBAB9B8B7B5",
|
4097 |
|
|
INIT_52 => X"F7F6F5F4F3F2F1F0EFEEEDECEBEAE9E8E7E6E5E4E2E1E0DFDEDDDCDBDAD9D8D7",
|
4098 |
|
|
INIT_53 => X"1918171615141312110F0E0D0C0B0A09080706050403020100FFFEFDFCFBFAF8",
|
4099 |
|
|
INIT_54 => X"3A393837363534333231302F2E2D2C2B2A2928262524232221201F1E1D1C1B1A",
|
4100 |
|
|
INIT_55 => X"5C5B5A5958565554535251504F4E4D4C4B4A494847464544434241403E3D3C3B",
|
4101 |
|
|
INIT_56 => X"7D7C7B7A7978777675747372716F6E6D6C6B6A696867666564636261605F5E5D",
|
4102 |
|
|
INIT_57 => X"9E9D9C9B9A999897969594939291908F8E8D8C8B8A8887868584838281807F7E",
|
4103 |
|
|
INIT_58 => X"C0BFBEBDBBBAB9B8B7B6B5B4B3B2B1B0AFAEADACABAAA9A8A7A6A5A4A3A1A09F",
|
4104 |
|
|
INIT_59 => X"E1E0DFDEDDDCDBDAD9D8D7D5D4D3D2D1D0CFCECDCCCBCAC9C8C7C6C5C4C3C2C1",
|
4105 |
|
|
INIT_5A => X"020100FFFEFDFCFBFAF9F8F7F6F5F4F3F2F0EFEEEDECEBEAE9E8E7E6E5E4E3E2",
|
4106 |
|
|
INIT_5B => X"232221201F1E1D1C1B1A191817161514131211100F0E0C0B0A09080706050403",
|
4107 |
|
|
INIT_5C => X"44434241403F3E3D3C3B3A393837363534333231302F2E2D2C2B2A2827262524",
|
4108 |
|
|
INIT_5D => X"6665636261605F5E5D5C5B5A595857565554535251504F4E4D4C4B4A49484745",
|
4109 |
|
|
INIT_5E => X"878685848381807F7E7D7C7B7A797877767574737271706F6E6D6C6B6A696867",
|
4110 |
|
|
INIT_5F => X"A8A7A6A5A4A3A1A09F9E9D9C9B9A999897969594939291908F8E8D8C8B8A8988",
|
4111 |
|
|
INIT_60 => X"C9C8C7C6C5C4C3C1C0BFBEBDBCBBBAB9B8B7B6B5B4B3B2B1B0AFAEADACABAAA9",
|
4112 |
|
|
INIT_61 => X"EAE9E8E7E6E5E4E2E1E0DFDEDDDCDBDAD9D8D7D6D5D4D3D2D1D0CFCECDCCCBCA",
|
4113 |
|
|
INIT_62 => X"0B0A090807050403020100FFFEFDFCFBFAF9F8F7F6F5F4F3F2F1F0EFEEEDECEB",
|
4114 |
|
|
INIT_63 => X"2C2B292827262524232221201F1E1D1C1B1A191817161514131211100F0E0D0C",
|
4115 |
|
|
INIT_64 => X"4C4B4A494847464544434241403F3E3D3C3B3A393837363534333231302F2E2D",
|
4116 |
|
|
INIT_65 => X"6D6C6B6A696867666564636261605F5E5D5C5B5A595857565554535251504E4D",
|
4117 |
|
|
INIT_66 => X"8E8D8C8B8A898887868584838281807F7E7D7C7B7A7978777574737271706F6E",
|
4118 |
|
|
INIT_67 => X"AFAEADACABAAA9A8A7A6A5A4A3A2A1A09F9D9C9B9A999897969594939291908F",
|
4119 |
|
|
INIT_68 => X"D0CFCECDCCCBCAC8C7C6C5C4C3C2C1C0BFBEBDBCBBBAB9B8B7B6B5B4B3B2B1B0",
|
4120 |
|
|
INIT_69 => X"F0EFEEEDECEBEAE9E8E7E6E5E4E3E2E1E0DFDEDDDCDBDAD9D8D7D6D5D4D3D2D1",
|
4121 |
|
|
INIT_6A => X"11100F0E0D0C0B0A09080706050403020100FFFEFDFCFBFAF9F8F6F5F4F3F2F1",
|
4122 |
|
|
INIT_6B => X"3231302F2E2D2C2B2A2928262524232221201F1E1D1C1B1A1918171615141312",
|
4123 |
|
|
INIT_6C => X"5251504F4E4D4C4B4A494847464544434241403F3E3D3C3B3A39383736353433",
|
4124 |
|
|
INIT_6D => X"737271706F6E6D6C6B6A696867666564636261605F5E5D5B5A59585756555453",
|
4125 |
|
|
INIT_6E => X"939291908F8E8D8C8B8A898887868584838281807F7E7D7C7B7A797877767574",
|
4126 |
|
|
INIT_6F => X"B4B3B2B1B0AFAEADACABAAA9A8A7A6A5A4A3A2A1A09F9E9D9C9B9A9998979694",
|
4127 |
|
|
INIT_70 => X"D4D3D2D1D0CFCECDCCCBCAC9C8C7C6C5C4C3C2C1C0BFBEBDBCBBBAB9B8B7B6B5",
|
4128 |
|
|
INIT_71 => X"F5F4F3F2F1F0EFEEEDECEBEAE9E8E7E6E5E4E3E2E1E0DFDEDDDCDBDAD9D8D7D6",
|
4129 |
|
|
INIT_72 => X"1514131211100F0E0D0C0B0A09080706050403020100FFFEFDFCFBFAF9F8F7F6",
|
4130 |
|
|
INIT_73 => X"363534333231302F2E2D2C2B2A292827262524232221201E1D1C1B1A19181716",
|
4131 |
|
|
INIT_74 => X"565554535251504F4E4D4C4B4A494847464544434241403F3E3D3C3B3A393837",
|
4132 |
|
|
INIT_75 => X"767574737271706F6E6D6C6B6A696867666564636261605F5E5D5C5B5A595857",
|
4133 |
|
|
INIT_76 => X"97969594939291908F8E8D8C8B8A898887868584838281807F7E7D7C7B797877",
|
4134 |
|
|
INIT_77 => X"B7B6B5B4B3B2B1B0AFAEADACABAAA9A8A7A6A5A4A3A2A1A09F9E9D9C9B9A9998",
|
4135 |
|
|
INIT_78 => X"D7D6D5D4D3D2D1D0CFCECDCCCBCAC9C8C7C6C5C4C3C2C1C0BFBEBDBCBBBAB9B8",
|
4136 |
|
|
INIT_79 => X"F7F6F5F4F3F2F1F0EFEEEDECEBEAE9E8E7E6E5E4E3E2E1E0DFDEDDDCDBDAD9D8",
|
4137 |
|
|
INIT_7A => X"1817161514131211100F0E0D0C0B0A09080706050403020100FFFEFDFCFAF9F8",
|
4138 |
|
|
INIT_7B => X"3837363534333231302F2E2D2C2B2A292827262524232221201F1E1D1C1B1A19",
|
4139 |
|
|
INIT_7C => X"5857565554535251504F4E4D4C4B4A494847464544434241403F3E3D3C3B3A39",
|
4140 |
|
|
INIT_7D => X"7877767574737271706F6E6D6C6B6A696867666564636261605F5E5D5C5B5A59",
|
4141 |
|
|
INITP_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC000000000000000000",
|
4142 |
|
|
INIT_FILE => "NONE",
|
4143 |
|
|
RAM_EXTENSION_A => "NONE",
|
4144 |
|
|
RAM_EXTENSION_B => "NONE",
|
4145 |
|
|
READ_WIDTH_A => 9,
|
4146 |
|
|
READ_WIDTH_B => 9,
|
4147 |
|
|
SIM_COLLISION_CHECK => "ALL",
|
4148 |
|
|
SIM_MODE => "SAFE",
|
4149 |
|
|
INIT_A => X"000000000",
|
4150 |
|
|
INIT_B => X"000000000",
|
4151 |
|
|
WRITE_MODE_A => "WRITE_FIRST",
|
4152 |
|
|
WRITE_MODE_B => "WRITE_FIRST",
|
4153 |
|
|
WRITE_WIDTH_A => 9,
|
4154 |
|
|
WRITE_WIDTH_B => 9,
|
4155 |
|
|
INITP_0F => X"00000000000000000000000000000000000000000000007FFFFFFFFFFFFFFFFF"
|
4156 |
|
|
)
|
4157 |
|
|
port map (
|
4158 |
|
|
ENAU => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_3_cmp_eq0000,
|
4159 |
|
|
ENAL => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_3_cmp_eq0000,
|
4160 |
|
|
ENBU => BU2_doutb(0),
|
4161 |
|
|
ENBL => BU2_doutb(0),
|
4162 |
|
|
SSRAU => BU2_doutb(0),
|
4163 |
|
|
SSRAL => BU2_doutb(0),
|
4164 |
|
|
SSRBU => BU2_doutb(0),
|
4165 |
|
|
SSRBL => BU2_doutb(0),
|
4166 |
|
|
CLKAU => clka,
|
4167 |
|
|
CLKAL => clka,
|
4168 |
|
|
CLKBU => BU2_doutb(0),
|
4169 |
|
|
CLKBL => BU2_doutb(0),
|
4170 |
|
|
REGCLKAU => clka,
|
4171 |
|
|
REGCLKAL => clka,
|
4172 |
|
|
REGCLKBU => BU2_doutb(0),
|
4173 |
|
|
REGCLKBL => BU2_doutb(0),
|
4174 |
|
|
REGCEAU => BU2_doutb(0),
|
4175 |
|
|
REGCEAL => BU2_doutb(0),
|
4176 |
|
|
REGCEBU => BU2_doutb(0),
|
4177 |
|
|
REGCEBL => BU2_doutb(0),
|
4178 |
|
|
CASCADEINLATA => BU2_doutb(0),
|
4179 |
|
|
CASCADEINLATB => BU2_doutb(0),
|
4180 |
|
|
CASCADEINREGA => BU2_doutb(0),
|
4181 |
|
|
CASCADEINREGB => BU2_doutb(0),
|
4182 |
|
|
CASCADEOUTLATA => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATA_UNCONNECTED,
|
4183 |
|
|
CASCADEOUTLATB => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATB_UNCONNECTED,
|
4184 |
|
|
CASCADEOUTREGA => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGA_UNCONNECTED,
|
4185 |
|
|
CASCADEOUTREGB => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGB_UNCONNECTED,
|
4186 |
|
|
DIA(31) => BU2_doutb(0),
|
4187 |
|
|
DIA(30) => BU2_doutb(0),
|
4188 |
|
|
DIA(29) => BU2_doutb(0),
|
4189 |
|
|
DIA(28) => BU2_doutb(0),
|
4190 |
|
|
DIA(27) => BU2_doutb(0),
|
4191 |
|
|
DIA(26) => BU2_doutb(0),
|
4192 |
|
|
DIA(25) => BU2_doutb(0),
|
4193 |
|
|
DIA(24) => BU2_doutb(0),
|
4194 |
|
|
DIA(23) => BU2_doutb(0),
|
4195 |
|
|
DIA(22) => BU2_doutb(0),
|
4196 |
|
|
DIA(21) => BU2_doutb(0),
|
4197 |
|
|
DIA(20) => BU2_doutb(0),
|
4198 |
|
|
DIA(19) => BU2_doutb(0),
|
4199 |
|
|
DIA(18) => BU2_doutb(0),
|
4200 |
|
|
DIA(17) => BU2_doutb(0),
|
4201 |
|
|
DIA(16) => BU2_doutb(0),
|
4202 |
|
|
DIA(15) => BU2_doutb(0),
|
4203 |
|
|
DIA(14) => BU2_doutb(0),
|
4204 |
|
|
DIA(13) => BU2_doutb(0),
|
4205 |
|
|
DIA(12) => BU2_doutb(0),
|
4206 |
|
|
DIA(11) => BU2_doutb(0),
|
4207 |
|
|
DIA(10) => BU2_doutb(0),
|
4208 |
|
|
DIA(9) => BU2_doutb(0),
|
4209 |
|
|
DIA(8) => BU2_doutb(0),
|
4210 |
|
|
DIA(7) => BU2_doutb(0),
|
4211 |
|
|
DIA(6) => BU2_doutb(0),
|
4212 |
|
|
DIA(5) => BU2_doutb(0),
|
4213 |
|
|
DIA(4) => BU2_doutb(0),
|
4214 |
|
|
DIA(3) => BU2_doutb(0),
|
4215 |
|
|
DIA(2) => BU2_doutb(0),
|
4216 |
|
|
DIA(1) => BU2_doutb(0),
|
4217 |
|
|
DIA(0) => BU2_doutb(0),
|
4218 |
|
|
DIPA(3) => BU2_doutb(0),
|
4219 |
|
|
DIPA(2) => BU2_doutb(0),
|
4220 |
|
|
DIPA(1) => BU2_doutb(0),
|
4221 |
|
|
DIPA(0) => BU2_doutb(0),
|
4222 |
|
|
DIB(31) => BU2_doutb(0),
|
4223 |
|
|
DIB(30) => BU2_doutb(0),
|
4224 |
|
|
DIB(29) => BU2_doutb(0),
|
4225 |
|
|
DIB(28) => BU2_doutb(0),
|
4226 |
|
|
DIB(27) => BU2_doutb(0),
|
4227 |
|
|
DIB(26) => BU2_doutb(0),
|
4228 |
|
|
DIB(25) => BU2_doutb(0),
|
4229 |
|
|
DIB(24) => BU2_doutb(0),
|
4230 |
|
|
DIB(23) => BU2_doutb(0),
|
4231 |
|
|
DIB(22) => BU2_doutb(0),
|
4232 |
|
|
DIB(21) => BU2_doutb(0),
|
4233 |
|
|
DIB(20) => BU2_doutb(0),
|
4234 |
|
|
DIB(19) => BU2_doutb(0),
|
4235 |
|
|
DIB(18) => BU2_doutb(0),
|
4236 |
|
|
DIB(17) => BU2_doutb(0),
|
4237 |
|
|
DIB(16) => BU2_doutb(0),
|
4238 |
|
|
DIB(15) => BU2_doutb(0),
|
4239 |
|
|
DIB(14) => BU2_doutb(0),
|
4240 |
|
|
DIB(13) => BU2_doutb(0),
|
4241 |
|
|
DIB(12) => BU2_doutb(0),
|
4242 |
|
|
DIB(11) => BU2_doutb(0),
|
4243 |
|
|
DIB(10) => BU2_doutb(0),
|
4244 |
|
|
DIB(9) => BU2_doutb(0),
|
4245 |
|
|
DIB(8) => BU2_doutb(0),
|
4246 |
|
|
DIB(7) => BU2_doutb(0),
|
4247 |
|
|
DIB(6) => BU2_doutb(0),
|
4248 |
|
|
DIB(5) => BU2_doutb(0),
|
4249 |
|
|
DIB(4) => BU2_doutb(0),
|
4250 |
|
|
DIB(3) => BU2_doutb(0),
|
4251 |
|
|
DIB(2) => BU2_doutb(0),
|
4252 |
|
|
DIB(1) => BU2_doutb(0),
|
4253 |
|
|
DIB(0) => BU2_doutb(0),
|
4254 |
|
|
DIPB(3) => BU2_doutb(0),
|
4255 |
|
|
DIPB(2) => BU2_doutb(0),
|
4256 |
|
|
DIPB(1) => BU2_doutb(0),
|
4257 |
|
|
DIPB(0) => BU2_doutb(0),
|
4258 |
|
|
ADDRAL(15) => BU2_doutb(0),
|
4259 |
|
|
ADDRAL(14) => addra_2(11),
|
4260 |
|
|
ADDRAL(13) => addra_2(10),
|
4261 |
|
|
ADDRAL(12) => addra_2(9),
|
4262 |
|
|
ADDRAL(11) => addra_2(8),
|
4263 |
|
|
ADDRAL(10) => addra_2(7),
|
4264 |
|
|
ADDRAL(9) => addra_2(6),
|
4265 |
|
|
ADDRAL(8) => addra_2(5),
|
4266 |
|
|
ADDRAL(7) => addra_2(4),
|
4267 |
|
|
ADDRAL(6) => addra_2(3),
|
4268 |
|
|
ADDRAL(5) => addra_2(2),
|
4269 |
|
|
ADDRAL(4) => addra_2(1),
|
4270 |
|
|
ADDRAL(3) => addra_2(0),
|
4271 |
|
|
ADDRAL(2) => BU2_doutb(0),
|
4272 |
|
|
ADDRAL(1) => BU2_doutb(0),
|
4273 |
|
|
ADDRAL(0) => BU2_doutb(0),
|
4274 |
|
|
ADDRAU(14) => addra_2(11),
|
4275 |
|
|
ADDRAU(13) => addra_2(10),
|
4276 |
|
|
ADDRAU(12) => addra_2(9),
|
4277 |
|
|
ADDRAU(11) => addra_2(8),
|
4278 |
|
|
ADDRAU(10) => addra_2(7),
|
4279 |
|
|
ADDRAU(9) => addra_2(6),
|
4280 |
|
|
ADDRAU(8) => addra_2(5),
|
4281 |
|
|
ADDRAU(7) => addra_2(4),
|
4282 |
|
|
ADDRAU(6) => addra_2(3),
|
4283 |
|
|
ADDRAU(5) => addra_2(2),
|
4284 |
|
|
ADDRAU(4) => addra_2(1),
|
4285 |
|
|
ADDRAU(3) => addra_2(0),
|
4286 |
|
|
ADDRAU(2) => BU2_doutb(0),
|
4287 |
|
|
ADDRAU(1) => BU2_doutb(0),
|
4288 |
|
|
ADDRAU(0) => BU2_doutb(0),
|
4289 |
|
|
ADDRBL(15) => BU2_doutb(0),
|
4290 |
|
|
ADDRBL(14) => BU2_doutb(0),
|
4291 |
|
|
ADDRBL(13) => BU2_doutb(0),
|
4292 |
|
|
ADDRBL(12) => BU2_doutb(0),
|
4293 |
|
|
ADDRBL(11) => BU2_doutb(0),
|
4294 |
|
|
ADDRBL(10) => BU2_doutb(0),
|
4295 |
|
|
ADDRBL(9) => BU2_doutb(0),
|
4296 |
|
|
ADDRBL(8) => BU2_doutb(0),
|
4297 |
|
|
ADDRBL(7) => BU2_doutb(0),
|
4298 |
|
|
ADDRBL(6) => BU2_doutb(0),
|
4299 |
|
|
ADDRBL(5) => BU2_doutb(0),
|
4300 |
|
|
ADDRBL(4) => BU2_doutb(0),
|
4301 |
|
|
ADDRBL(3) => BU2_doutb(0),
|
4302 |
|
|
ADDRBL(2) => BU2_doutb(0),
|
4303 |
|
|
ADDRBL(1) => BU2_doutb(0),
|
4304 |
|
|
ADDRBL(0) => BU2_doutb(0),
|
4305 |
|
|
ADDRBU(14) => BU2_doutb(0),
|
4306 |
|
|
ADDRBU(13) => BU2_doutb(0),
|
4307 |
|
|
ADDRBU(12) => BU2_doutb(0),
|
4308 |
|
|
ADDRBU(11) => BU2_doutb(0),
|
4309 |
|
|
ADDRBU(10) => BU2_doutb(0),
|
4310 |
|
|
ADDRBU(9) => BU2_doutb(0),
|
4311 |
|
|
ADDRBU(8) => BU2_doutb(0),
|
4312 |
|
|
ADDRBU(7) => BU2_doutb(0),
|
4313 |
|
|
ADDRBU(6) => BU2_doutb(0),
|
4314 |
|
|
ADDRBU(5) => BU2_doutb(0),
|
4315 |
|
|
ADDRBU(4) => BU2_doutb(0),
|
4316 |
|
|
ADDRBU(3) => BU2_doutb(0),
|
4317 |
|
|
ADDRBU(2) => BU2_doutb(0),
|
4318 |
|
|
ADDRBU(1) => BU2_doutb(0),
|
4319 |
|
|
ADDRBU(0) => BU2_doutb(0),
|
4320 |
|
|
WEAU(3) => BU2_doutb(0),
|
4321 |
|
|
WEAU(2) => BU2_doutb(0),
|
4322 |
|
|
WEAU(1) => BU2_doutb(0),
|
4323 |
|
|
WEAU(0) => BU2_doutb(0),
|
4324 |
|
|
WEAL(3) => BU2_doutb(0),
|
4325 |
|
|
WEAL(2) => BU2_doutb(0),
|
4326 |
|
|
WEAL(1) => BU2_doutb(0),
|
4327 |
|
|
WEAL(0) => BU2_doutb(0),
|
4328 |
|
|
WEBU(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_7_UNCONNECTED,
|
4329 |
|
|
WEBU(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_6_UNCONNECTED,
|
4330 |
|
|
WEBU(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_5_UNCONNECTED,
|
4331 |
|
|
WEBU(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_4_UNCONNECTED,
|
4332 |
|
|
WEBU(3) => BU2_doutb(0),
|
4333 |
|
|
WEBU(2) => BU2_doutb(0),
|
4334 |
|
|
WEBU(1) => BU2_doutb(0),
|
4335 |
|
|
WEBU(0) => BU2_doutb(0),
|
4336 |
|
|
WEBL(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_7_UNCONNECTED,
|
4337 |
|
|
WEBL(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_6_UNCONNECTED,
|
4338 |
|
|
WEBL(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_5_UNCONNECTED,
|
4339 |
|
|
WEBL(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_4_UNCONNECTED,
|
4340 |
|
|
WEBL(3) => BU2_doutb(0),
|
4341 |
|
|
WEBL(2) => BU2_doutb(0),
|
4342 |
|
|
WEBL(1) => BU2_doutb(0),
|
4343 |
|
|
WEBL(0) => BU2_doutb(0),
|
4344 |
|
|
DOA(31) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_31_UNCONNECTED,
|
4345 |
|
|
DOA(30) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_30_UNCONNECTED,
|
4346 |
|
|
DOA(29) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_29_UNCONNECTED,
|
4347 |
|
|
DOA(28) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_28_UNCONNECTED,
|
4348 |
|
|
DOA(27) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_27_UNCONNECTED,
|
4349 |
|
|
DOA(26) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_26_UNCONNECTED,
|
4350 |
|
|
DOA(25) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_25_UNCONNECTED,
|
4351 |
|
|
DOA(24) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_24_UNCONNECTED,
|
4352 |
|
|
DOA(23) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_23_UNCONNECTED,
|
4353 |
|
|
DOA(22) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_22_UNCONNECTED,
|
4354 |
|
|
DOA(21) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_21_UNCONNECTED,
|
4355 |
|
|
DOA(20) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_20_UNCONNECTED,
|
4356 |
|
|
DOA(19) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_19_UNCONNECTED,
|
4357 |
|
|
DOA(18) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_18_UNCONNECTED,
|
4358 |
|
|
DOA(17) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_17_UNCONNECTED,
|
4359 |
|
|
DOA(16) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_16_UNCONNECTED,
|
4360 |
|
|
DOA(15) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_15_UNCONNECTED,
|
4361 |
|
|
DOA(14) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_14_UNCONNECTED,
|
4362 |
|
|
DOA(13) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_13_UNCONNECTED,
|
4363 |
|
|
DOA(12) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_12_UNCONNECTED,
|
4364 |
|
|
DOA(11) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_11_UNCONNECTED,
|
4365 |
|
|
DOA(10) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_10_UNCONNECTED,
|
4366 |
|
|
DOA(9) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_9_UNCONNECTED,
|
4367 |
|
|
DOA(8) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_8_UNCONNECTED,
|
4368 |
|
|
DOA(7) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta6(7),
|
4369 |
|
|
DOA(6) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta6(6),
|
4370 |
|
|
DOA(5) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta6(5),
|
4371 |
|
|
DOA(4) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta6(4),
|
4372 |
|
|
DOA(3) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta6(3),
|
4373 |
|
|
DOA(2) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta6(2),
|
4374 |
|
|
DOA(1) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta6(1),
|
4375 |
|
|
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta6(0),
|
4376 |
|
|
DOPA(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_3_UNCONNECTED,
|
4377 |
|
|
DOPA(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_2_UNCONNECTED,
|
4378 |
|
|
DOPA(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_1_UNCONNECTED,
|
4379 |
|
|
DOPA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta6(8),
|
4380 |
|
|
DOB(31) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_31_UNCONNECTED,
|
4381 |
|
|
DOB(30) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_30_UNCONNECTED,
|
4382 |
|
|
DOB(29) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_29_UNCONNECTED,
|
4383 |
|
|
DOB(28) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_28_UNCONNECTED,
|
4384 |
|
|
DOB(27) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_27_UNCONNECTED,
|
4385 |
|
|
DOB(26) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_26_UNCONNECTED,
|
4386 |
|
|
DOB(25) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_25_UNCONNECTED,
|
4387 |
|
|
DOB(24) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_24_UNCONNECTED,
|
4388 |
|
|
DOB(23) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_23_UNCONNECTED,
|
4389 |
|
|
DOB(22) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_22_UNCONNECTED,
|
4390 |
|
|
DOB(21) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_21_UNCONNECTED,
|
4391 |
|
|
DOB(20) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_20_UNCONNECTED,
|
4392 |
|
|
DOB(19) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_19_UNCONNECTED,
|
4393 |
|
|
DOB(18) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_18_UNCONNECTED,
|
4394 |
|
|
DOB(17) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_17_UNCONNECTED,
|
4395 |
|
|
DOB(16) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_16_UNCONNECTED,
|
4396 |
|
|
DOB(15) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_15_UNCONNECTED,
|
4397 |
|
|
DOB(14) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_14_UNCONNECTED,
|
4398 |
|
|
DOB(13) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_13_UNCONNECTED,
|
4399 |
|
|
DOB(12) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_12_UNCONNECTED,
|
4400 |
|
|
DOB(11) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_11_UNCONNECTED,
|
4401 |
|
|
DOB(10) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_10_UNCONNECTED,
|
4402 |
|
|
DOB(9) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_9_UNCONNECTED,
|
4403 |
|
|
DOB(8) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_8_UNCONNECTED,
|
4404 |
|
|
DOB(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_7_UNCONNECTED,
|
4405 |
|
|
DOB(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_6_UNCONNECTED,
|
4406 |
|
|
DOB(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_5_UNCONNECTED,
|
4407 |
|
|
DOB(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_4_UNCONNECTED,
|
4408 |
|
|
DOB(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_3_UNCONNECTED,
|
4409 |
|
|
DOB(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_2_UNCONNECTED,
|
4410 |
|
|
DOB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_1_UNCONNECTED,
|
4411 |
|
|
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_0_UNCONNECTED,
|
4412 |
|
|
DOPB(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_3_UNCONNECTED,
|
4413 |
|
|
DOPB(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_2_UNCONNECTED,
|
4414 |
|
|
DOPB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_1_UNCONNECTED,
|
4415 |
|
|
DOPB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_0_UNCONNECTED
|
4416 |
|
|
);
|
4417 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP : RAMB36_EXP
|
4418 |
|
|
generic map(
|
4419 |
|
|
DOA_REG => 0,
|
4420 |
|
|
DOB_REG => 0,
|
4421 |
|
|
INIT_7E => X"9898989898989898989898989898989898989898989898989898989898989898",
|
4422 |
|
|
INIT_7F => X"9999999999999999999998989898989898989898989898989898989898989898",
|
4423 |
|
|
INITP_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000000000000000000000000000001",
|
4424 |
|
|
INITP_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4425 |
|
|
INITP_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4426 |
|
|
INITP_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4427 |
|
|
INITP_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4428 |
|
|
INITP_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4429 |
|
|
INITP_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4430 |
|
|
INITP_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4431 |
|
|
INITP_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4432 |
|
|
INITP_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4433 |
|
|
INITP_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4434 |
|
|
INITP_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4435 |
|
|
INITP_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4436 |
|
|
INITP_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4437 |
|
|
SRVAL_A => X"000000000",
|
4438 |
|
|
SRVAL_B => X"000000000",
|
4439 |
|
|
INIT_00 => X"BEBCBAB8B6B4B2B0AEACAAA8A6A4A2A09D9995918D8985817B736B6357472FFF",
|
4440 |
|
|
INIT_01 => X"DFDEDDDCDBDAD9D8D7D6D5D4D3D2D1D0CFCECDCCCBCAC9C8C7C6C5C4C3C2C1C0",
|
4441 |
|
|
INIT_02 => X"EFEFEEEEEDEDECECEBEBEAEAE9E9E8E8E7E7E6E6E5E5E4E4E3E3E2E2E1E1E0E0",
|
4442 |
|
|
INIT_03 => X"FFFFFEFEFDFDFCFCFBFBFAFAF9F9F8F8F7F7F6F6F5F5F4F4F3F3F2F2F1F1F0F0",
|
4443 |
|
|
INIT_04 => X"07070706060606050505050404040403030303020202020101010100000000FF",
|
4444 |
|
|
INIT_05 => X"0F0F0F0E0E0E0E0D0D0D0D0C0C0C0C0B0B0B0B0A0A0A0A090909090808080807",
|
4445 |
|
|
INIT_06 => X"171717161616161515151514141414131313131212121211111111101010100F",
|
4446 |
|
|
INIT_07 => X"1F1F1E1E1E1E1D1D1D1D1C1C1C1C1B1B1B1B1A1A1A1A19191919181818181717",
|
4447 |
|
|
INIT_08 => X"2323232323232222222222222222212121212121212120202020202020201F1F",
|
4448 |
|
|
INIT_09 => X"2727272727262626262626262625252525252525252424242424242424232323",
|
4449 |
|
|
INIT_0A => X"2B2B2B2B2A2A2A2A2A2A2A2A2A29292929292929292828282828282828272727",
|
4450 |
|
|
INIT_0B => X"2F2F2F2F2E2E2E2E2E2E2E2E2D2D2D2D2D2D2D2D2C2C2C2C2C2C2C2C2B2B2B2B",
|
4451 |
|
|
INIT_0C => X"3333333232323232323232313131313131313130303030303030302F2F2F2F2F",
|
4452 |
|
|
INIT_0D => X"3737363636363636363635353535353535353434343434343434343333333333",
|
4453 |
|
|
INIT_0E => X"3B3A3A3A3A3A3A3A3A3939393939393939393838383838383838373737373737",
|
4454 |
|
|
INIT_0F => X"3E3E3E3E3E3E3E3E3D3D3D3D3D3D3D3D3D3C3C3C3C3C3C3C3C3B3B3B3B3B3B3B",
|
4455 |
|
|
INIT_10 => X"4141414141414140404040404040404040404040404040403F3F3F3F3F3F3F3F",
|
4456 |
|
|
INIT_11 => X"4343434343434242424242424242424242424242424242414141414141414141",
|
4457 |
|
|
INIT_12 => X"4545454545444444444444444444444444444444444443434343434343434343",
|
4458 |
|
|
INIT_13 => X"4747474746464646464646464646464646464646464545454545454545454545",
|
4459 |
|
|
INIT_14 => X"4949494848484848484848484848484848484847474747474747474747474747",
|
4460 |
|
|
INIT_15 => X"4B4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4949494949494949494949494949",
|
4461 |
|
|
INIT_16 => X"4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B",
|
4462 |
|
|
INIT_17 => X"4E4E4E4E4E4E4E4E4E4E4E4E4E4E4E4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D4D",
|
4463 |
|
|
INIT_18 => X"50505050505050505050505050504F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4E4E",
|
4464 |
|
|
INIT_19 => X"5252525252525252525252525151515151515151515151515151515151505050",
|
4465 |
|
|
INIT_1A => X"5454545454545454545454535353535353535353535353535353535252525252",
|
4466 |
|
|
INIT_1B => X"5656565656565656565555555555555555555555555555555555545454545454",
|
4467 |
|
|
INIT_1C => X"5858585858585857575757575757575757575757575757575656565656565656",
|
4468 |
|
|
INIT_1D => X"5A5A5A5A5A595959595959595959595959595959595958585858585858585858",
|
4469 |
|
|
INIT_1E => X"5C5C5C5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5A5A5A5A5A5A5A5A5A5A5A5A",
|
4470 |
|
|
INIT_1F => X"5E5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5D5C5C5C5C5C5C5C5C5C5C5C5C5C5C",
|
4471 |
|
|
INIT_20 => X"5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5F5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E5E",
|
4472 |
|
|
INIT_21 => X"606060606060606060606060606060606060606060606060606060606060605F",
|
4473 |
|
|
INIT_22 => X"6161616161616161616161616161616161616161616161616161616161606060",
|
4474 |
|
|
INIT_23 => X"6262626262626262626262626262626262626262626262626262626161616161",
|
4475 |
|
|
INIT_24 => X"6363636363636363636363636363636363636363636363636362626262626262",
|
4476 |
|
|
INIT_25 => X"6464646464646464646464646464646464646464646464636363636363636363",
|
4477 |
|
|
INIT_26 => X"6565656565656565656565656565656565656565646464646464646464646464",
|
4478 |
|
|
INIT_27 => X"6666666666666666666666666666666666666565656565656565656565656565",
|
4479 |
|
|
INIT_28 => X"6767676767676767676767676767676666666666666666666666666666666666",
|
4480 |
|
|
INIT_29 => X"6868686868686868686868686867676767676767676767676767676767676767",
|
4481 |
|
|
INIT_2A => X"6969696969696969696968686868686868686868686868686868686868686868",
|
4482 |
|
|
INIT_2B => X"6A6A6A6A6A6A6A69696969696969696969696969696969696969696969696969",
|
4483 |
|
|
INIT_2C => X"6B6B6B6B6B6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A",
|
4484 |
|
|
INIT_2D => X"6C6C6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B",
|
4485 |
|
|
INIT_2E => X"6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C",
|
4486 |
|
|
INIT_2F => X"6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6C",
|
4487 |
|
|
INIT_30 => X"6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6D6D6D6D",
|
4488 |
|
|
INIT_31 => X"6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6F6E6E6E6E6E6E6E",
|
4489 |
|
|
INIT_32 => X"707070707070707070707070707070707070707070706F6F6F6F6F6F6F6F6F6F",
|
4490 |
|
|
INIT_33 => X"7171717171717171717171717171717171717170707070707070707070707070",
|
4491 |
|
|
INIT_34 => X"7272727272727272727272727272727171717171717171717171717171717171",
|
4492 |
|
|
INIT_35 => X"7373737373737373737373737272727272727272727272727272727272727272",
|
4493 |
|
|
INIT_36 => X"7474747474747474747373737373737373737373737373737373737373737373",
|
4494 |
|
|
INIT_37 => X"7575757575747474747474747474747474747474747474747474747474747474",
|
4495 |
|
|
INIT_38 => X"7676757575757575757575757575757575757575757575757575757575757575",
|
4496 |
|
|
INIT_39 => X"7676767676767676767676767676767676767676767676767676767676767676",
|
4497 |
|
|
INIT_3A => X"7777777777777777777777777777777777777777777777777777777777777676",
|
4498 |
|
|
INIT_3B => X"7878787878787878787878787878787878787878787878787878777777777777",
|
4499 |
|
|
INIT_3C => X"7979797979797979797979797979797979797979797979787878787878787878",
|
4500 |
|
|
INIT_3D => X"7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A79797979797979797979797979",
|
4501 |
|
|
INIT_3E => X"7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A",
|
4502 |
|
|
INIT_3F => X"7C7C7C7C7C7C7C7C7C7C7C7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B",
|
4503 |
|
|
INIT_40 => X"7D7D7D7D7D7D7D7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C",
|
4504 |
|
|
INIT_41 => X"7E7E7E7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D",
|
4505 |
|
|
INIT_42 => X"7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E",
|
4506 |
|
|
INIT_43 => X"7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7E",
|
4507 |
|
|
INIT_44 => X"80808080808080808080808080808080808080808080808080807F7F7F7F7F7F",
|
4508 |
|
|
INIT_45 => X"8080808080808080808080808080808080808080808080808080808080808080",
|
4509 |
|
|
INIT_46 => X"8181818181818181818181818181818181818080808080808080808080808080",
|
4510 |
|
|
INIT_47 => X"8181818181818181818181818181818181818181818181818181818181818181",
|
4511 |
|
|
INIT_48 => X"8282828282828282828181818181818181818181818181818181818181818181",
|
4512 |
|
|
INIT_49 => X"8282828282828282828282828282828282828282828282828282828282828282",
|
4513 |
|
|
INIT_4A => X"8282828282828282828282828282828282828282828282828282828282828282",
|
4514 |
|
|
INIT_4B => X"8383838383838383838383838383838383838383838383838383838383838383",
|
4515 |
|
|
INIT_4C => X"8383838383838383838383838383838383838383838383838383838383838383",
|
4516 |
|
|
INIT_4D => X"8484848484848484848484848484848484848484848483838383838383838383",
|
4517 |
|
|
INIT_4E => X"8484848484848484848484848484848484848484848484848484848484848484",
|
4518 |
|
|
INIT_4F => X"8585858585858585858585858484848484848484848484848484848484848484",
|
4519 |
|
|
INIT_50 => X"8585858585858585858585858585858585858585858585858585858585858585",
|
4520 |
|
|
INIT_51 => X"8686858585858585858585858585858585858585858585858585858585858585",
|
4521 |
|
|
INIT_52 => X"8686868686868686868686868686868686868686868686868686868686868686",
|
4522 |
|
|
INIT_53 => X"8686868686868686868686868686868686868686868686868686868686868686",
|
4523 |
|
|
INIT_54 => X"8787878787878787878787878787878787878787878787878686868686868686",
|
4524 |
|
|
INIT_55 => X"8787878787878787878787878787878787878787878787878787878787878787",
|
4525 |
|
|
INIT_56 => X"8888888888888888888888888887878787878787878787878787878787878787",
|
4526 |
|
|
INIT_57 => X"8888888888888888888888888888888888888888888888888888888888888888",
|
4527 |
|
|
INIT_58 => X"8989888888888888888888888888888888888888888888888888888888888888",
|
4528 |
|
|
INIT_59 => X"8989898989898989898989898989898989898989898989898989898989898989",
|
4529 |
|
|
INIT_5A => X"8989898989898989898989898989898989898989898989898989898989898989",
|
4530 |
|
|
INIT_5B => X"8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A898989898989898989",
|
4531 |
|
|
INIT_5C => X"8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A",
|
4532 |
|
|
INIT_5D => X"8B8B8B8B8B8B8B8B8B8B8B8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A",
|
4533 |
|
|
INIT_5E => X"8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B",
|
4534 |
|
|
INIT_5F => X"8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B",
|
4535 |
|
|
INIT_60 => X"8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C",
|
4536 |
|
|
INIT_61 => X"8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C",
|
4537 |
|
|
INIT_62 => X"8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8C8C8C8C8C8C8C8C8C8C8C8C8C",
|
4538 |
|
|
INIT_63 => X"8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D",
|
4539 |
|
|
INIT_64 => X"8E8E8E8E8E8E8E8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D8D",
|
4540 |
|
|
INIT_65 => X"8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E",
|
4541 |
|
|
INIT_66 => X"8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E8E",
|
4542 |
|
|
INIT_67 => X"8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8E8E8E8E8E8E",
|
4543 |
|
|
INIT_68 => X"8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F",
|
4544 |
|
|
INIT_69 => X"909090909090909090909090908F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F8F",
|
4545 |
|
|
INIT_6A => X"9090909090909090909090909090909090909090909090909090909090909090",
|
4546 |
|
|
INIT_6B => X"9090909090909090909090909090909090909090909090909090909090909090",
|
4547 |
|
|
INIT_6C => X"9191919191919191919191919191919191919191919191919191919191919191",
|
4548 |
|
|
INIT_6D => X"9191919191919191919191919191919191919191919191919191919191919191",
|
4549 |
|
|
INIT_6E => X"9292929292929292929292929292929292929191919191919191919191919191",
|
4550 |
|
|
INIT_6F => X"9292929292929292929292929292929292929292929292929292929292929292",
|
4551 |
|
|
INIT_70 => X"9393939392929292929292929292929292929292929292929292929292929292",
|
4552 |
|
|
INIT_71 => X"9393939393939393939393939393939393939393939393939393939393939393",
|
4553 |
|
|
INIT_72 => X"9393939393939393939393939393939393939393939393939393939393939393",
|
4554 |
|
|
INIT_73 => X"9494949494949494949494949494949494949494949493939393939393939393",
|
4555 |
|
|
INIT_74 => X"9494949494949494949494949494949494949494949494949494949494949494",
|
4556 |
|
|
INIT_75 => X"9595959595959594949494949494949494949494949494949494949494949494",
|
4557 |
|
|
INIT_76 => X"9595959595959595959595959595959595959595959595959595959595959595",
|
4558 |
|
|
INIT_77 => X"9595959595959595959595959595959595959595959595959595959595959595",
|
4559 |
|
|
INIT_78 => X"9696969696969696969696969696969696969696969696969595959595959595",
|
4560 |
|
|
INIT_79 => X"9696969696969696969696969696969696969696969696969696969696969696",
|
4561 |
|
|
INIT_7A => X"9797979797979797979696969696969696969696969696969696969696969696",
|
4562 |
|
|
INIT_7B => X"9797979797979797979797979797979797979797979797979797979797979797",
|
4563 |
|
|
INIT_7C => X"9797979797979797979797979797979797979797979797979797979797979797",
|
4564 |
|
|
INIT_7D => X"9898989898989898989898989898989898989898989898989898979797979797",
|
4565 |
|
|
INITP_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4566 |
|
|
INIT_FILE => "NONE",
|
4567 |
|
|
RAM_EXTENSION_A => "NONE",
|
4568 |
|
|
RAM_EXTENSION_B => "NONE",
|
4569 |
|
|
READ_WIDTH_A => 9,
|
4570 |
|
|
READ_WIDTH_B => 9,
|
4571 |
|
|
SIM_COLLISION_CHECK => "ALL",
|
4572 |
|
|
SIM_MODE => "SAFE",
|
4573 |
|
|
INIT_A => X"000000000",
|
4574 |
|
|
INIT_B => X"000000000",
|
4575 |
|
|
WRITE_MODE_A => "WRITE_FIRST",
|
4576 |
|
|
WRITE_MODE_B => "WRITE_FIRST",
|
4577 |
|
|
WRITE_WIDTH_A => 9,
|
4578 |
|
|
WRITE_WIDTH_B => 9,
|
4579 |
|
|
INITP_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
|
4580 |
|
|
)
|
4581 |
|
|
port map (
|
4582 |
|
|
ENAU => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_0_cmp_eq0000,
|
4583 |
|
|
ENAL => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_0_cmp_eq0000,
|
4584 |
|
|
ENBU => BU2_doutb(0),
|
4585 |
|
|
ENBL => BU2_doutb(0),
|
4586 |
|
|
SSRAU => BU2_doutb(0),
|
4587 |
|
|
SSRAL => BU2_doutb(0),
|
4588 |
|
|
SSRBU => BU2_doutb(0),
|
4589 |
|
|
SSRBL => BU2_doutb(0),
|
4590 |
|
|
CLKAU => clka,
|
4591 |
|
|
CLKAL => clka,
|
4592 |
|
|
CLKBU => BU2_doutb(0),
|
4593 |
|
|
CLKBL => BU2_doutb(0),
|
4594 |
|
|
REGCLKAU => clka,
|
4595 |
|
|
REGCLKAL => clka,
|
4596 |
|
|
REGCLKBU => BU2_doutb(0),
|
4597 |
|
|
REGCLKBL => BU2_doutb(0),
|
4598 |
|
|
REGCEAU => BU2_doutb(0),
|
4599 |
|
|
REGCEAL => BU2_doutb(0),
|
4600 |
|
|
REGCEBU => BU2_doutb(0),
|
4601 |
|
|
REGCEBL => BU2_doutb(0),
|
4602 |
|
|
CASCADEINLATA => BU2_doutb(0),
|
4603 |
|
|
CASCADEINLATB => BU2_doutb(0),
|
4604 |
|
|
CASCADEINREGA => BU2_doutb(0),
|
4605 |
|
|
CASCADEINREGB => BU2_doutb(0),
|
4606 |
|
|
CASCADEOUTLATA => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATA_UNCONNECTED,
|
4607 |
|
|
CASCADEOUTLATB => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATB_UNCONNECTED,
|
4608 |
|
|
CASCADEOUTREGA => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGA_UNCONNECTED,
|
4609 |
|
|
CASCADEOUTREGB => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGB_UNCONNECTED,
|
4610 |
|
|
DIA(31) => BU2_doutb(0),
|
4611 |
|
|
DIA(30) => BU2_doutb(0),
|
4612 |
|
|
DIA(29) => BU2_doutb(0),
|
4613 |
|
|
DIA(28) => BU2_doutb(0),
|
4614 |
|
|
DIA(27) => BU2_doutb(0),
|
4615 |
|
|
DIA(26) => BU2_doutb(0),
|
4616 |
|
|
DIA(25) => BU2_doutb(0),
|
4617 |
|
|
DIA(24) => BU2_doutb(0),
|
4618 |
|
|
DIA(23) => BU2_doutb(0),
|
4619 |
|
|
DIA(22) => BU2_doutb(0),
|
4620 |
|
|
DIA(21) => BU2_doutb(0),
|
4621 |
|
|
DIA(20) => BU2_doutb(0),
|
4622 |
|
|
DIA(19) => BU2_doutb(0),
|
4623 |
|
|
DIA(18) => BU2_doutb(0),
|
4624 |
|
|
DIA(17) => BU2_doutb(0),
|
4625 |
|
|
DIA(16) => BU2_doutb(0),
|
4626 |
|
|
DIA(15) => BU2_doutb(0),
|
4627 |
|
|
DIA(14) => BU2_doutb(0),
|
4628 |
|
|
DIA(13) => BU2_doutb(0),
|
4629 |
|
|
DIA(12) => BU2_doutb(0),
|
4630 |
|
|
DIA(11) => BU2_doutb(0),
|
4631 |
|
|
DIA(10) => BU2_doutb(0),
|
4632 |
|
|
DIA(9) => BU2_doutb(0),
|
4633 |
|
|
DIA(8) => BU2_doutb(0),
|
4634 |
|
|
DIA(7) => BU2_doutb(0),
|
4635 |
|
|
DIA(6) => BU2_doutb(0),
|
4636 |
|
|
DIA(5) => BU2_doutb(0),
|
4637 |
|
|
DIA(4) => BU2_doutb(0),
|
4638 |
|
|
DIA(3) => BU2_doutb(0),
|
4639 |
|
|
DIA(2) => BU2_doutb(0),
|
4640 |
|
|
DIA(1) => BU2_doutb(0),
|
4641 |
|
|
DIA(0) => BU2_doutb(0),
|
4642 |
|
|
DIPA(3) => BU2_doutb(0),
|
4643 |
|
|
DIPA(2) => BU2_doutb(0),
|
4644 |
|
|
DIPA(1) => BU2_doutb(0),
|
4645 |
|
|
DIPA(0) => BU2_doutb(0),
|
4646 |
|
|
DIB(31) => BU2_doutb(0),
|
4647 |
|
|
DIB(30) => BU2_doutb(0),
|
4648 |
|
|
DIB(29) => BU2_doutb(0),
|
4649 |
|
|
DIB(28) => BU2_doutb(0),
|
4650 |
|
|
DIB(27) => BU2_doutb(0),
|
4651 |
|
|
DIB(26) => BU2_doutb(0),
|
4652 |
|
|
DIB(25) => BU2_doutb(0),
|
4653 |
|
|
DIB(24) => BU2_doutb(0),
|
4654 |
|
|
DIB(23) => BU2_doutb(0),
|
4655 |
|
|
DIB(22) => BU2_doutb(0),
|
4656 |
|
|
DIB(21) => BU2_doutb(0),
|
4657 |
|
|
DIB(20) => BU2_doutb(0),
|
4658 |
|
|
DIB(19) => BU2_doutb(0),
|
4659 |
|
|
DIB(18) => BU2_doutb(0),
|
4660 |
|
|
DIB(17) => BU2_doutb(0),
|
4661 |
|
|
DIB(16) => BU2_doutb(0),
|
4662 |
|
|
DIB(15) => BU2_doutb(0),
|
4663 |
|
|
DIB(14) => BU2_doutb(0),
|
4664 |
|
|
DIB(13) => BU2_doutb(0),
|
4665 |
|
|
DIB(12) => BU2_doutb(0),
|
4666 |
|
|
DIB(11) => BU2_doutb(0),
|
4667 |
|
|
DIB(10) => BU2_doutb(0),
|
4668 |
|
|
DIB(9) => BU2_doutb(0),
|
4669 |
|
|
DIB(8) => BU2_doutb(0),
|
4670 |
|
|
DIB(7) => BU2_doutb(0),
|
4671 |
|
|
DIB(6) => BU2_doutb(0),
|
4672 |
|
|
DIB(5) => BU2_doutb(0),
|
4673 |
|
|
DIB(4) => BU2_doutb(0),
|
4674 |
|
|
DIB(3) => BU2_doutb(0),
|
4675 |
|
|
DIB(2) => BU2_doutb(0),
|
4676 |
|
|
DIB(1) => BU2_doutb(0),
|
4677 |
|
|
DIB(0) => BU2_doutb(0),
|
4678 |
|
|
DIPB(3) => BU2_doutb(0),
|
4679 |
|
|
DIPB(2) => BU2_doutb(0),
|
4680 |
|
|
DIPB(1) => BU2_doutb(0),
|
4681 |
|
|
DIPB(0) => BU2_doutb(0),
|
4682 |
|
|
ADDRAL(15) => BU2_doutb(0),
|
4683 |
|
|
ADDRAL(14) => addra_2(11),
|
4684 |
|
|
ADDRAL(13) => addra_2(10),
|
4685 |
|
|
ADDRAL(12) => addra_2(9),
|
4686 |
|
|
ADDRAL(11) => addra_2(8),
|
4687 |
|
|
ADDRAL(10) => addra_2(7),
|
4688 |
|
|
ADDRAL(9) => addra_2(6),
|
4689 |
|
|
ADDRAL(8) => addra_2(5),
|
4690 |
|
|
ADDRAL(7) => addra_2(4),
|
4691 |
|
|
ADDRAL(6) => addra_2(3),
|
4692 |
|
|
ADDRAL(5) => addra_2(2),
|
4693 |
|
|
ADDRAL(4) => addra_2(1),
|
4694 |
|
|
ADDRAL(3) => addra_2(0),
|
4695 |
|
|
ADDRAL(2) => BU2_doutb(0),
|
4696 |
|
|
ADDRAL(1) => BU2_doutb(0),
|
4697 |
|
|
ADDRAL(0) => BU2_doutb(0),
|
4698 |
|
|
ADDRAU(14) => addra_2(11),
|
4699 |
|
|
ADDRAU(13) => addra_2(10),
|
4700 |
|
|
ADDRAU(12) => addra_2(9),
|
4701 |
|
|
ADDRAU(11) => addra_2(8),
|
4702 |
|
|
ADDRAU(10) => addra_2(7),
|
4703 |
|
|
ADDRAU(9) => addra_2(6),
|
4704 |
|
|
ADDRAU(8) => addra_2(5),
|
4705 |
|
|
ADDRAU(7) => addra_2(4),
|
4706 |
|
|
ADDRAU(6) => addra_2(3),
|
4707 |
|
|
ADDRAU(5) => addra_2(2),
|
4708 |
|
|
ADDRAU(4) => addra_2(1),
|
4709 |
|
|
ADDRAU(3) => addra_2(0),
|
4710 |
|
|
ADDRAU(2) => BU2_doutb(0),
|
4711 |
|
|
ADDRAU(1) => BU2_doutb(0),
|
4712 |
|
|
ADDRAU(0) => BU2_doutb(0),
|
4713 |
|
|
ADDRBL(15) => BU2_doutb(0),
|
4714 |
|
|
ADDRBL(14) => BU2_doutb(0),
|
4715 |
|
|
ADDRBL(13) => BU2_doutb(0),
|
4716 |
|
|
ADDRBL(12) => BU2_doutb(0),
|
4717 |
|
|
ADDRBL(11) => BU2_doutb(0),
|
4718 |
|
|
ADDRBL(10) => BU2_doutb(0),
|
4719 |
|
|
ADDRBL(9) => BU2_doutb(0),
|
4720 |
|
|
ADDRBL(8) => BU2_doutb(0),
|
4721 |
|
|
ADDRBL(7) => BU2_doutb(0),
|
4722 |
|
|
ADDRBL(6) => BU2_doutb(0),
|
4723 |
|
|
ADDRBL(5) => BU2_doutb(0),
|
4724 |
|
|
ADDRBL(4) => BU2_doutb(0),
|
4725 |
|
|
ADDRBL(3) => BU2_doutb(0),
|
4726 |
|
|
ADDRBL(2) => BU2_doutb(0),
|
4727 |
|
|
ADDRBL(1) => BU2_doutb(0),
|
4728 |
|
|
ADDRBL(0) => BU2_doutb(0),
|
4729 |
|
|
ADDRBU(14) => BU2_doutb(0),
|
4730 |
|
|
ADDRBU(13) => BU2_doutb(0),
|
4731 |
|
|
ADDRBU(12) => BU2_doutb(0),
|
4732 |
|
|
ADDRBU(11) => BU2_doutb(0),
|
4733 |
|
|
ADDRBU(10) => BU2_doutb(0),
|
4734 |
|
|
ADDRBU(9) => BU2_doutb(0),
|
4735 |
|
|
ADDRBU(8) => BU2_doutb(0),
|
4736 |
|
|
ADDRBU(7) => BU2_doutb(0),
|
4737 |
|
|
ADDRBU(6) => BU2_doutb(0),
|
4738 |
|
|
ADDRBU(5) => BU2_doutb(0),
|
4739 |
|
|
ADDRBU(4) => BU2_doutb(0),
|
4740 |
|
|
ADDRBU(3) => BU2_doutb(0),
|
4741 |
|
|
ADDRBU(2) => BU2_doutb(0),
|
4742 |
|
|
ADDRBU(1) => BU2_doutb(0),
|
4743 |
|
|
ADDRBU(0) => BU2_doutb(0),
|
4744 |
|
|
WEAU(3) => BU2_doutb(0),
|
4745 |
|
|
WEAU(2) => BU2_doutb(0),
|
4746 |
|
|
WEAU(1) => BU2_doutb(0),
|
4747 |
|
|
WEAU(0) => BU2_doutb(0),
|
4748 |
|
|
WEAL(3) => BU2_doutb(0),
|
4749 |
|
|
WEAL(2) => BU2_doutb(0),
|
4750 |
|
|
WEAL(1) => BU2_doutb(0),
|
4751 |
|
|
WEAL(0) => BU2_doutb(0),
|
4752 |
|
|
WEBU(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_7_UNCONNECTED,
|
4753 |
|
|
WEBU(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_6_UNCONNECTED,
|
4754 |
|
|
WEBU(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_5_UNCONNECTED,
|
4755 |
|
|
WEBU(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_4_UNCONNECTED,
|
4756 |
|
|
WEBU(3) => BU2_doutb(0),
|
4757 |
|
|
WEBU(2) => BU2_doutb(0),
|
4758 |
|
|
WEBU(1) => BU2_doutb(0),
|
4759 |
|
|
WEBU(0) => BU2_doutb(0),
|
4760 |
|
|
WEBL(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_7_UNCONNECTED,
|
4761 |
|
|
WEBL(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_6_UNCONNECTED,
|
4762 |
|
|
WEBL(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_5_UNCONNECTED,
|
4763 |
|
|
WEBL(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_4_UNCONNECTED,
|
4764 |
|
|
WEBL(3) => BU2_doutb(0),
|
4765 |
|
|
WEBL(2) => BU2_doutb(0),
|
4766 |
|
|
WEBL(1) => BU2_doutb(0),
|
4767 |
|
|
WEBL(0) => BU2_doutb(0),
|
4768 |
|
|
DOA(31) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_31_UNCONNECTED,
|
4769 |
|
|
DOA(30) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_30_UNCONNECTED,
|
4770 |
|
|
DOA(29) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_29_UNCONNECTED,
|
4771 |
|
|
DOA(28) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_28_UNCONNECTED,
|
4772 |
|
|
DOA(27) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_27_UNCONNECTED,
|
4773 |
|
|
DOA(26) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_26_UNCONNECTED,
|
4774 |
|
|
DOA(25) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_25_UNCONNECTED,
|
4775 |
|
|
DOA(24) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_24_UNCONNECTED,
|
4776 |
|
|
DOA(23) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_23_UNCONNECTED,
|
4777 |
|
|
DOA(22) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_22_UNCONNECTED,
|
4778 |
|
|
DOA(21) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_21_UNCONNECTED,
|
4779 |
|
|
DOA(20) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_20_UNCONNECTED,
|
4780 |
|
|
DOA(19) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_19_UNCONNECTED,
|
4781 |
|
|
DOA(18) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_18_UNCONNECTED,
|
4782 |
|
|
DOA(17) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_17_UNCONNECTED,
|
4783 |
|
|
DOA(16) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_16_UNCONNECTED,
|
4784 |
|
|
DOA(15) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_15_UNCONNECTED,
|
4785 |
|
|
DOA(14) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_14_UNCONNECTED,
|
4786 |
|
|
DOA(13) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_13_UNCONNECTED,
|
4787 |
|
|
DOA(12) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_12_UNCONNECTED,
|
4788 |
|
|
DOA(11) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_11_UNCONNECTED,
|
4789 |
|
|
DOA(10) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_10_UNCONNECTED,
|
4790 |
|
|
DOA(9) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_9_UNCONNECTED,
|
4791 |
|
|
DOA(8) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_8_UNCONNECTED,
|
4792 |
|
|
DOA(7) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta7(7),
|
4793 |
|
|
DOA(6) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta7(6),
|
4794 |
|
|
DOA(5) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta7(5),
|
4795 |
|
|
DOA(4) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta7(4),
|
4796 |
|
|
DOA(3) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta7(3),
|
4797 |
|
|
DOA(2) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta7(2),
|
4798 |
|
|
DOA(1) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta7(1),
|
4799 |
|
|
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta7(0),
|
4800 |
|
|
DOPA(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_3_UNCONNECTED,
|
4801 |
|
|
DOPA(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_2_UNCONNECTED,
|
4802 |
|
|
DOPA(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_1_UNCONNECTED,
|
4803 |
|
|
DOPA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta7(8),
|
4804 |
|
|
DOB(31) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_31_UNCONNECTED,
|
4805 |
|
|
DOB(30) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_30_UNCONNECTED,
|
4806 |
|
|
DOB(29) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_29_UNCONNECTED,
|
4807 |
|
|
DOB(28) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_28_UNCONNECTED,
|
4808 |
|
|
DOB(27) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_27_UNCONNECTED,
|
4809 |
|
|
DOB(26) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_26_UNCONNECTED,
|
4810 |
|
|
DOB(25) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_25_UNCONNECTED,
|
4811 |
|
|
DOB(24) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_24_UNCONNECTED,
|
4812 |
|
|
DOB(23) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_23_UNCONNECTED,
|
4813 |
|
|
DOB(22) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_22_UNCONNECTED,
|
4814 |
|
|
DOB(21) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_21_UNCONNECTED,
|
4815 |
|
|
DOB(20) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_20_UNCONNECTED,
|
4816 |
|
|
DOB(19) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_19_UNCONNECTED,
|
4817 |
|
|
DOB(18) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_18_UNCONNECTED,
|
4818 |
|
|
DOB(17) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_17_UNCONNECTED,
|
4819 |
|
|
DOB(16) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_16_UNCONNECTED,
|
4820 |
|
|
DOB(15) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_15_UNCONNECTED,
|
4821 |
|
|
DOB(14) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_14_UNCONNECTED,
|
4822 |
|
|
DOB(13) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_13_UNCONNECTED,
|
4823 |
|
|
DOB(12) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_12_UNCONNECTED,
|
4824 |
|
|
DOB(11) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_11_UNCONNECTED,
|
4825 |
|
|
DOB(10) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_10_UNCONNECTED,
|
4826 |
|
|
DOB(9) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_9_UNCONNECTED,
|
4827 |
|
|
DOB(8) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_8_UNCONNECTED,
|
4828 |
|
|
DOB(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_7_UNCONNECTED,
|
4829 |
|
|
DOB(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_6_UNCONNECTED,
|
4830 |
|
|
DOB(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_5_UNCONNECTED,
|
4831 |
|
|
DOB(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_4_UNCONNECTED,
|
4832 |
|
|
DOB(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_3_UNCONNECTED,
|
4833 |
|
|
DOB(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_2_UNCONNECTED,
|
4834 |
|
|
DOB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_1_UNCONNECTED,
|
4835 |
|
|
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_0_UNCONNECTED,
|
4836 |
|
|
DOPB(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_3_UNCONNECTED,
|
4837 |
|
|
DOPB(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_2_UNCONNECTED,
|
4838 |
|
|
DOPB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_1_UNCONNECTED,
|
4839 |
|
|
DOPB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_0_UNCONNECTED
|
4840 |
|
|
);
|
4841 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP : RAMB36_EXP
|
4842 |
|
|
generic map(
|
4843 |
|
|
DOA_REG => 0,
|
4844 |
|
|
DOB_REG => 0,
|
4845 |
|
|
INIT_7E => X"B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3",
|
4846 |
|
|
INIT_7F => X"B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3",
|
4847 |
|
|
INITP_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4848 |
|
|
INITP_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4849 |
|
|
INITP_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4850 |
|
|
INITP_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4851 |
|
|
INITP_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4852 |
|
|
INITP_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4853 |
|
|
INITP_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4854 |
|
|
INITP_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4855 |
|
|
INITP_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4856 |
|
|
INITP_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4857 |
|
|
INITP_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4858 |
|
|
INITP_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4859 |
|
|
INITP_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4860 |
|
|
INITP_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4861 |
|
|
SRVAL_A => X"000000000",
|
4862 |
|
|
SRVAL_B => X"000000000",
|
4863 |
|
|
INIT_00 => X"9999999999999999999999999999999999999999999999999999999999999999",
|
4864 |
|
|
INIT_01 => X"9999999999999999999999999999999999999999999999999999999999999999",
|
4865 |
|
|
INIT_02 => X"9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A999999999999",
|
4866 |
|
|
INIT_03 => X"9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A",
|
4867 |
|
|
INIT_04 => X"9B9B9B9B9B9B9B9B9B9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A",
|
4868 |
|
|
INIT_05 => X"9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B",
|
4869 |
|
|
INIT_06 => X"9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B",
|
4870 |
|
|
INIT_07 => X"9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9B9B9B9B9B9B9B",
|
4871 |
|
|
INIT_08 => X"9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C",
|
4872 |
|
|
INIT_09 => X"9D9D9D9D9D9D9D9D9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C",
|
4873 |
|
|
INIT_0A => X"9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D",
|
4874 |
|
|
INIT_0B => X"9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D9D",
|
4875 |
|
|
INIT_0C => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9D9D9D9D9D9D9D9D9D9D",
|
4876 |
|
|
INIT_0D => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
|
4877 |
|
|
INIT_0E => X"9F9F9F9F9F9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
|
4878 |
|
|
INIT_0F => X"9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F",
|
4879 |
|
|
INIT_10 => X"9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F9F",
|
4880 |
|
|
INIT_11 => X"A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A09F9F9F9F9F9F9F9F9F9F9F9F9F",
|
4881 |
|
|
INIT_12 => X"A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0",
|
4882 |
|
|
INIT_13 => X"A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0",
|
4883 |
|
|
INIT_14 => X"A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0",
|
4884 |
|
|
INIT_15 => X"A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0",
|
4885 |
|
|
INIT_16 => X"A1A1A1A1A1A1A1A1A1A1A1A1A1A1A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0",
|
4886 |
|
|
INIT_17 => X"A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1",
|
4887 |
|
|
INIT_18 => X"A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1",
|
4888 |
|
|
INIT_19 => X"A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1",
|
4889 |
|
|
INIT_1A => X"A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1",
|
4890 |
|
|
INIT_1B => X"A2A2A2A2A2A2A2A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1",
|
4891 |
|
|
INIT_1C => X"A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2",
|
4892 |
|
|
INIT_1D => X"A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2",
|
4893 |
|
|
INIT_1E => X"A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2",
|
4894 |
|
|
INIT_1F => X"A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2",
|
4895 |
|
|
INIT_20 => X"A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2",
|
4896 |
|
|
INIT_21 => X"A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3",
|
4897 |
|
|
INIT_22 => X"A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3",
|
4898 |
|
|
INIT_23 => X"A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3",
|
4899 |
|
|
INIT_24 => X"A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3",
|
4900 |
|
|
INIT_25 => X"A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3",
|
4901 |
|
|
INIT_26 => X"A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A3A3A3A3A3A3A3A3A3",
|
4902 |
|
|
INIT_27 => X"A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4",
|
4903 |
|
|
INIT_28 => X"A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4",
|
4904 |
|
|
INIT_29 => X"A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4",
|
4905 |
|
|
INIT_2A => X"A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4",
|
4906 |
|
|
INIT_2B => X"A5A5A5A5A5A5A5A5A5A5A5A5A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4A4",
|
4907 |
|
|
INIT_2C => X"A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5",
|
4908 |
|
|
INIT_2D => X"A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5",
|
4909 |
|
|
INIT_2E => X"A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5",
|
4910 |
|
|
INIT_2F => X"A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5",
|
4911 |
|
|
INIT_30 => X"A6A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5",
|
4912 |
|
|
INIT_31 => X"A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6",
|
4913 |
|
|
INIT_32 => X"A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6",
|
4914 |
|
|
INIT_33 => X"A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6",
|
4915 |
|
|
INIT_34 => X"A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6",
|
4916 |
|
|
INIT_35 => X"A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6A6",
|
4917 |
|
|
INIT_36 => X"A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A6A6A6A6A6A6A6A6A6A6A6A6",
|
4918 |
|
|
INIT_37 => X"A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7",
|
4919 |
|
|
INIT_38 => X"A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7",
|
4920 |
|
|
INIT_39 => X"A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7",
|
4921 |
|
|
INIT_3A => X"A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7",
|
4922 |
|
|
INIT_3B => X"A8A8A8A8A8A8A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7",
|
4923 |
|
|
INIT_3C => X"A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8",
|
4924 |
|
|
INIT_3D => X"A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8",
|
4925 |
|
|
INIT_3E => X"A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8",
|
4926 |
|
|
INIT_3F => X"A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8",
|
4927 |
|
|
INIT_40 => X"A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8A8",
|
4928 |
|
|
INIT_41 => X"A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A8A8A8A8A8A8A8A8A8A8",
|
4929 |
|
|
INIT_42 => X"A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9",
|
4930 |
|
|
INIT_43 => X"A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9",
|
4931 |
|
|
INIT_44 => X"A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9",
|
4932 |
|
|
INIT_45 => X"A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9",
|
4933 |
|
|
INIT_46 => X"AAAAAAAAAAA9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9A9",
|
4934 |
|
|
INIT_47 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
|
4935 |
|
|
INIT_48 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
|
4936 |
|
|
INIT_49 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
|
4937 |
|
|
INIT_4A => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
|
4938 |
|
|
INIT_4B => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
|
4939 |
|
|
INIT_4C => X"ABABABABABABABABABABABABABABABABABABABAAAAAAAAAAAAAAAAAAAAAAAAAA",
|
4940 |
|
|
INIT_4D => X"ABABABABABABABABABABABABABABABABABABABABABABABABABABABABABABABAB",
|
4941 |
|
|
INIT_4E => X"ABABABABABABABABABABABABABABABABABABABABABABABABABABABABABABABAB",
|
4942 |
|
|
INIT_4F => X"ABABABABABABABABABABABABABABABABABABABABABABABABABABABABABABABAB",
|
4943 |
|
|
INIT_50 => X"ABABABABABABABABABABABABABABABABABABABABABABABABABABABABABABABAB",
|
4944 |
|
|
INIT_51 => X"ABABABABABABABABABABABABABABABABABABABABABABABABABABABABABABABAB",
|
4945 |
|
|
INIT_52 => X"ACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACAB",
|
4946 |
|
|
INIT_53 => X"ACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACAC",
|
4947 |
|
|
INIT_54 => X"ACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACAC",
|
4948 |
|
|
INIT_55 => X"ACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACAC",
|
4949 |
|
|
INIT_56 => X"ACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACAC",
|
4950 |
|
|
INIT_57 => X"ADADADADADADADADADADACACACACACACACACACACACACACACACACACACACACACAC",
|
4951 |
|
|
INIT_58 => X"ADADADADADADADADADADADADADADADADADADADADADADADADADADADADADADADAD",
|
4952 |
|
|
INIT_59 => X"ADADADADADADADADADADADADADADADADADADADADADADADADADADADADADADADAD",
|
4953 |
|
|
INIT_5A => X"ADADADADADADADADADADADADADADADADADADADADADADADADADADADADADADADAD",
|
4954 |
|
|
INIT_5B => X"ADADADADADADADADADADADADADADADADADADADADADADADADADADADADADADADAD",
|
4955 |
|
|
INIT_5C => X"ADADADADADADADADADADADADADADADADADADADADADADADADADADADADADADADAD",
|
4956 |
|
|
INIT_5D => X"AEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEADADADADADADADADADADADADAD",
|
4957 |
|
|
INIT_5E => X"AEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAE",
|
4958 |
|
|
INIT_5F => X"AEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAE",
|
4959 |
|
|
INIT_60 => X"AEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAE",
|
4960 |
|
|
INIT_61 => X"AEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAE",
|
4961 |
|
|
INIT_62 => X"AEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAE",
|
4962 |
|
|
INIT_63 => X"AFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAEAEAEAEAE",
|
4963 |
|
|
INIT_64 => X"AFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAF",
|
4964 |
|
|
INIT_65 => X"AFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAF",
|
4965 |
|
|
INIT_66 => X"AFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAF",
|
4966 |
|
|
INIT_67 => X"AFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAF",
|
4967 |
|
|
INIT_68 => X"B0AFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAFAF",
|
4968 |
|
|
INIT_69 => X"B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0",
|
4969 |
|
|
INIT_6A => X"B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0",
|
4970 |
|
|
INIT_6B => X"B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0",
|
4971 |
|
|
INIT_6C => X"B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0",
|
4972 |
|
|
INIT_6D => X"B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0",
|
4973 |
|
|
INIT_6E => X"B1B1B1B1B1B1B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0",
|
4974 |
|
|
INIT_6F => X"B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1",
|
4975 |
|
|
INIT_70 => X"B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1",
|
4976 |
|
|
INIT_71 => X"B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1",
|
4977 |
|
|
INIT_72 => X"B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1",
|
4978 |
|
|
INIT_73 => X"B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1",
|
4979 |
|
|
INIT_74 => X"B2B2B2B2B2B2B2B2B2B2B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1",
|
4980 |
|
|
INIT_75 => X"B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2",
|
4981 |
|
|
INIT_76 => X"B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2",
|
4982 |
|
|
INIT_77 => X"B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2",
|
4983 |
|
|
INIT_78 => X"B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2",
|
4984 |
|
|
INIT_79 => X"B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2",
|
4985 |
|
|
INIT_7A => X"B3B3B3B3B3B3B3B3B3B3B3B3B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2B2",
|
4986 |
|
|
INIT_7B => X"B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3",
|
4987 |
|
|
INIT_7C => X"B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3",
|
4988 |
|
|
INIT_7D => X"B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3",
|
4989 |
|
|
INITP_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
4990 |
|
|
INIT_FILE => "NONE",
|
4991 |
|
|
RAM_EXTENSION_A => "NONE",
|
4992 |
|
|
RAM_EXTENSION_B => "NONE",
|
4993 |
|
|
READ_WIDTH_A => 9,
|
4994 |
|
|
READ_WIDTH_B => 9,
|
4995 |
|
|
SIM_COLLISION_CHECK => "ALL",
|
4996 |
|
|
SIM_MODE => "SAFE",
|
4997 |
|
|
INIT_A => X"000000000",
|
4998 |
|
|
INIT_B => X"000000000",
|
4999 |
|
|
WRITE_MODE_A => "WRITE_FIRST",
|
5000 |
|
|
WRITE_MODE_B => "WRITE_FIRST",
|
5001 |
|
|
WRITE_WIDTH_A => 9,
|
5002 |
|
|
WRITE_WIDTH_B => 9,
|
5003 |
|
|
INITP_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
|
5004 |
|
|
)
|
5005 |
|
|
port map (
|
5006 |
|
|
ENAU => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_1_cmp_eq0000,
|
5007 |
|
|
ENAL => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_1_cmp_eq0000,
|
5008 |
|
|
ENBU => BU2_doutb(0),
|
5009 |
|
|
ENBL => BU2_doutb(0),
|
5010 |
|
|
SSRAU => BU2_doutb(0),
|
5011 |
|
|
SSRAL => BU2_doutb(0),
|
5012 |
|
|
SSRBU => BU2_doutb(0),
|
5013 |
|
|
SSRBL => BU2_doutb(0),
|
5014 |
|
|
CLKAU => clka,
|
5015 |
|
|
CLKAL => clka,
|
5016 |
|
|
CLKBU => BU2_doutb(0),
|
5017 |
|
|
CLKBL => BU2_doutb(0),
|
5018 |
|
|
REGCLKAU => clka,
|
5019 |
|
|
REGCLKAL => clka,
|
5020 |
|
|
REGCLKBU => BU2_doutb(0),
|
5021 |
|
|
REGCLKBL => BU2_doutb(0),
|
5022 |
|
|
REGCEAU => BU2_doutb(0),
|
5023 |
|
|
REGCEAL => BU2_doutb(0),
|
5024 |
|
|
REGCEBU => BU2_doutb(0),
|
5025 |
|
|
REGCEBL => BU2_doutb(0),
|
5026 |
|
|
CASCADEINLATA => BU2_doutb(0),
|
5027 |
|
|
CASCADEINLATB => BU2_doutb(0),
|
5028 |
|
|
CASCADEINREGA => BU2_doutb(0),
|
5029 |
|
|
CASCADEINREGB => BU2_doutb(0),
|
5030 |
|
|
CASCADEOUTLATA => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATA_UNCONNECTED,
|
5031 |
|
|
CASCADEOUTLATB => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATB_UNCONNECTED,
|
5032 |
|
|
CASCADEOUTREGA => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGA_UNCONNECTED,
|
5033 |
|
|
CASCADEOUTREGB => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGB_UNCONNECTED,
|
5034 |
|
|
DIA(31) => BU2_doutb(0),
|
5035 |
|
|
DIA(30) => BU2_doutb(0),
|
5036 |
|
|
DIA(29) => BU2_doutb(0),
|
5037 |
|
|
DIA(28) => BU2_doutb(0),
|
5038 |
|
|
DIA(27) => BU2_doutb(0),
|
5039 |
|
|
DIA(26) => BU2_doutb(0),
|
5040 |
|
|
DIA(25) => BU2_doutb(0),
|
5041 |
|
|
DIA(24) => BU2_doutb(0),
|
5042 |
|
|
DIA(23) => BU2_doutb(0),
|
5043 |
|
|
DIA(22) => BU2_doutb(0),
|
5044 |
|
|
DIA(21) => BU2_doutb(0),
|
5045 |
|
|
DIA(20) => BU2_doutb(0),
|
5046 |
|
|
DIA(19) => BU2_doutb(0),
|
5047 |
|
|
DIA(18) => BU2_doutb(0),
|
5048 |
|
|
DIA(17) => BU2_doutb(0),
|
5049 |
|
|
DIA(16) => BU2_doutb(0),
|
5050 |
|
|
DIA(15) => BU2_doutb(0),
|
5051 |
|
|
DIA(14) => BU2_doutb(0),
|
5052 |
|
|
DIA(13) => BU2_doutb(0),
|
5053 |
|
|
DIA(12) => BU2_doutb(0),
|
5054 |
|
|
DIA(11) => BU2_doutb(0),
|
5055 |
|
|
DIA(10) => BU2_doutb(0),
|
5056 |
|
|
DIA(9) => BU2_doutb(0),
|
5057 |
|
|
DIA(8) => BU2_doutb(0),
|
5058 |
|
|
DIA(7) => BU2_doutb(0),
|
5059 |
|
|
DIA(6) => BU2_doutb(0),
|
5060 |
|
|
DIA(5) => BU2_doutb(0),
|
5061 |
|
|
DIA(4) => BU2_doutb(0),
|
5062 |
|
|
DIA(3) => BU2_doutb(0),
|
5063 |
|
|
DIA(2) => BU2_doutb(0),
|
5064 |
|
|
DIA(1) => BU2_doutb(0),
|
5065 |
|
|
DIA(0) => BU2_doutb(0),
|
5066 |
|
|
DIPA(3) => BU2_doutb(0),
|
5067 |
|
|
DIPA(2) => BU2_doutb(0),
|
5068 |
|
|
DIPA(1) => BU2_doutb(0),
|
5069 |
|
|
DIPA(0) => BU2_doutb(0),
|
5070 |
|
|
DIB(31) => BU2_doutb(0),
|
5071 |
|
|
DIB(30) => BU2_doutb(0),
|
5072 |
|
|
DIB(29) => BU2_doutb(0),
|
5073 |
|
|
DIB(28) => BU2_doutb(0),
|
5074 |
|
|
DIB(27) => BU2_doutb(0),
|
5075 |
|
|
DIB(26) => BU2_doutb(0),
|
5076 |
|
|
DIB(25) => BU2_doutb(0),
|
5077 |
|
|
DIB(24) => BU2_doutb(0),
|
5078 |
|
|
DIB(23) => BU2_doutb(0),
|
5079 |
|
|
DIB(22) => BU2_doutb(0),
|
5080 |
|
|
DIB(21) => BU2_doutb(0),
|
5081 |
|
|
DIB(20) => BU2_doutb(0),
|
5082 |
|
|
DIB(19) => BU2_doutb(0),
|
5083 |
|
|
DIB(18) => BU2_doutb(0),
|
5084 |
|
|
DIB(17) => BU2_doutb(0),
|
5085 |
|
|
DIB(16) => BU2_doutb(0),
|
5086 |
|
|
DIB(15) => BU2_doutb(0),
|
5087 |
|
|
DIB(14) => BU2_doutb(0),
|
5088 |
|
|
DIB(13) => BU2_doutb(0),
|
5089 |
|
|
DIB(12) => BU2_doutb(0),
|
5090 |
|
|
DIB(11) => BU2_doutb(0),
|
5091 |
|
|
DIB(10) => BU2_doutb(0),
|
5092 |
|
|
DIB(9) => BU2_doutb(0),
|
5093 |
|
|
DIB(8) => BU2_doutb(0),
|
5094 |
|
|
DIB(7) => BU2_doutb(0),
|
5095 |
|
|
DIB(6) => BU2_doutb(0),
|
5096 |
|
|
DIB(5) => BU2_doutb(0),
|
5097 |
|
|
DIB(4) => BU2_doutb(0),
|
5098 |
|
|
DIB(3) => BU2_doutb(0),
|
5099 |
|
|
DIB(2) => BU2_doutb(0),
|
5100 |
|
|
DIB(1) => BU2_doutb(0),
|
5101 |
|
|
DIB(0) => BU2_doutb(0),
|
5102 |
|
|
DIPB(3) => BU2_doutb(0),
|
5103 |
|
|
DIPB(2) => BU2_doutb(0),
|
5104 |
|
|
DIPB(1) => BU2_doutb(0),
|
5105 |
|
|
DIPB(0) => BU2_doutb(0),
|
5106 |
|
|
ADDRAL(15) => BU2_doutb(0),
|
5107 |
|
|
ADDRAL(14) => addra_2(11),
|
5108 |
|
|
ADDRAL(13) => addra_2(10),
|
5109 |
|
|
ADDRAL(12) => addra_2(9),
|
5110 |
|
|
ADDRAL(11) => addra_2(8),
|
5111 |
|
|
ADDRAL(10) => addra_2(7),
|
5112 |
|
|
ADDRAL(9) => addra_2(6),
|
5113 |
|
|
ADDRAL(8) => addra_2(5),
|
5114 |
|
|
ADDRAL(7) => addra_2(4),
|
5115 |
|
|
ADDRAL(6) => addra_2(3),
|
5116 |
|
|
ADDRAL(5) => addra_2(2),
|
5117 |
|
|
ADDRAL(4) => addra_2(1),
|
5118 |
|
|
ADDRAL(3) => addra_2(0),
|
5119 |
|
|
ADDRAL(2) => BU2_doutb(0),
|
5120 |
|
|
ADDRAL(1) => BU2_doutb(0),
|
5121 |
|
|
ADDRAL(0) => BU2_doutb(0),
|
5122 |
|
|
ADDRAU(14) => addra_2(11),
|
5123 |
|
|
ADDRAU(13) => addra_2(10),
|
5124 |
|
|
ADDRAU(12) => addra_2(9),
|
5125 |
|
|
ADDRAU(11) => addra_2(8),
|
5126 |
|
|
ADDRAU(10) => addra_2(7),
|
5127 |
|
|
ADDRAU(9) => addra_2(6),
|
5128 |
|
|
ADDRAU(8) => addra_2(5),
|
5129 |
|
|
ADDRAU(7) => addra_2(4),
|
5130 |
|
|
ADDRAU(6) => addra_2(3),
|
5131 |
|
|
ADDRAU(5) => addra_2(2),
|
5132 |
|
|
ADDRAU(4) => addra_2(1),
|
5133 |
|
|
ADDRAU(3) => addra_2(0),
|
5134 |
|
|
ADDRAU(2) => BU2_doutb(0),
|
5135 |
|
|
ADDRAU(1) => BU2_doutb(0),
|
5136 |
|
|
ADDRAU(0) => BU2_doutb(0),
|
5137 |
|
|
ADDRBL(15) => BU2_doutb(0),
|
5138 |
|
|
ADDRBL(14) => BU2_doutb(0),
|
5139 |
|
|
ADDRBL(13) => BU2_doutb(0),
|
5140 |
|
|
ADDRBL(12) => BU2_doutb(0),
|
5141 |
|
|
ADDRBL(11) => BU2_doutb(0),
|
5142 |
|
|
ADDRBL(10) => BU2_doutb(0),
|
5143 |
|
|
ADDRBL(9) => BU2_doutb(0),
|
5144 |
|
|
ADDRBL(8) => BU2_doutb(0),
|
5145 |
|
|
ADDRBL(7) => BU2_doutb(0),
|
5146 |
|
|
ADDRBL(6) => BU2_doutb(0),
|
5147 |
|
|
ADDRBL(5) => BU2_doutb(0),
|
5148 |
|
|
ADDRBL(4) => BU2_doutb(0),
|
5149 |
|
|
ADDRBL(3) => BU2_doutb(0),
|
5150 |
|
|
ADDRBL(2) => BU2_doutb(0),
|
5151 |
|
|
ADDRBL(1) => BU2_doutb(0),
|
5152 |
|
|
ADDRBL(0) => BU2_doutb(0),
|
5153 |
|
|
ADDRBU(14) => BU2_doutb(0),
|
5154 |
|
|
ADDRBU(13) => BU2_doutb(0),
|
5155 |
|
|
ADDRBU(12) => BU2_doutb(0),
|
5156 |
|
|
ADDRBU(11) => BU2_doutb(0),
|
5157 |
|
|
ADDRBU(10) => BU2_doutb(0),
|
5158 |
|
|
ADDRBU(9) => BU2_doutb(0),
|
5159 |
|
|
ADDRBU(8) => BU2_doutb(0),
|
5160 |
|
|
ADDRBU(7) => BU2_doutb(0),
|
5161 |
|
|
ADDRBU(6) => BU2_doutb(0),
|
5162 |
|
|
ADDRBU(5) => BU2_doutb(0),
|
5163 |
|
|
ADDRBU(4) => BU2_doutb(0),
|
5164 |
|
|
ADDRBU(3) => BU2_doutb(0),
|
5165 |
|
|
ADDRBU(2) => BU2_doutb(0),
|
5166 |
|
|
ADDRBU(1) => BU2_doutb(0),
|
5167 |
|
|
ADDRBU(0) => BU2_doutb(0),
|
5168 |
|
|
WEAU(3) => BU2_doutb(0),
|
5169 |
|
|
WEAU(2) => BU2_doutb(0),
|
5170 |
|
|
WEAU(1) => BU2_doutb(0),
|
5171 |
|
|
WEAU(0) => BU2_doutb(0),
|
5172 |
|
|
WEAL(3) => BU2_doutb(0),
|
5173 |
|
|
WEAL(2) => BU2_doutb(0),
|
5174 |
|
|
WEAL(1) => BU2_doutb(0),
|
5175 |
|
|
WEAL(0) => BU2_doutb(0),
|
5176 |
|
|
WEBU(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_7_UNCONNECTED,
|
5177 |
|
|
WEBU(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_6_UNCONNECTED,
|
5178 |
|
|
WEBU(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_5_UNCONNECTED,
|
5179 |
|
|
WEBU(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_4_UNCONNECTED,
|
5180 |
|
|
WEBU(3) => BU2_doutb(0),
|
5181 |
|
|
WEBU(2) => BU2_doutb(0),
|
5182 |
|
|
WEBU(1) => BU2_doutb(0),
|
5183 |
|
|
WEBU(0) => BU2_doutb(0),
|
5184 |
|
|
WEBL(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_7_UNCONNECTED,
|
5185 |
|
|
WEBL(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_6_UNCONNECTED,
|
5186 |
|
|
WEBL(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_5_UNCONNECTED,
|
5187 |
|
|
WEBL(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_4_UNCONNECTED,
|
5188 |
|
|
WEBL(3) => BU2_doutb(0),
|
5189 |
|
|
WEBL(2) => BU2_doutb(0),
|
5190 |
|
|
WEBL(1) => BU2_doutb(0),
|
5191 |
|
|
WEBL(0) => BU2_doutb(0),
|
5192 |
|
|
DOA(31) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_31_UNCONNECTED,
|
5193 |
|
|
DOA(30) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_30_UNCONNECTED,
|
5194 |
|
|
DOA(29) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_29_UNCONNECTED,
|
5195 |
|
|
DOA(28) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_28_UNCONNECTED,
|
5196 |
|
|
DOA(27) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_27_UNCONNECTED,
|
5197 |
|
|
DOA(26) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_26_UNCONNECTED,
|
5198 |
|
|
DOA(25) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_25_UNCONNECTED,
|
5199 |
|
|
DOA(24) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_24_UNCONNECTED,
|
5200 |
|
|
DOA(23) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_23_UNCONNECTED,
|
5201 |
|
|
DOA(22) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_22_UNCONNECTED,
|
5202 |
|
|
DOA(21) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_21_UNCONNECTED,
|
5203 |
|
|
DOA(20) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_20_UNCONNECTED,
|
5204 |
|
|
DOA(19) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_19_UNCONNECTED,
|
5205 |
|
|
DOA(18) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_18_UNCONNECTED,
|
5206 |
|
|
DOA(17) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_17_UNCONNECTED,
|
5207 |
|
|
DOA(16) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_16_UNCONNECTED,
|
5208 |
|
|
DOA(15) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_15_UNCONNECTED,
|
5209 |
|
|
DOA(14) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_14_UNCONNECTED,
|
5210 |
|
|
DOA(13) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_13_UNCONNECTED,
|
5211 |
|
|
DOA(12) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_12_UNCONNECTED,
|
5212 |
|
|
DOA(11) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_11_UNCONNECTED,
|
5213 |
|
|
DOA(10) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_10_UNCONNECTED,
|
5214 |
|
|
DOA(9) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_9_UNCONNECTED,
|
5215 |
|
|
DOA(8) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_8_UNCONNECTED,
|
5216 |
|
|
DOA(7) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta8(7),
|
5217 |
|
|
DOA(6) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta8(6),
|
5218 |
|
|
DOA(5) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta8(5),
|
5219 |
|
|
DOA(4) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta8(4),
|
5220 |
|
|
DOA(3) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta8(3),
|
5221 |
|
|
DOA(2) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta8(2),
|
5222 |
|
|
DOA(1) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta8(1),
|
5223 |
|
|
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta8(0),
|
5224 |
|
|
DOPA(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_3_UNCONNECTED,
|
5225 |
|
|
DOPA(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_2_UNCONNECTED,
|
5226 |
|
|
DOPA(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_1_UNCONNECTED,
|
5227 |
|
|
DOPA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta8(8),
|
5228 |
|
|
DOB(31) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_31_UNCONNECTED,
|
5229 |
|
|
DOB(30) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_30_UNCONNECTED,
|
5230 |
|
|
DOB(29) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_29_UNCONNECTED,
|
5231 |
|
|
DOB(28) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_28_UNCONNECTED,
|
5232 |
|
|
DOB(27) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_27_UNCONNECTED,
|
5233 |
|
|
DOB(26) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_26_UNCONNECTED,
|
5234 |
|
|
DOB(25) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_25_UNCONNECTED,
|
5235 |
|
|
DOB(24) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_24_UNCONNECTED,
|
5236 |
|
|
DOB(23) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_23_UNCONNECTED,
|
5237 |
|
|
DOB(22) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_22_UNCONNECTED,
|
5238 |
|
|
DOB(21) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_21_UNCONNECTED,
|
5239 |
|
|
DOB(20) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_20_UNCONNECTED,
|
5240 |
|
|
DOB(19) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_19_UNCONNECTED,
|
5241 |
|
|
DOB(18) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_18_UNCONNECTED,
|
5242 |
|
|
DOB(17) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_17_UNCONNECTED,
|
5243 |
|
|
DOB(16) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_16_UNCONNECTED,
|
5244 |
|
|
DOB(15) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_15_UNCONNECTED,
|
5245 |
|
|
DOB(14) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_14_UNCONNECTED,
|
5246 |
|
|
DOB(13) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_13_UNCONNECTED,
|
5247 |
|
|
DOB(12) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_12_UNCONNECTED,
|
5248 |
|
|
DOB(11) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_11_UNCONNECTED,
|
5249 |
|
|
DOB(10) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_10_UNCONNECTED,
|
5250 |
|
|
DOB(9) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_9_UNCONNECTED,
|
5251 |
|
|
DOB(8) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_8_UNCONNECTED,
|
5252 |
|
|
DOB(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_7_UNCONNECTED,
|
5253 |
|
|
DOB(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_6_UNCONNECTED,
|
5254 |
|
|
DOB(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_5_UNCONNECTED,
|
5255 |
|
|
DOB(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_4_UNCONNECTED,
|
5256 |
|
|
DOB(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_3_UNCONNECTED,
|
5257 |
|
|
DOB(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_2_UNCONNECTED,
|
5258 |
|
|
DOB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_1_UNCONNECTED,
|
5259 |
|
|
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_0_UNCONNECTED,
|
5260 |
|
|
DOPB(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_3_UNCONNECTED,
|
5261 |
|
|
DOPB(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_2_UNCONNECTED,
|
5262 |
|
|
DOPB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_1_UNCONNECTED,
|
5263 |
|
|
DOPB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_0_UNCONNECTED
|
5264 |
|
|
);
|
5265 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP : RAMB36_EXP
|
5266 |
|
|
generic map(
|
5267 |
|
|
DOA_REG => 0,
|
5268 |
|
|
DOB_REG => 0,
|
5269 |
|
|
INIT_7E => X"C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3",
|
5270 |
|
|
INIT_7F => X"C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3",
|
5271 |
|
|
INITP_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
5272 |
|
|
INITP_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
5273 |
|
|
INITP_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
5274 |
|
|
INITP_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
5275 |
|
|
INITP_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
5276 |
|
|
INITP_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
5277 |
|
|
INITP_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
5278 |
|
|
INITP_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
5279 |
|
|
INITP_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
5280 |
|
|
INITP_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
5281 |
|
|
INITP_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
5282 |
|
|
INITP_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
5283 |
|
|
INITP_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
5284 |
|
|
INITP_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
5285 |
|
|
SRVAL_A => X"000000000",
|
5286 |
|
|
SRVAL_B => X"000000000",
|
5287 |
|
|
INIT_00 => X"B4B4B4B4B4B4B4B4B4B4B4B4B4B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3B3",
|
5288 |
|
|
INIT_01 => X"B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4",
|
5289 |
|
|
INIT_02 => X"B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4",
|
5290 |
|
|
INIT_03 => X"B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4",
|
5291 |
|
|
INIT_04 => X"B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4",
|
5292 |
|
|
INIT_05 => X"B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4",
|
5293 |
|
|
INIT_06 => X"B5B5B5B5B5B5B5B5B5B5B5B5B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4",
|
5294 |
|
|
INIT_07 => X"B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5",
|
5295 |
|
|
INIT_08 => X"B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5",
|
5296 |
|
|
INIT_09 => X"B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5",
|
5297 |
|
|
INIT_0A => X"B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5",
|
5298 |
|
|
INIT_0B => X"B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5",
|
5299 |
|
|
INIT_0C => X"B6B6B6B6B6B6B6B6B6B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5B5",
|
5300 |
|
|
INIT_0D => X"B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6",
|
5301 |
|
|
INIT_0E => X"B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6",
|
5302 |
|
|
INIT_0F => X"B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6",
|
5303 |
|
|
INIT_10 => X"B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6",
|
5304 |
|
|
INIT_11 => X"B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6",
|
5305 |
|
|
INIT_12 => X"B7B7B7B7B7B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6",
|
5306 |
|
|
INIT_13 => X"B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7",
|
5307 |
|
|
INIT_14 => X"B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7",
|
5308 |
|
|
INIT_15 => X"B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7",
|
5309 |
|
|
INIT_16 => X"B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7",
|
5310 |
|
|
INIT_17 => X"B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7",
|
5311 |
|
|
INIT_18 => X"B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B7",
|
5312 |
|
|
INIT_19 => X"B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8",
|
5313 |
|
|
INIT_1A => X"B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8",
|
5314 |
|
|
INIT_1B => X"B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8",
|
5315 |
|
|
INIT_1C => X"B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8",
|
5316 |
|
|
INIT_1D => X"B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8",
|
5317 |
|
|
INIT_1E => X"B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8B8",
|
5318 |
|
|
INIT_1F => X"B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B8B8B8B8B8B8B8",
|
5319 |
|
|
INIT_20 => X"B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9",
|
5320 |
|
|
INIT_21 => X"B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9",
|
5321 |
|
|
INIT_22 => X"B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9",
|
5322 |
|
|
INIT_23 => X"B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9",
|
5323 |
|
|
INIT_24 => X"B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9",
|
5324 |
|
|
INIT_25 => X"BABABABABABABABABABABABABABABABAB9B9B9B9B9B9B9B9B9B9B9B9B9B9B9B9",
|
5325 |
|
|
INIT_26 => X"BABABABABABABABABABABABABABABABABABABABABABABABABABABABABABABABA",
|
5326 |
|
|
INIT_27 => X"BABABABABABABABABABABABABABABABABABABABABABABABABABABABABABABABA",
|
5327 |
|
|
INIT_28 => X"BABABABABABABABABABABABABABABABABABABABABABABABABABABABABABABABA",
|
5328 |
|
|
INIT_29 => X"BABABABABABABABABABABABABABABABABABABABABABABABABABABABABABABABA",
|
5329 |
|
|
INIT_2A => X"BABABABABABABABABABABABABABABABABABABABABABABABABABABABABABABABA",
|
5330 |
|
|
INIT_2B => X"BBBBBBBBBBBBBABABABABABABABABABABABABABABABABABABABABABABABABABA",
|
5331 |
|
|
INIT_2C => X"BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB",
|
5332 |
|
|
INIT_2D => X"BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB",
|
5333 |
|
|
INIT_2E => X"BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB",
|
5334 |
|
|
INIT_2F => X"BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB",
|
5335 |
|
|
INIT_30 => X"BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB",
|
5336 |
|
|
INIT_31 => X"BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB",
|
5337 |
|
|
INIT_32 => X"BCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBBBBBBBBBBBB",
|
5338 |
|
|
INIT_33 => X"BCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBC",
|
5339 |
|
|
INIT_34 => X"BCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBC",
|
5340 |
|
|
INIT_35 => X"BCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBC",
|
5341 |
|
|
INIT_36 => X"BCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBC",
|
5342 |
|
|
INIT_37 => X"BCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBC",
|
5343 |
|
|
INIT_38 => X"BDBDBDBDBDBDBDBDBDBDBDBDBDBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBC",
|
5344 |
|
|
INIT_39 => X"BDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBD",
|
5345 |
|
|
INIT_3A => X"BDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBD",
|
5346 |
|
|
INIT_3B => X"BDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBD",
|
5347 |
|
|
INIT_3C => X"BDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBD",
|
5348 |
|
|
INIT_3D => X"BDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBD",
|
5349 |
|
|
INIT_3E => X"BDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBD",
|
5350 |
|
|
INIT_3F => X"BEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBDBD",
|
5351 |
|
|
INIT_40 => X"BEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBE",
|
5352 |
|
|
INIT_41 => X"BEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBE",
|
5353 |
|
|
INIT_42 => X"BEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBE",
|
5354 |
|
|
INIT_43 => X"BEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBE",
|
5355 |
|
|
INIT_44 => X"BEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBE",
|
5356 |
|
|
INIT_45 => X"BFBFBFBFBFBFBFBFBFBFBFBFBFBFBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBEBE",
|
5357 |
|
|
INIT_46 => X"BFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBF",
|
5358 |
|
|
INIT_47 => X"BFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBF",
|
5359 |
|
|
INIT_48 => X"BFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBF",
|
5360 |
|
|
INIT_49 => X"BFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBF",
|
5361 |
|
|
INIT_4A => X"BFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBF",
|
5362 |
|
|
INIT_4B => X"BFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBFBF",
|
5363 |
|
|
INIT_4C => X"C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0BFBFBFBFBF",
|
5364 |
|
|
INIT_4D => X"C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0",
|
5365 |
|
|
INIT_4E => X"C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0",
|
5366 |
|
|
INIT_4F => X"C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0",
|
5367 |
|
|
INIT_50 => X"C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0",
|
5368 |
|
|
INIT_51 => X"C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0",
|
5369 |
|
|
INIT_52 => X"C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0",
|
5370 |
|
|
INIT_53 => X"C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0",
|
5371 |
|
|
INIT_54 => X"C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0",
|
5372 |
|
|
INIT_55 => X"C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0",
|
5373 |
|
|
INIT_56 => X"C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0",
|
5374 |
|
|
INIT_57 => X"C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0",
|
5375 |
|
|
INIT_58 => X"C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0",
|
5376 |
|
|
INIT_59 => X"C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C0C0C0C0C0C0C0C0C0C0C0C0C0C0",
|
5377 |
|
|
INIT_5A => X"C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1",
|
5378 |
|
|
INIT_5B => X"C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1",
|
5379 |
|
|
INIT_5C => X"C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1",
|
5380 |
|
|
INIT_5D => X"C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1",
|
5381 |
|
|
INIT_5E => X"C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1",
|
5382 |
|
|
INIT_5F => X"C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1",
|
5383 |
|
|
INIT_60 => X"C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1",
|
5384 |
|
|
INIT_61 => X"C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1",
|
5385 |
|
|
INIT_62 => X"C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1",
|
5386 |
|
|
INIT_63 => X"C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1",
|
5387 |
|
|
INIT_64 => X"C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1",
|
5388 |
|
|
INIT_65 => X"C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1",
|
5389 |
|
|
INIT_66 => X"C2C2C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1",
|
5390 |
|
|
INIT_67 => X"C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2",
|
5391 |
|
|
INIT_68 => X"C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2",
|
5392 |
|
|
INIT_69 => X"C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2",
|
5393 |
|
|
INIT_6A => X"C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2",
|
5394 |
|
|
INIT_6B => X"C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2",
|
5395 |
|
|
INIT_6C => X"C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2",
|
5396 |
|
|
INIT_6D => X"C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2",
|
5397 |
|
|
INIT_6E => X"C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2",
|
5398 |
|
|
INIT_6F => X"C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2",
|
5399 |
|
|
INIT_70 => X"C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2",
|
5400 |
|
|
INIT_71 => X"C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2",
|
5401 |
|
|
INIT_72 => X"C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2",
|
5402 |
|
|
INIT_73 => X"C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2",
|
5403 |
|
|
INIT_74 => X"C3C3C3C3C3C3C3C3C3C3C3C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2C2",
|
5404 |
|
|
INIT_75 => X"C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3",
|
5405 |
|
|
INIT_76 => X"C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3",
|
5406 |
|
|
INIT_77 => X"C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3",
|
5407 |
|
|
INIT_78 => X"C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3",
|
5408 |
|
|
INIT_79 => X"C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3",
|
5409 |
|
|
INIT_7A => X"C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3",
|
5410 |
|
|
INIT_7B => X"C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3",
|
5411 |
|
|
INIT_7C => X"C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3",
|
5412 |
|
|
INIT_7D => X"C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3",
|
5413 |
|
|
INITP_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
5414 |
|
|
INIT_FILE => "NONE",
|
5415 |
|
|
RAM_EXTENSION_A => "NONE",
|
5416 |
|
|
RAM_EXTENSION_B => "NONE",
|
5417 |
|
|
READ_WIDTH_A => 9,
|
5418 |
|
|
READ_WIDTH_B => 9,
|
5419 |
|
|
SIM_COLLISION_CHECK => "ALL",
|
5420 |
|
|
SIM_MODE => "SAFE",
|
5421 |
|
|
INIT_A => X"000000000",
|
5422 |
|
|
INIT_B => X"000000000",
|
5423 |
|
|
WRITE_MODE_A => "WRITE_FIRST",
|
5424 |
|
|
WRITE_MODE_B => "WRITE_FIRST",
|
5425 |
|
|
WRITE_WIDTH_A => 9,
|
5426 |
|
|
WRITE_WIDTH_B => 9,
|
5427 |
|
|
INITP_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
|
5428 |
|
|
)
|
5429 |
|
|
port map (
|
5430 |
|
|
ENAU => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_2_cmp_eq0000,
|
5431 |
|
|
ENAL => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_2_cmp_eq0000,
|
5432 |
|
|
ENBU => BU2_doutb(0),
|
5433 |
|
|
ENBL => BU2_doutb(0),
|
5434 |
|
|
SSRAU => BU2_doutb(0),
|
5435 |
|
|
SSRAL => BU2_doutb(0),
|
5436 |
|
|
SSRBU => BU2_doutb(0),
|
5437 |
|
|
SSRBL => BU2_doutb(0),
|
5438 |
|
|
CLKAU => clka,
|
5439 |
|
|
CLKAL => clka,
|
5440 |
|
|
CLKBU => BU2_doutb(0),
|
5441 |
|
|
CLKBL => BU2_doutb(0),
|
5442 |
|
|
REGCLKAU => clka,
|
5443 |
|
|
REGCLKAL => clka,
|
5444 |
|
|
REGCLKBU => BU2_doutb(0),
|
5445 |
|
|
REGCLKBL => BU2_doutb(0),
|
5446 |
|
|
REGCEAU => BU2_doutb(0),
|
5447 |
|
|
REGCEAL => BU2_doutb(0),
|
5448 |
|
|
REGCEBU => BU2_doutb(0),
|
5449 |
|
|
REGCEBL => BU2_doutb(0),
|
5450 |
|
|
CASCADEINLATA => BU2_doutb(0),
|
5451 |
|
|
CASCADEINLATB => BU2_doutb(0),
|
5452 |
|
|
CASCADEINREGA => BU2_doutb(0),
|
5453 |
|
|
CASCADEINREGB => BU2_doutb(0),
|
5454 |
|
|
CASCADEOUTLATA => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATA_UNCONNECTED,
|
5455 |
|
|
CASCADEOUTLATB => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATB_UNCONNECTED,
|
5456 |
|
|
CASCADEOUTREGA => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGA_UNCONNECTED,
|
5457 |
|
|
CASCADEOUTREGB => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGB_UNCONNECTED,
|
5458 |
|
|
DIA(31) => BU2_doutb(0),
|
5459 |
|
|
DIA(30) => BU2_doutb(0),
|
5460 |
|
|
DIA(29) => BU2_doutb(0),
|
5461 |
|
|
DIA(28) => BU2_doutb(0),
|
5462 |
|
|
DIA(27) => BU2_doutb(0),
|
5463 |
|
|
DIA(26) => BU2_doutb(0),
|
5464 |
|
|
DIA(25) => BU2_doutb(0),
|
5465 |
|
|
DIA(24) => BU2_doutb(0),
|
5466 |
|
|
DIA(23) => BU2_doutb(0),
|
5467 |
|
|
DIA(22) => BU2_doutb(0),
|
5468 |
|
|
DIA(21) => BU2_doutb(0),
|
5469 |
|
|
DIA(20) => BU2_doutb(0),
|
5470 |
|
|
DIA(19) => BU2_doutb(0),
|
5471 |
|
|
DIA(18) => BU2_doutb(0),
|
5472 |
|
|
DIA(17) => BU2_doutb(0),
|
5473 |
|
|
DIA(16) => BU2_doutb(0),
|
5474 |
|
|
DIA(15) => BU2_doutb(0),
|
5475 |
|
|
DIA(14) => BU2_doutb(0),
|
5476 |
|
|
DIA(13) => BU2_doutb(0),
|
5477 |
|
|
DIA(12) => BU2_doutb(0),
|
5478 |
|
|
DIA(11) => BU2_doutb(0),
|
5479 |
|
|
DIA(10) => BU2_doutb(0),
|
5480 |
|
|
DIA(9) => BU2_doutb(0),
|
5481 |
|
|
DIA(8) => BU2_doutb(0),
|
5482 |
|
|
DIA(7) => BU2_doutb(0),
|
5483 |
|
|
DIA(6) => BU2_doutb(0),
|
5484 |
|
|
DIA(5) => BU2_doutb(0),
|
5485 |
|
|
DIA(4) => BU2_doutb(0),
|
5486 |
|
|
DIA(3) => BU2_doutb(0),
|
5487 |
|
|
DIA(2) => BU2_doutb(0),
|
5488 |
|
|
DIA(1) => BU2_doutb(0),
|
5489 |
|
|
DIA(0) => BU2_doutb(0),
|
5490 |
|
|
DIPA(3) => BU2_doutb(0),
|
5491 |
|
|
DIPA(2) => BU2_doutb(0),
|
5492 |
|
|
DIPA(1) => BU2_doutb(0),
|
5493 |
|
|
DIPA(0) => BU2_doutb(0),
|
5494 |
|
|
DIB(31) => BU2_doutb(0),
|
5495 |
|
|
DIB(30) => BU2_doutb(0),
|
5496 |
|
|
DIB(29) => BU2_doutb(0),
|
5497 |
|
|
DIB(28) => BU2_doutb(0),
|
5498 |
|
|
DIB(27) => BU2_doutb(0),
|
5499 |
|
|
DIB(26) => BU2_doutb(0),
|
5500 |
|
|
DIB(25) => BU2_doutb(0),
|
5501 |
|
|
DIB(24) => BU2_doutb(0),
|
5502 |
|
|
DIB(23) => BU2_doutb(0),
|
5503 |
|
|
DIB(22) => BU2_doutb(0),
|
5504 |
|
|
DIB(21) => BU2_doutb(0),
|
5505 |
|
|
DIB(20) => BU2_doutb(0),
|
5506 |
|
|
DIB(19) => BU2_doutb(0),
|
5507 |
|
|
DIB(18) => BU2_doutb(0),
|
5508 |
|
|
DIB(17) => BU2_doutb(0),
|
5509 |
|
|
DIB(16) => BU2_doutb(0),
|
5510 |
|
|
DIB(15) => BU2_doutb(0),
|
5511 |
|
|
DIB(14) => BU2_doutb(0),
|
5512 |
|
|
DIB(13) => BU2_doutb(0),
|
5513 |
|
|
DIB(12) => BU2_doutb(0),
|
5514 |
|
|
DIB(11) => BU2_doutb(0),
|
5515 |
|
|
DIB(10) => BU2_doutb(0),
|
5516 |
|
|
DIB(9) => BU2_doutb(0),
|
5517 |
|
|
DIB(8) => BU2_doutb(0),
|
5518 |
|
|
DIB(7) => BU2_doutb(0),
|
5519 |
|
|
DIB(6) => BU2_doutb(0),
|
5520 |
|
|
DIB(5) => BU2_doutb(0),
|
5521 |
|
|
DIB(4) => BU2_doutb(0),
|
5522 |
|
|
DIB(3) => BU2_doutb(0),
|
5523 |
|
|
DIB(2) => BU2_doutb(0),
|
5524 |
|
|
DIB(1) => BU2_doutb(0),
|
5525 |
|
|
DIB(0) => BU2_doutb(0),
|
5526 |
|
|
DIPB(3) => BU2_doutb(0),
|
5527 |
|
|
DIPB(2) => BU2_doutb(0),
|
5528 |
|
|
DIPB(1) => BU2_doutb(0),
|
5529 |
|
|
DIPB(0) => BU2_doutb(0),
|
5530 |
|
|
ADDRAL(15) => BU2_doutb(0),
|
5531 |
|
|
ADDRAL(14) => addra_2(11),
|
5532 |
|
|
ADDRAL(13) => addra_2(10),
|
5533 |
|
|
ADDRAL(12) => addra_2(9),
|
5534 |
|
|
ADDRAL(11) => addra_2(8),
|
5535 |
|
|
ADDRAL(10) => addra_2(7),
|
5536 |
|
|
ADDRAL(9) => addra_2(6),
|
5537 |
|
|
ADDRAL(8) => addra_2(5),
|
5538 |
|
|
ADDRAL(7) => addra_2(4),
|
5539 |
|
|
ADDRAL(6) => addra_2(3),
|
5540 |
|
|
ADDRAL(5) => addra_2(2),
|
5541 |
|
|
ADDRAL(4) => addra_2(1),
|
5542 |
|
|
ADDRAL(3) => addra_2(0),
|
5543 |
|
|
ADDRAL(2) => BU2_doutb(0),
|
5544 |
|
|
ADDRAL(1) => BU2_doutb(0),
|
5545 |
|
|
ADDRAL(0) => BU2_doutb(0),
|
5546 |
|
|
ADDRAU(14) => addra_2(11),
|
5547 |
|
|
ADDRAU(13) => addra_2(10),
|
5548 |
|
|
ADDRAU(12) => addra_2(9),
|
5549 |
|
|
ADDRAU(11) => addra_2(8),
|
5550 |
|
|
ADDRAU(10) => addra_2(7),
|
5551 |
|
|
ADDRAU(9) => addra_2(6),
|
5552 |
|
|
ADDRAU(8) => addra_2(5),
|
5553 |
|
|
ADDRAU(7) => addra_2(4),
|
5554 |
|
|
ADDRAU(6) => addra_2(3),
|
5555 |
|
|
ADDRAU(5) => addra_2(2),
|
5556 |
|
|
ADDRAU(4) => addra_2(1),
|
5557 |
|
|
ADDRAU(3) => addra_2(0),
|
5558 |
|
|
ADDRAU(2) => BU2_doutb(0),
|
5559 |
|
|
ADDRAU(1) => BU2_doutb(0),
|
5560 |
|
|
ADDRAU(0) => BU2_doutb(0),
|
5561 |
|
|
ADDRBL(15) => BU2_doutb(0),
|
5562 |
|
|
ADDRBL(14) => BU2_doutb(0),
|
5563 |
|
|
ADDRBL(13) => BU2_doutb(0),
|
5564 |
|
|
ADDRBL(12) => BU2_doutb(0),
|
5565 |
|
|
ADDRBL(11) => BU2_doutb(0),
|
5566 |
|
|
ADDRBL(10) => BU2_doutb(0),
|
5567 |
|
|
ADDRBL(9) => BU2_doutb(0),
|
5568 |
|
|
ADDRBL(8) => BU2_doutb(0),
|
5569 |
|
|
ADDRBL(7) => BU2_doutb(0),
|
5570 |
|
|
ADDRBL(6) => BU2_doutb(0),
|
5571 |
|
|
ADDRBL(5) => BU2_doutb(0),
|
5572 |
|
|
ADDRBL(4) => BU2_doutb(0),
|
5573 |
|
|
ADDRBL(3) => BU2_doutb(0),
|
5574 |
|
|
ADDRBL(2) => BU2_doutb(0),
|
5575 |
|
|
ADDRBL(1) => BU2_doutb(0),
|
5576 |
|
|
ADDRBL(0) => BU2_doutb(0),
|
5577 |
|
|
ADDRBU(14) => BU2_doutb(0),
|
5578 |
|
|
ADDRBU(13) => BU2_doutb(0),
|
5579 |
|
|
ADDRBU(12) => BU2_doutb(0),
|
5580 |
|
|
ADDRBU(11) => BU2_doutb(0),
|
5581 |
|
|
ADDRBU(10) => BU2_doutb(0),
|
5582 |
|
|
ADDRBU(9) => BU2_doutb(0),
|
5583 |
|
|
ADDRBU(8) => BU2_doutb(0),
|
5584 |
|
|
ADDRBU(7) => BU2_doutb(0),
|
5585 |
|
|
ADDRBU(6) => BU2_doutb(0),
|
5586 |
|
|
ADDRBU(5) => BU2_doutb(0),
|
5587 |
|
|
ADDRBU(4) => BU2_doutb(0),
|
5588 |
|
|
ADDRBU(3) => BU2_doutb(0),
|
5589 |
|
|
ADDRBU(2) => BU2_doutb(0),
|
5590 |
|
|
ADDRBU(1) => BU2_doutb(0),
|
5591 |
|
|
ADDRBU(0) => BU2_doutb(0),
|
5592 |
|
|
WEAU(3) => BU2_doutb(0),
|
5593 |
|
|
WEAU(2) => BU2_doutb(0),
|
5594 |
|
|
WEAU(1) => BU2_doutb(0),
|
5595 |
|
|
WEAU(0) => BU2_doutb(0),
|
5596 |
|
|
WEAL(3) => BU2_doutb(0),
|
5597 |
|
|
WEAL(2) => BU2_doutb(0),
|
5598 |
|
|
WEAL(1) => BU2_doutb(0),
|
5599 |
|
|
WEAL(0) => BU2_doutb(0),
|
5600 |
|
|
WEBU(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_7_UNCONNECTED,
|
5601 |
|
|
WEBU(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_6_UNCONNECTED,
|
5602 |
|
|
WEBU(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_5_UNCONNECTED,
|
5603 |
|
|
WEBU(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_4_UNCONNECTED,
|
5604 |
|
|
WEBU(3) => BU2_doutb(0),
|
5605 |
|
|
WEBU(2) => BU2_doutb(0),
|
5606 |
|
|
WEBU(1) => BU2_doutb(0),
|
5607 |
|
|
WEBU(0) => BU2_doutb(0),
|
5608 |
|
|
WEBL(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_7_UNCONNECTED,
|
5609 |
|
|
WEBL(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_6_UNCONNECTED,
|
5610 |
|
|
WEBL(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_5_UNCONNECTED,
|
5611 |
|
|
WEBL(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_4_UNCONNECTED,
|
5612 |
|
|
WEBL(3) => BU2_doutb(0),
|
5613 |
|
|
WEBL(2) => BU2_doutb(0),
|
5614 |
|
|
WEBL(1) => BU2_doutb(0),
|
5615 |
|
|
WEBL(0) => BU2_doutb(0),
|
5616 |
|
|
DOA(31) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_31_UNCONNECTED,
|
5617 |
|
|
DOA(30) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_30_UNCONNECTED,
|
5618 |
|
|
DOA(29) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_29_UNCONNECTED,
|
5619 |
|
|
DOA(28) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_28_UNCONNECTED,
|
5620 |
|
|
DOA(27) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_27_UNCONNECTED,
|
5621 |
|
|
DOA(26) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_26_UNCONNECTED,
|
5622 |
|
|
DOA(25) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_25_UNCONNECTED,
|
5623 |
|
|
DOA(24) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_24_UNCONNECTED,
|
5624 |
|
|
DOA(23) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_23_UNCONNECTED,
|
5625 |
|
|
DOA(22) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_22_UNCONNECTED,
|
5626 |
|
|
DOA(21) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_21_UNCONNECTED,
|
5627 |
|
|
DOA(20) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_20_UNCONNECTED,
|
5628 |
|
|
DOA(19) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_19_UNCONNECTED,
|
5629 |
|
|
DOA(18) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_18_UNCONNECTED,
|
5630 |
|
|
DOA(17) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_17_UNCONNECTED,
|
5631 |
|
|
DOA(16) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_16_UNCONNECTED,
|
5632 |
|
|
DOA(15) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_15_UNCONNECTED,
|
5633 |
|
|
DOA(14) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_14_UNCONNECTED,
|
5634 |
|
|
DOA(13) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_13_UNCONNECTED,
|
5635 |
|
|
DOA(12) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_12_UNCONNECTED,
|
5636 |
|
|
DOA(11) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_11_UNCONNECTED,
|
5637 |
|
|
DOA(10) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_10_UNCONNECTED,
|
5638 |
|
|
DOA(9) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_9_UNCONNECTED,
|
5639 |
|
|
DOA(8) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_8_UNCONNECTED,
|
5640 |
|
|
DOA(7) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta9(7),
|
5641 |
|
|
DOA(6) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta9(6),
|
5642 |
|
|
DOA(5) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta9(5),
|
5643 |
|
|
DOA(4) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta9(4),
|
5644 |
|
|
DOA(3) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta9(3),
|
5645 |
|
|
DOA(2) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta9(2),
|
5646 |
|
|
DOA(1) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta9(1),
|
5647 |
|
|
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta9(0),
|
5648 |
|
|
DOPA(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_3_UNCONNECTED,
|
5649 |
|
|
DOPA(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_2_UNCONNECTED,
|
5650 |
|
|
DOPA(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_1_UNCONNECTED,
|
5651 |
|
|
DOPA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta9(8),
|
5652 |
|
|
DOB(31) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_31_UNCONNECTED,
|
5653 |
|
|
DOB(30) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_30_UNCONNECTED,
|
5654 |
|
|
DOB(29) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_29_UNCONNECTED,
|
5655 |
|
|
DOB(28) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_28_UNCONNECTED,
|
5656 |
|
|
DOB(27) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_27_UNCONNECTED,
|
5657 |
|
|
DOB(26) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_26_UNCONNECTED,
|
5658 |
|
|
DOB(25) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_25_UNCONNECTED,
|
5659 |
|
|
DOB(24) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_24_UNCONNECTED,
|
5660 |
|
|
DOB(23) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_23_UNCONNECTED,
|
5661 |
|
|
DOB(22) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_22_UNCONNECTED,
|
5662 |
|
|
DOB(21) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_21_UNCONNECTED,
|
5663 |
|
|
DOB(20) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_20_UNCONNECTED,
|
5664 |
|
|
DOB(19) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_19_UNCONNECTED,
|
5665 |
|
|
DOB(18) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_18_UNCONNECTED,
|
5666 |
|
|
DOB(17) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_17_UNCONNECTED,
|
5667 |
|
|
DOB(16) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_16_UNCONNECTED,
|
5668 |
|
|
DOB(15) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_15_UNCONNECTED,
|
5669 |
|
|
DOB(14) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_14_UNCONNECTED,
|
5670 |
|
|
DOB(13) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_13_UNCONNECTED,
|
5671 |
|
|
DOB(12) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_12_UNCONNECTED,
|
5672 |
|
|
DOB(11) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_11_UNCONNECTED,
|
5673 |
|
|
DOB(10) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_10_UNCONNECTED,
|
5674 |
|
|
DOB(9) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_9_UNCONNECTED,
|
5675 |
|
|
DOB(8) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_8_UNCONNECTED,
|
5676 |
|
|
DOB(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_7_UNCONNECTED,
|
5677 |
|
|
DOB(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_6_UNCONNECTED,
|
5678 |
|
|
DOB(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_5_UNCONNECTED,
|
5679 |
|
|
DOB(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_4_UNCONNECTED,
|
5680 |
|
|
DOB(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_3_UNCONNECTED,
|
5681 |
|
|
DOB(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_2_UNCONNECTED,
|
5682 |
|
|
DOB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_1_UNCONNECTED,
|
5683 |
|
|
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_0_UNCONNECTED,
|
5684 |
|
|
DOPB(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_3_UNCONNECTED,
|
5685 |
|
|
DOPB(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_2_UNCONNECTED,
|
5686 |
|
|
DOPB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_1_UNCONNECTED,
|
5687 |
|
|
DOPB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_0_UNCONNECTED
|
5688 |
|
|
);
|
5689 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP : RAMB36_EXP
|
5690 |
|
|
generic map(
|
5691 |
|
|
DOA_REG => 0,
|
5692 |
|
|
DOB_REG => 0,
|
5693 |
|
|
INIT_7E => X"CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC",
|
5694 |
|
|
INIT_7F => X"CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC",
|
5695 |
|
|
INITP_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
5696 |
|
|
INITP_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
5697 |
|
|
INITP_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
5698 |
|
|
INITP_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
5699 |
|
|
INITP_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
5700 |
|
|
INITP_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
5701 |
|
|
INITP_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
5702 |
|
|
INITP_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
5703 |
|
|
INITP_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
5704 |
|
|
INITP_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
5705 |
|
|
INITP_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
5706 |
|
|
INITP_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
5707 |
|
|
INITP_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
5708 |
|
|
INITP_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
5709 |
|
|
SRVAL_A => X"000000000",
|
5710 |
|
|
SRVAL_B => X"000000000",
|
5711 |
|
|
INIT_00 => X"C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3",
|
5712 |
|
|
INIT_01 => X"C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3",
|
5713 |
|
|
INIT_02 => X"C4C4C4C4C4C4C4C4C4C4C4C4C4C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3",
|
5714 |
|
|
INIT_03 => X"C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4",
|
5715 |
|
|
INIT_04 => X"C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4",
|
5716 |
|
|
INIT_05 => X"C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4",
|
5717 |
|
|
INIT_06 => X"C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4",
|
5718 |
|
|
INIT_07 => X"C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4",
|
5719 |
|
|
INIT_08 => X"C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4",
|
5720 |
|
|
INIT_09 => X"C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4",
|
5721 |
|
|
INIT_0A => X"C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4",
|
5722 |
|
|
INIT_0B => X"C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4",
|
5723 |
|
|
INIT_0C => X"C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4",
|
5724 |
|
|
INIT_0D => X"C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4",
|
5725 |
|
|
INIT_0E => X"C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4",
|
5726 |
|
|
INIT_0F => X"C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4",
|
5727 |
|
|
INIT_10 => X"C5C5C5C5C5C5C5C5C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4",
|
5728 |
|
|
INIT_11 => X"C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5",
|
5729 |
|
|
INIT_12 => X"C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5",
|
5730 |
|
|
INIT_13 => X"C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5",
|
5731 |
|
|
INIT_14 => X"C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5",
|
5732 |
|
|
INIT_15 => X"C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5",
|
5733 |
|
|
INIT_16 => X"C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5",
|
5734 |
|
|
INIT_17 => X"C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5",
|
5735 |
|
|
INIT_18 => X"C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5",
|
5736 |
|
|
INIT_19 => X"C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5",
|
5737 |
|
|
INIT_1A => X"C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5",
|
5738 |
|
|
INIT_1B => X"C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5",
|
5739 |
|
|
INIT_1C => X"C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5",
|
5740 |
|
|
INIT_1D => X"C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5",
|
5741 |
|
|
INIT_1E => X"C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5C5",
|
5742 |
|
|
INIT_1F => X"C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C5C5C5C5",
|
5743 |
|
|
INIT_20 => X"C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6",
|
5744 |
|
|
INIT_21 => X"C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6",
|
5745 |
|
|
INIT_22 => X"C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6",
|
5746 |
|
|
INIT_23 => X"C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6",
|
5747 |
|
|
INIT_24 => X"C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6",
|
5748 |
|
|
INIT_25 => X"C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6",
|
5749 |
|
|
INIT_26 => X"C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6",
|
5750 |
|
|
INIT_27 => X"C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6",
|
5751 |
|
|
INIT_28 => X"C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6",
|
5752 |
|
|
INIT_29 => X"C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6",
|
5753 |
|
|
INIT_2A => X"C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6",
|
5754 |
|
|
INIT_2B => X"C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6",
|
5755 |
|
|
INIT_2C => X"C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6",
|
5756 |
|
|
INIT_2D => X"C7C7C7C7C7C7C7C7C7C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6",
|
5757 |
|
|
INIT_2E => X"C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7",
|
5758 |
|
|
INIT_2F => X"C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7",
|
5759 |
|
|
INIT_30 => X"C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7",
|
5760 |
|
|
INIT_31 => X"C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7",
|
5761 |
|
|
INIT_32 => X"C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7",
|
5762 |
|
|
INIT_33 => X"C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7",
|
5763 |
|
|
INIT_34 => X"C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7",
|
5764 |
|
|
INIT_35 => X"C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7",
|
5765 |
|
|
INIT_36 => X"C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7",
|
5766 |
|
|
INIT_37 => X"C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7",
|
5767 |
|
|
INIT_38 => X"C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7",
|
5768 |
|
|
INIT_39 => X"C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7",
|
5769 |
|
|
INIT_3A => X"C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7",
|
5770 |
|
|
INIT_3B => X"C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7",
|
5771 |
|
|
INIT_3C => X"C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7",
|
5772 |
|
|
INIT_3D => X"C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8",
|
5773 |
|
|
INIT_3E => X"C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8",
|
5774 |
|
|
INIT_3F => X"C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8",
|
5775 |
|
|
INIT_40 => X"C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8",
|
5776 |
|
|
INIT_41 => X"C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8",
|
5777 |
|
|
INIT_42 => X"C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8",
|
5778 |
|
|
INIT_43 => X"C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8",
|
5779 |
|
|
INIT_44 => X"C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8",
|
5780 |
|
|
INIT_45 => X"C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8",
|
5781 |
|
|
INIT_46 => X"C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8",
|
5782 |
|
|
INIT_47 => X"C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8",
|
5783 |
|
|
INIT_48 => X"C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8",
|
5784 |
|
|
INIT_49 => X"C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8",
|
5785 |
|
|
INIT_4A => X"C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8",
|
5786 |
|
|
INIT_4B => X"C9C9C9C9C9C9C9C9C9C9C9C9C9C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8C8",
|
5787 |
|
|
INIT_4C => X"C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9",
|
5788 |
|
|
INIT_4D => X"C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9",
|
5789 |
|
|
INIT_4E => X"C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9",
|
5790 |
|
|
INIT_4F => X"C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9",
|
5791 |
|
|
INIT_50 => X"C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9",
|
5792 |
|
|
INIT_51 => X"C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9",
|
5793 |
|
|
INIT_52 => X"C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9",
|
5794 |
|
|
INIT_53 => X"C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9",
|
5795 |
|
|
INIT_54 => X"C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9",
|
5796 |
|
|
INIT_55 => X"C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9",
|
5797 |
|
|
INIT_56 => X"C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9",
|
5798 |
|
|
INIT_57 => X"C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9",
|
5799 |
|
|
INIT_58 => X"C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9",
|
5800 |
|
|
INIT_59 => X"C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9",
|
5801 |
|
|
INIT_5A => X"CACACAC9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9C9",
|
5802 |
|
|
INIT_5B => X"CACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACA",
|
5803 |
|
|
INIT_5C => X"CACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACA",
|
5804 |
|
|
INIT_5D => X"CACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACA",
|
5805 |
|
|
INIT_5E => X"CACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACA",
|
5806 |
|
|
INIT_5F => X"CACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACA",
|
5807 |
|
|
INIT_60 => X"CACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACA",
|
5808 |
|
|
INIT_61 => X"CACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACA",
|
5809 |
|
|
INIT_62 => X"CACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACA",
|
5810 |
|
|
INIT_63 => X"CACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACA",
|
5811 |
|
|
INIT_64 => X"CACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACA",
|
5812 |
|
|
INIT_65 => X"CACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACA",
|
5813 |
|
|
INIT_66 => X"CACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACA",
|
5814 |
|
|
INIT_67 => X"CACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACA",
|
5815 |
|
|
INIT_68 => X"CACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACA",
|
5816 |
|
|
INIT_69 => X"CACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACACA",
|
5817 |
|
|
INIT_6A => X"CBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCACACACACACACACACACACACACACA",
|
5818 |
|
|
INIT_6B => X"CBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCB",
|
5819 |
|
|
INIT_6C => X"CBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCB",
|
5820 |
|
|
INIT_6D => X"CBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCB",
|
5821 |
|
|
INIT_6E => X"CBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCB",
|
5822 |
|
|
INIT_6F => X"CBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCB",
|
5823 |
|
|
INIT_70 => X"CBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCB",
|
5824 |
|
|
INIT_71 => X"CBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCB",
|
5825 |
|
|
INIT_72 => X"CBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCB",
|
5826 |
|
|
INIT_73 => X"CBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCB",
|
5827 |
|
|
INIT_74 => X"CBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCB",
|
5828 |
|
|
INIT_75 => X"CBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCB",
|
5829 |
|
|
INIT_76 => X"CBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCB",
|
5830 |
|
|
INIT_77 => X"CBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCB",
|
5831 |
|
|
INIT_78 => X"CBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCB",
|
5832 |
|
|
INIT_79 => X"CBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCBCB",
|
5833 |
|
|
INIT_7A => X"CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCBCBCBCBCBCBCB",
|
5834 |
|
|
INIT_7B => X"CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC",
|
5835 |
|
|
INIT_7C => X"CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC",
|
5836 |
|
|
INIT_7D => X"CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC",
|
5837 |
|
|
INITP_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
|
5838 |
|
|
INIT_FILE => "NONE",
|
5839 |
|
|
RAM_EXTENSION_A => "NONE",
|
5840 |
|
|
RAM_EXTENSION_B => "NONE",
|
5841 |
|
|
READ_WIDTH_A => 9,
|
5842 |
|
|
READ_WIDTH_B => 9,
|
5843 |
|
|
SIM_COLLISION_CHECK => "ALL",
|
5844 |
|
|
SIM_MODE => "SAFE",
|
5845 |
|
|
INIT_A => X"000000000",
|
5846 |
|
|
INIT_B => X"000000000",
|
5847 |
|
|
WRITE_MODE_A => "WRITE_FIRST",
|
5848 |
|
|
WRITE_MODE_B => "WRITE_FIRST",
|
5849 |
|
|
WRITE_WIDTH_A => 9,
|
5850 |
|
|
WRITE_WIDTH_B => 9,
|
5851 |
|
|
INITP_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
|
5852 |
|
|
)
|
5853 |
|
|
port map (
|
5854 |
|
|
ENAU => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_3_cmp_eq0000,
|
5855 |
|
|
ENAL => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_3_cmp_eq0000,
|
5856 |
|
|
ENBU => BU2_doutb(0),
|
5857 |
|
|
ENBL => BU2_doutb(0),
|
5858 |
|
|
SSRAU => BU2_doutb(0),
|
5859 |
|
|
SSRAL => BU2_doutb(0),
|
5860 |
|
|
SSRBU => BU2_doutb(0),
|
5861 |
|
|
SSRBL => BU2_doutb(0),
|
5862 |
|
|
CLKAU => clka,
|
5863 |
|
|
CLKAL => clka,
|
5864 |
|
|
CLKBU => BU2_doutb(0),
|
5865 |
|
|
CLKBL => BU2_doutb(0),
|
5866 |
|
|
REGCLKAU => clka,
|
5867 |
|
|
REGCLKAL => clka,
|
5868 |
|
|
REGCLKBU => BU2_doutb(0),
|
5869 |
|
|
REGCLKBL => BU2_doutb(0),
|
5870 |
|
|
REGCEAU => BU2_doutb(0),
|
5871 |
|
|
REGCEAL => BU2_doutb(0),
|
5872 |
|
|
REGCEBU => BU2_doutb(0),
|
5873 |
|
|
REGCEBL => BU2_doutb(0),
|
5874 |
|
|
CASCADEINLATA => BU2_doutb(0),
|
5875 |
|
|
CASCADEINLATB => BU2_doutb(0),
|
5876 |
|
|
CASCADEINREGA => BU2_doutb(0),
|
5877 |
|
|
CASCADEINREGB => BU2_doutb(0),
|
5878 |
|
|
CASCADEOUTLATA => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATA_UNCONNECTED,
|
5879 |
|
|
CASCADEOUTLATB => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTLATB_UNCONNECTED,
|
5880 |
|
|
CASCADEOUTREGA => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGA_UNCONNECTED,
|
5881 |
|
|
CASCADEOUTREGB => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_CASCADEOUTREGB_UNCONNECTED,
|
5882 |
|
|
DIA(31) => BU2_doutb(0),
|
5883 |
|
|
DIA(30) => BU2_doutb(0),
|
5884 |
|
|
DIA(29) => BU2_doutb(0),
|
5885 |
|
|
DIA(28) => BU2_doutb(0),
|
5886 |
|
|
DIA(27) => BU2_doutb(0),
|
5887 |
|
|
DIA(26) => BU2_doutb(0),
|
5888 |
|
|
DIA(25) => BU2_doutb(0),
|
5889 |
|
|
DIA(24) => BU2_doutb(0),
|
5890 |
|
|
DIA(23) => BU2_doutb(0),
|
5891 |
|
|
DIA(22) => BU2_doutb(0),
|
5892 |
|
|
DIA(21) => BU2_doutb(0),
|
5893 |
|
|
DIA(20) => BU2_doutb(0),
|
5894 |
|
|
DIA(19) => BU2_doutb(0),
|
5895 |
|
|
DIA(18) => BU2_doutb(0),
|
5896 |
|
|
DIA(17) => BU2_doutb(0),
|
5897 |
|
|
DIA(16) => BU2_doutb(0),
|
5898 |
|
|
DIA(15) => BU2_doutb(0),
|
5899 |
|
|
DIA(14) => BU2_doutb(0),
|
5900 |
|
|
DIA(13) => BU2_doutb(0),
|
5901 |
|
|
DIA(12) => BU2_doutb(0),
|
5902 |
|
|
DIA(11) => BU2_doutb(0),
|
5903 |
|
|
DIA(10) => BU2_doutb(0),
|
5904 |
|
|
DIA(9) => BU2_doutb(0),
|
5905 |
|
|
DIA(8) => BU2_doutb(0),
|
5906 |
|
|
DIA(7) => BU2_doutb(0),
|
5907 |
|
|
DIA(6) => BU2_doutb(0),
|
5908 |
|
|
DIA(5) => BU2_doutb(0),
|
5909 |
|
|
DIA(4) => BU2_doutb(0),
|
5910 |
|
|
DIA(3) => BU2_doutb(0),
|
5911 |
|
|
DIA(2) => BU2_doutb(0),
|
5912 |
|
|
DIA(1) => BU2_doutb(0),
|
5913 |
|
|
DIA(0) => BU2_doutb(0),
|
5914 |
|
|
DIPA(3) => BU2_doutb(0),
|
5915 |
|
|
DIPA(2) => BU2_doutb(0),
|
5916 |
|
|
DIPA(1) => BU2_doutb(0),
|
5917 |
|
|
DIPA(0) => BU2_doutb(0),
|
5918 |
|
|
DIB(31) => BU2_doutb(0),
|
5919 |
|
|
DIB(30) => BU2_doutb(0),
|
5920 |
|
|
DIB(29) => BU2_doutb(0),
|
5921 |
|
|
DIB(28) => BU2_doutb(0),
|
5922 |
|
|
DIB(27) => BU2_doutb(0),
|
5923 |
|
|
DIB(26) => BU2_doutb(0),
|
5924 |
|
|
DIB(25) => BU2_doutb(0),
|
5925 |
|
|
DIB(24) => BU2_doutb(0),
|
5926 |
|
|
DIB(23) => BU2_doutb(0),
|
5927 |
|
|
DIB(22) => BU2_doutb(0),
|
5928 |
|
|
DIB(21) => BU2_doutb(0),
|
5929 |
|
|
DIB(20) => BU2_doutb(0),
|
5930 |
|
|
DIB(19) => BU2_doutb(0),
|
5931 |
|
|
DIB(18) => BU2_doutb(0),
|
5932 |
|
|
DIB(17) => BU2_doutb(0),
|
5933 |
|
|
DIB(16) => BU2_doutb(0),
|
5934 |
|
|
DIB(15) => BU2_doutb(0),
|
5935 |
|
|
DIB(14) => BU2_doutb(0),
|
5936 |
|
|
DIB(13) => BU2_doutb(0),
|
5937 |
|
|
DIB(12) => BU2_doutb(0),
|
5938 |
|
|
DIB(11) => BU2_doutb(0),
|
5939 |
|
|
DIB(10) => BU2_doutb(0),
|
5940 |
|
|
DIB(9) => BU2_doutb(0),
|
5941 |
|
|
DIB(8) => BU2_doutb(0),
|
5942 |
|
|
DIB(7) => BU2_doutb(0),
|
5943 |
|
|
DIB(6) => BU2_doutb(0),
|
5944 |
|
|
DIB(5) => BU2_doutb(0),
|
5945 |
|
|
DIB(4) => BU2_doutb(0),
|
5946 |
|
|
DIB(3) => BU2_doutb(0),
|
5947 |
|
|
DIB(2) => BU2_doutb(0),
|
5948 |
|
|
DIB(1) => BU2_doutb(0),
|
5949 |
|
|
DIB(0) => BU2_doutb(0),
|
5950 |
|
|
DIPB(3) => BU2_doutb(0),
|
5951 |
|
|
DIPB(2) => BU2_doutb(0),
|
5952 |
|
|
DIPB(1) => BU2_doutb(0),
|
5953 |
|
|
DIPB(0) => BU2_doutb(0),
|
5954 |
|
|
ADDRAL(15) => BU2_doutb(0),
|
5955 |
|
|
ADDRAL(14) => addra_2(11),
|
5956 |
|
|
ADDRAL(13) => addra_2(10),
|
5957 |
|
|
ADDRAL(12) => addra_2(9),
|
5958 |
|
|
ADDRAL(11) => addra_2(8),
|
5959 |
|
|
ADDRAL(10) => addra_2(7),
|
5960 |
|
|
ADDRAL(9) => addra_2(6),
|
5961 |
|
|
ADDRAL(8) => addra_2(5),
|
5962 |
|
|
ADDRAL(7) => addra_2(4),
|
5963 |
|
|
ADDRAL(6) => addra_2(3),
|
5964 |
|
|
ADDRAL(5) => addra_2(2),
|
5965 |
|
|
ADDRAL(4) => addra_2(1),
|
5966 |
|
|
ADDRAL(3) => addra_2(0),
|
5967 |
|
|
ADDRAL(2) => BU2_doutb(0),
|
5968 |
|
|
ADDRAL(1) => BU2_doutb(0),
|
5969 |
|
|
ADDRAL(0) => BU2_doutb(0),
|
5970 |
|
|
ADDRAU(14) => addra_2(11),
|
5971 |
|
|
ADDRAU(13) => addra_2(10),
|
5972 |
|
|
ADDRAU(12) => addra_2(9),
|
5973 |
|
|
ADDRAU(11) => addra_2(8),
|
5974 |
|
|
ADDRAU(10) => addra_2(7),
|
5975 |
|
|
ADDRAU(9) => addra_2(6),
|
5976 |
|
|
ADDRAU(8) => addra_2(5),
|
5977 |
|
|
ADDRAU(7) => addra_2(4),
|
5978 |
|
|
ADDRAU(6) => addra_2(3),
|
5979 |
|
|
ADDRAU(5) => addra_2(2),
|
5980 |
|
|
ADDRAU(4) => addra_2(1),
|
5981 |
|
|
ADDRAU(3) => addra_2(0),
|
5982 |
|
|
ADDRAU(2) => BU2_doutb(0),
|
5983 |
|
|
ADDRAU(1) => BU2_doutb(0),
|
5984 |
|
|
ADDRAU(0) => BU2_doutb(0),
|
5985 |
|
|
ADDRBL(15) => BU2_doutb(0),
|
5986 |
|
|
ADDRBL(14) => BU2_doutb(0),
|
5987 |
|
|
ADDRBL(13) => BU2_doutb(0),
|
5988 |
|
|
ADDRBL(12) => BU2_doutb(0),
|
5989 |
|
|
ADDRBL(11) => BU2_doutb(0),
|
5990 |
|
|
ADDRBL(10) => BU2_doutb(0),
|
5991 |
|
|
ADDRBL(9) => BU2_doutb(0),
|
5992 |
|
|
ADDRBL(8) => BU2_doutb(0),
|
5993 |
|
|
ADDRBL(7) => BU2_doutb(0),
|
5994 |
|
|
ADDRBL(6) => BU2_doutb(0),
|
5995 |
|
|
ADDRBL(5) => BU2_doutb(0),
|
5996 |
|
|
ADDRBL(4) => BU2_doutb(0),
|
5997 |
|
|
ADDRBL(3) => BU2_doutb(0),
|
5998 |
|
|
ADDRBL(2) => BU2_doutb(0),
|
5999 |
|
|
ADDRBL(1) => BU2_doutb(0),
|
6000 |
|
|
ADDRBL(0) => BU2_doutb(0),
|
6001 |
|
|
ADDRBU(14) => BU2_doutb(0),
|
6002 |
|
|
ADDRBU(13) => BU2_doutb(0),
|
6003 |
|
|
ADDRBU(12) => BU2_doutb(0),
|
6004 |
|
|
ADDRBU(11) => BU2_doutb(0),
|
6005 |
|
|
ADDRBU(10) => BU2_doutb(0),
|
6006 |
|
|
ADDRBU(9) => BU2_doutb(0),
|
6007 |
|
|
ADDRBU(8) => BU2_doutb(0),
|
6008 |
|
|
ADDRBU(7) => BU2_doutb(0),
|
6009 |
|
|
ADDRBU(6) => BU2_doutb(0),
|
6010 |
|
|
ADDRBU(5) => BU2_doutb(0),
|
6011 |
|
|
ADDRBU(4) => BU2_doutb(0),
|
6012 |
|
|
ADDRBU(3) => BU2_doutb(0),
|
6013 |
|
|
ADDRBU(2) => BU2_doutb(0),
|
6014 |
|
|
ADDRBU(1) => BU2_doutb(0),
|
6015 |
|
|
ADDRBU(0) => BU2_doutb(0),
|
6016 |
|
|
WEAU(3) => BU2_doutb(0),
|
6017 |
|
|
WEAU(2) => BU2_doutb(0),
|
6018 |
|
|
WEAU(1) => BU2_doutb(0),
|
6019 |
|
|
WEAU(0) => BU2_doutb(0),
|
6020 |
|
|
WEAL(3) => BU2_doutb(0),
|
6021 |
|
|
WEAL(2) => BU2_doutb(0),
|
6022 |
|
|
WEAL(1) => BU2_doutb(0),
|
6023 |
|
|
WEAL(0) => BU2_doutb(0),
|
6024 |
|
|
WEBU(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_7_UNCONNECTED,
|
6025 |
|
|
WEBU(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_6_UNCONNECTED,
|
6026 |
|
|
WEBU(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_5_UNCONNECTED,
|
6027 |
|
|
WEBU(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBU_4_UNCONNECTED,
|
6028 |
|
|
WEBU(3) => BU2_doutb(0),
|
6029 |
|
|
WEBU(2) => BU2_doutb(0),
|
6030 |
|
|
WEBU(1) => BU2_doutb(0),
|
6031 |
|
|
WEBU(0) => BU2_doutb(0),
|
6032 |
|
|
WEBL(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_7_UNCONNECTED,
|
6033 |
|
|
WEBL(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_6_UNCONNECTED,
|
6034 |
|
|
WEBL(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_5_UNCONNECTED,
|
6035 |
|
|
WEBL(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_WEBL_4_UNCONNECTED,
|
6036 |
|
|
WEBL(3) => BU2_doutb(0),
|
6037 |
|
|
WEBL(2) => BU2_doutb(0),
|
6038 |
|
|
WEBL(1) => BU2_doutb(0),
|
6039 |
|
|
WEBL(0) => BU2_doutb(0),
|
6040 |
|
|
DOA(31) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_31_UNCONNECTED,
|
6041 |
|
|
DOA(30) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_30_UNCONNECTED,
|
6042 |
|
|
DOA(29) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_29_UNCONNECTED,
|
6043 |
|
|
DOA(28) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_28_UNCONNECTED,
|
6044 |
|
|
DOA(27) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_27_UNCONNECTED,
|
6045 |
|
|
DOA(26) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_26_UNCONNECTED,
|
6046 |
|
|
DOA(25) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_25_UNCONNECTED,
|
6047 |
|
|
DOA(24) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_24_UNCONNECTED,
|
6048 |
|
|
DOA(23) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_23_UNCONNECTED,
|
6049 |
|
|
DOA(22) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_22_UNCONNECTED,
|
6050 |
|
|
DOA(21) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_21_UNCONNECTED,
|
6051 |
|
|
DOA(20) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_20_UNCONNECTED,
|
6052 |
|
|
DOA(19) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_19_UNCONNECTED,
|
6053 |
|
|
DOA(18) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_18_UNCONNECTED,
|
6054 |
|
|
DOA(17) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_17_UNCONNECTED,
|
6055 |
|
|
DOA(16) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_16_UNCONNECTED,
|
6056 |
|
|
DOA(15) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_15_UNCONNECTED,
|
6057 |
|
|
DOA(14) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_14_UNCONNECTED,
|
6058 |
|
|
DOA(13) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_13_UNCONNECTED,
|
6059 |
|
|
DOA(12) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_12_UNCONNECTED,
|
6060 |
|
|
DOA(11) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_11_UNCONNECTED,
|
6061 |
|
|
DOA(10) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_10_UNCONNECTED,
|
6062 |
|
|
DOA(9) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_9_UNCONNECTED,
|
6063 |
|
|
DOA(8) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOA_8_UNCONNECTED,
|
6064 |
|
|
DOA(7) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta10(7),
|
6065 |
|
|
DOA(6) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta10(6),
|
6066 |
|
|
DOA(5) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta10(5),
|
6067 |
|
|
DOA(4) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta10(4),
|
6068 |
|
|
DOA(3) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta10(3),
|
6069 |
|
|
DOA(2) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta10(2),
|
6070 |
|
|
DOA(1) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta10(1),
|
6071 |
|
|
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta10(0),
|
6072 |
|
|
DOPA(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_3_UNCONNECTED,
|
6073 |
|
|
DOPA(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_2_UNCONNECTED,
|
6074 |
|
|
DOPA(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPA_1_UNCONNECTED,
|
6075 |
|
|
DOPA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta10(8),
|
6076 |
|
|
DOB(31) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_31_UNCONNECTED,
|
6077 |
|
|
DOB(30) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_30_UNCONNECTED,
|
6078 |
|
|
DOB(29) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_29_UNCONNECTED,
|
6079 |
|
|
DOB(28) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_28_UNCONNECTED,
|
6080 |
|
|
DOB(27) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_27_UNCONNECTED,
|
6081 |
|
|
DOB(26) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_26_UNCONNECTED,
|
6082 |
|
|
DOB(25) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_25_UNCONNECTED,
|
6083 |
|
|
DOB(24) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_24_UNCONNECTED,
|
6084 |
|
|
DOB(23) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_23_UNCONNECTED,
|
6085 |
|
|
DOB(22) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_22_UNCONNECTED,
|
6086 |
|
|
DOB(21) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_21_UNCONNECTED,
|
6087 |
|
|
DOB(20) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_20_UNCONNECTED,
|
6088 |
|
|
DOB(19) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_19_UNCONNECTED,
|
6089 |
|
|
DOB(18) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_18_UNCONNECTED,
|
6090 |
|
|
DOB(17) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_17_UNCONNECTED,
|
6091 |
|
|
DOB(16) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_16_UNCONNECTED,
|
6092 |
|
|
DOB(15) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_15_UNCONNECTED,
|
6093 |
|
|
DOB(14) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_14_UNCONNECTED,
|
6094 |
|
|
DOB(13) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_13_UNCONNECTED,
|
6095 |
|
|
DOB(12) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_12_UNCONNECTED,
|
6096 |
|
|
DOB(11) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_11_UNCONNECTED,
|
6097 |
|
|
DOB(10) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_10_UNCONNECTED,
|
6098 |
|
|
DOB(9) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_9_UNCONNECTED,
|
6099 |
|
|
DOB(8) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_8_UNCONNECTED,
|
6100 |
|
|
DOB(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_7_UNCONNECTED,
|
6101 |
|
|
DOB(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_6_UNCONNECTED,
|
6102 |
|
|
DOB(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_5_UNCONNECTED,
|
6103 |
|
|
DOB(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_4_UNCONNECTED,
|
6104 |
|
|
DOB(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_3_UNCONNECTED,
|
6105 |
|
|
DOB(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_2_UNCONNECTED,
|
6106 |
|
|
DOB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_1_UNCONNECTED,
|
6107 |
|
|
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOB_0_UNCONNECTED,
|
6108 |
|
|
DOPB(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_3_UNCONNECTED,
|
6109 |
|
|
DOPB(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_2_UNCONNECTED,
|
6110 |
|
|
DOPB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_1_UNCONNECTED,
|
6111 |
|
|
DOPB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v5_init_ram_SP_SINGLE_PRIM36_SP_DOPB_0_UNCONNECTED
|
6112 |
|
|
);
|
6113 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_dout_mux_17_1 : LUT6
|
6114 |
|
|
generic map(
|
6115 |
|
|
INIT => X"DFD5DAD08F858A80"
|
6116 |
|
|
)
|
6117 |
|
|
port map (
|
6118 |
|
|
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
|
6119 |
|
|
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta6(8),
|
6120 |
|
|
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
|
6121 |
|
|
I3 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta5(8),
|
6122 |
|
|
I4 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta3(8),
|
6123 |
|
|
I5 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta4(8),
|
6124 |
|
|
O => douta_3(17)
|
6125 |
|
|
);
|
6126 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_dout_mux_26_1 : LUT6
|
6127 |
|
|
generic map(
|
6128 |
|
|
INIT => X"DFD5DAD08F858A80"
|
6129 |
|
|
)
|
6130 |
|
|
port map (
|
6131 |
|
|
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
|
6132 |
|
|
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta10(8),
|
6133 |
|
|
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
|
6134 |
|
|
I3 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta9(8),
|
6135 |
|
|
I4 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta7(8),
|
6136 |
|
|
I5 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta8(8),
|
6137 |
|
|
O => douta_3(26)
|
6138 |
|
|
);
|
6139 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_dout_mux_8_1 : LUT6
|
6140 |
|
|
generic map(
|
6141 |
|
|
INIT => X"DFD5DAD08F858A80"
|
6142 |
|
|
)
|
6143 |
|
|
port map (
|
6144 |
|
|
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
|
6145 |
|
|
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta2(8),
|
6146 |
|
|
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
|
6147 |
|
|
I3 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta0(8),
|
6148 |
|
|
I4 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta(8),
|
6149 |
|
|
I5 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta1(8),
|
6150 |
|
|
O => douta_3(8)
|
6151 |
|
|
);
|
6152 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_dout_mux_0_1 : LUT6
|
6153 |
|
|
generic map(
|
6154 |
|
|
INIT => X"DFD5DAD08F858A80"
|
6155 |
|
|
)
|
6156 |
|
|
port map (
|
6157 |
|
|
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
|
6158 |
|
|
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta2(0),
|
6159 |
|
|
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
|
6160 |
|
|
I3 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta1(0),
|
6161 |
|
|
I4 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta(0),
|
6162 |
|
|
I5 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta0(0),
|
6163 |
|
|
O => douta_3(0)
|
6164 |
|
|
);
|
6165 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_dout_mux_10_1 : LUT6
|
6166 |
|
|
generic map(
|
6167 |
|
|
INIT => X"DFD5DAD08F858A80"
|
6168 |
|
|
)
|
6169 |
|
|
port map (
|
6170 |
|
|
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
|
6171 |
|
|
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta6(1),
|
6172 |
|
|
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
|
6173 |
|
|
I3 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta5(1),
|
6174 |
|
|
I4 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta3(1),
|
6175 |
|
|
I5 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta4(1),
|
6176 |
|
|
O => douta_3(10)
|
6177 |
|
|
);
|
6178 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_dout_mux_11_1 : LUT6
|
6179 |
|
|
generic map(
|
6180 |
|
|
INIT => X"DFD5DAD08F858A80"
|
6181 |
|
|
)
|
6182 |
|
|
port map (
|
6183 |
|
|
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
|
6184 |
|
|
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta6(2),
|
6185 |
|
|
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
|
6186 |
|
|
I3 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta5(2),
|
6187 |
|
|
I4 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta3(2),
|
6188 |
|
|
I5 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta4(2),
|
6189 |
|
|
O => douta_3(11)
|
6190 |
|
|
);
|
6191 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_dout_mux_12_1 : LUT6
|
6192 |
|
|
generic map(
|
6193 |
|
|
INIT => X"DFD5DAD08F858A80"
|
6194 |
|
|
)
|
6195 |
|
|
port map (
|
6196 |
|
|
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
|
6197 |
|
|
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta6(3),
|
6198 |
|
|
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
|
6199 |
|
|
I3 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta5(3),
|
6200 |
|
|
I4 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta3(3),
|
6201 |
|
|
I5 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta4(3),
|
6202 |
|
|
O => douta_3(12)
|
6203 |
|
|
);
|
6204 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_dout_mux_13_1 : LUT6
|
6205 |
|
|
generic map(
|
6206 |
|
|
INIT => X"DFD5DAD08F858A80"
|
6207 |
|
|
)
|
6208 |
|
|
port map (
|
6209 |
|
|
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
|
6210 |
|
|
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta6(4),
|
6211 |
|
|
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
|
6212 |
|
|
I3 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta5(4),
|
6213 |
|
|
I4 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta3(4),
|
6214 |
|
|
I5 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta4(4),
|
6215 |
|
|
O => douta_3(13)
|
6216 |
|
|
);
|
6217 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_dout_mux_14_1 : LUT6
|
6218 |
|
|
generic map(
|
6219 |
|
|
INIT => X"DFD5DAD08F858A80"
|
6220 |
|
|
)
|
6221 |
|
|
port map (
|
6222 |
|
|
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
|
6223 |
|
|
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta6(5),
|
6224 |
|
|
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
|
6225 |
|
|
I3 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta5(5),
|
6226 |
|
|
I4 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta3(5),
|
6227 |
|
|
I5 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta4(5),
|
6228 |
|
|
O => douta_3(14)
|
6229 |
|
|
);
|
6230 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_dout_mux_15_1 : LUT6
|
6231 |
|
|
generic map(
|
6232 |
|
|
INIT => X"DFD5DAD08F858A80"
|
6233 |
|
|
)
|
6234 |
|
|
port map (
|
6235 |
|
|
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
|
6236 |
|
|
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta6(6),
|
6237 |
|
|
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
|
6238 |
|
|
I3 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta5(6),
|
6239 |
|
|
I4 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta3(6),
|
6240 |
|
|
I5 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta4(6),
|
6241 |
|
|
O => douta_3(15)
|
6242 |
|
|
);
|
6243 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_dout_mux_16_1 : LUT6
|
6244 |
|
|
generic map(
|
6245 |
|
|
INIT => X"DFD5DAD08F858A80"
|
6246 |
|
|
)
|
6247 |
|
|
port map (
|
6248 |
|
|
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
|
6249 |
|
|
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta6(7),
|
6250 |
|
|
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
|
6251 |
|
|
I3 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta5(7),
|
6252 |
|
|
I4 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta3(7),
|
6253 |
|
|
I5 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta4(7),
|
6254 |
|
|
O => douta_3(16)
|
6255 |
|
|
);
|
6256 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_dout_mux_18_1 : LUT6
|
6257 |
|
|
generic map(
|
6258 |
|
|
INIT => X"DFD5DAD08F858A80"
|
6259 |
|
|
)
|
6260 |
|
|
port map (
|
6261 |
|
|
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
|
6262 |
|
|
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta10(0),
|
6263 |
|
|
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
|
6264 |
|
|
I3 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta9(0),
|
6265 |
|
|
I4 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta7(0),
|
6266 |
|
|
I5 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta8(0),
|
6267 |
|
|
O => douta_3(18)
|
6268 |
|
|
);
|
6269 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_dout_mux_19_1 : LUT6
|
6270 |
|
|
generic map(
|
6271 |
|
|
INIT => X"DFD5DAD08F858A80"
|
6272 |
|
|
)
|
6273 |
|
|
port map (
|
6274 |
|
|
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
|
6275 |
|
|
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta10(1),
|
6276 |
|
|
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
|
6277 |
|
|
I3 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta9(1),
|
6278 |
|
|
I4 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta7(1),
|
6279 |
|
|
I5 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta8(1),
|
6280 |
|
|
O => douta_3(19)
|
6281 |
|
|
);
|
6282 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_dout_mux_1_1 : LUT6
|
6283 |
|
|
generic map(
|
6284 |
|
|
INIT => X"DFD5DAD08F858A80"
|
6285 |
|
|
)
|
6286 |
|
|
port map (
|
6287 |
|
|
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
|
6288 |
|
|
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta2(1),
|
6289 |
|
|
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
|
6290 |
|
|
I3 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta1(1),
|
6291 |
|
|
I4 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta(1),
|
6292 |
|
|
I5 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta0(1),
|
6293 |
|
|
O => douta_3(1)
|
6294 |
|
|
);
|
6295 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_dout_mux_20_1 : LUT6
|
6296 |
|
|
generic map(
|
6297 |
|
|
INIT => X"DFD5DAD08F858A80"
|
6298 |
|
|
)
|
6299 |
|
|
port map (
|
6300 |
|
|
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
|
6301 |
|
|
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta10(2),
|
6302 |
|
|
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
|
6303 |
|
|
I3 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta9(2),
|
6304 |
|
|
I4 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta7(2),
|
6305 |
|
|
I5 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta8(2),
|
6306 |
|
|
O => douta_3(20)
|
6307 |
|
|
);
|
6308 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_dout_mux_21_1 : LUT6
|
6309 |
|
|
generic map(
|
6310 |
|
|
INIT => X"DFD5DAD08F858A80"
|
6311 |
|
|
)
|
6312 |
|
|
port map (
|
6313 |
|
|
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
|
6314 |
|
|
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta10(3),
|
6315 |
|
|
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
|
6316 |
|
|
I3 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta9(3),
|
6317 |
|
|
I4 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta7(3),
|
6318 |
|
|
I5 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta8(3),
|
6319 |
|
|
O => douta_3(21)
|
6320 |
|
|
);
|
6321 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_dout_mux_22_1 : LUT6
|
6322 |
|
|
generic map(
|
6323 |
|
|
INIT => X"DFD5DAD08F858A80"
|
6324 |
|
|
)
|
6325 |
|
|
port map (
|
6326 |
|
|
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
|
6327 |
|
|
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta10(4),
|
6328 |
|
|
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
|
6329 |
|
|
I3 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta9(4),
|
6330 |
|
|
I4 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta7(4),
|
6331 |
|
|
I5 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta8(4),
|
6332 |
|
|
O => douta_3(22)
|
6333 |
|
|
);
|
6334 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_dout_mux_23_1 : LUT6
|
6335 |
|
|
generic map(
|
6336 |
|
|
INIT => X"DFD5DAD08F858A80"
|
6337 |
|
|
)
|
6338 |
|
|
port map (
|
6339 |
|
|
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
|
6340 |
|
|
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta10(5),
|
6341 |
|
|
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
|
6342 |
|
|
I3 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta9(5),
|
6343 |
|
|
I4 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta7(5),
|
6344 |
|
|
I5 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta8(5),
|
6345 |
|
|
O => douta_3(23)
|
6346 |
|
|
);
|
6347 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_dout_mux_24_1 : LUT6
|
6348 |
|
|
generic map(
|
6349 |
|
|
INIT => X"DFD5DAD08F858A80"
|
6350 |
|
|
)
|
6351 |
|
|
port map (
|
6352 |
|
|
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
|
6353 |
|
|
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta10(6),
|
6354 |
|
|
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
|
6355 |
|
|
I3 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta9(6),
|
6356 |
|
|
I4 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta7(6),
|
6357 |
|
|
I5 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta8(6),
|
6358 |
|
|
O => douta_3(24)
|
6359 |
|
|
);
|
6360 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_dout_mux_25_1 : LUT6
|
6361 |
|
|
generic map(
|
6362 |
|
|
INIT => X"DFD5DAD08F858A80"
|
6363 |
|
|
)
|
6364 |
|
|
port map (
|
6365 |
|
|
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
|
6366 |
|
|
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta10(7),
|
6367 |
|
|
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
|
6368 |
|
|
I3 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta9(7),
|
6369 |
|
|
I4 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta7(7),
|
6370 |
|
|
I5 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta8(7),
|
6371 |
|
|
O => douta_3(25)
|
6372 |
|
|
);
|
6373 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_dout_mux_2_1 : LUT6
|
6374 |
|
|
generic map(
|
6375 |
|
|
INIT => X"DFD5DAD08F858A80"
|
6376 |
|
|
)
|
6377 |
|
|
port map (
|
6378 |
|
|
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
|
6379 |
|
|
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta2(2),
|
6380 |
|
|
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
|
6381 |
|
|
I3 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta1(2),
|
6382 |
|
|
I4 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta(2),
|
6383 |
|
|
I5 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta0(2),
|
6384 |
|
|
O => douta_3(2)
|
6385 |
|
|
);
|
6386 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_dout_mux_3_1 : LUT6
|
6387 |
|
|
generic map(
|
6388 |
|
|
INIT => X"DFD5DAD08F858A80"
|
6389 |
|
|
)
|
6390 |
|
|
port map (
|
6391 |
|
|
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
|
6392 |
|
|
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta2(3),
|
6393 |
|
|
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
|
6394 |
|
|
I3 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta1(3),
|
6395 |
|
|
I4 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta(3),
|
6396 |
|
|
I5 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta0(3),
|
6397 |
|
|
O => douta_3(3)
|
6398 |
|
|
);
|
6399 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_dout_mux_4_1 : LUT6
|
6400 |
|
|
generic map(
|
6401 |
|
|
INIT => X"DFD5DAD08F858A80"
|
6402 |
|
|
)
|
6403 |
|
|
port map (
|
6404 |
|
|
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
|
6405 |
|
|
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta2(4),
|
6406 |
|
|
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
|
6407 |
|
|
I3 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta1(4),
|
6408 |
|
|
I4 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta(4),
|
6409 |
|
|
I5 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta0(4),
|
6410 |
|
|
O => douta_3(4)
|
6411 |
|
|
);
|
6412 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_dout_mux_5_1 : LUT6
|
6413 |
|
|
generic map(
|
6414 |
|
|
INIT => X"DFD5DAD08F858A80"
|
6415 |
|
|
)
|
6416 |
|
|
port map (
|
6417 |
|
|
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
|
6418 |
|
|
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta2(5),
|
6419 |
|
|
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
|
6420 |
|
|
I3 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta0(5),
|
6421 |
|
|
I4 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta(5),
|
6422 |
|
|
I5 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta1(5),
|
6423 |
|
|
O => douta_3(5)
|
6424 |
|
|
);
|
6425 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_dout_mux_6_1 : LUT6
|
6426 |
|
|
generic map(
|
6427 |
|
|
INIT => X"DFD5DAD08F858A80"
|
6428 |
|
|
)
|
6429 |
|
|
port map (
|
6430 |
|
|
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
|
6431 |
|
|
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta2(6),
|
6432 |
|
|
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
|
6433 |
|
|
I3 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta0(6),
|
6434 |
|
|
I4 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta(6),
|
6435 |
|
|
I5 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta1(6),
|
6436 |
|
|
O => douta_3(6)
|
6437 |
|
|
);
|
6438 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_dout_mux_7_1 : LUT6
|
6439 |
|
|
generic map(
|
6440 |
|
|
INIT => X"DFD5DAD08F858A80"
|
6441 |
|
|
)
|
6442 |
|
|
port map (
|
6443 |
|
|
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
|
6444 |
|
|
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta2(7),
|
6445 |
|
|
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
|
6446 |
|
|
I3 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta0(7),
|
6447 |
|
|
I4 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta(7),
|
6448 |
|
|
I5 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta1(7),
|
6449 |
|
|
O => douta_3(7)
|
6450 |
|
|
);
|
6451 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_dout_mux_9_1 : LUT6
|
6452 |
|
|
generic map(
|
6453 |
|
|
INIT => X"DFD5DAD08F858A80"
|
6454 |
|
|
)
|
6455 |
|
|
port map (
|
6456 |
|
|
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
|
6457 |
|
|
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta6(0),
|
6458 |
|
|
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
|
6459 |
|
|
I3 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta4(0),
|
6460 |
|
|
I4 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta3(0),
|
6461 |
|
|
I5 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta5(0),
|
6462 |
|
|
O => douta_3(9)
|
6463 |
|
|
);
|
6464 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_0_cmp_eq00001 : LUT2
|
6465 |
|
|
generic map(
|
6466 |
|
|
INIT => X"1"
|
6467 |
|
|
)
|
6468 |
|
|
port map (
|
6469 |
|
|
I0 => addra_2(12),
|
6470 |
|
|
I1 => addra_2(13),
|
6471 |
|
|
O => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_0_cmp_eq0000
|
6472 |
|
|
);
|
6473 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_1_cmp_eq00001 : LUT2
|
6474 |
|
|
generic map(
|
6475 |
|
|
INIT => X"4"
|
6476 |
|
|
)
|
6477 |
|
|
port map (
|
6478 |
|
|
I0 => addra_2(13),
|
6479 |
|
|
I1 => addra_2(12),
|
6480 |
|
|
O => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_1_cmp_eq0000
|
6481 |
|
|
);
|
6482 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_2_cmp_eq00001 : LUT2
|
6483 |
|
|
generic map(
|
6484 |
|
|
INIT => X"4"
|
6485 |
|
|
)
|
6486 |
|
|
port map (
|
6487 |
|
|
I0 => addra_2(12),
|
6488 |
|
|
I1 => addra_2(13),
|
6489 |
|
|
O => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_2_cmp_eq0000
|
6490 |
|
|
);
|
6491 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_3_cmp_eq00001 : LUT2
|
6492 |
|
|
generic map(
|
6493 |
|
|
INIT => X"8"
|
6494 |
|
|
)
|
6495 |
|
|
port map (
|
6496 |
|
|
I0 => addra_2(12),
|
6497 |
|
|
I1 => addra_2(13),
|
6498 |
|
|
O => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_3_cmp_eq0000
|
6499 |
|
|
);
|
6500 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_1 : FDE
|
6501 |
|
|
generic map(
|
6502 |
|
|
INIT => '0'
|
6503 |
|
|
)
|
6504 |
|
|
port map (
|
6505 |
|
|
C => clka,
|
6506 |
|
|
CE => BU2_N1,
|
6507 |
|
|
D => addra_2(13),
|
6508 |
|
|
Q => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1)
|
6509 |
|
|
);
|
6510 |
|
|
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_0 : FDE
|
6511 |
|
|
generic map(
|
6512 |
|
|
INIT => '0'
|
6513 |
|
|
)
|
6514 |
|
|
port map (
|
6515 |
|
|
C => clka,
|
6516 |
|
|
CE => BU2_N1,
|
6517 |
|
|
D => addra_2(12),
|
6518 |
|
|
Q => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0)
|
6519 |
|
|
);
|
6520 |
|
|
BU2_XST_VCC : VCC
|
6521 |
|
|
port map (
|
6522 |
|
|
P => BU2_N1
|
6523 |
|
|
);
|
6524 |
|
|
BU2_XST_GND : GND
|
6525 |
|
|
port map (
|
6526 |
|
|
G => BU2_doutb(0)
|
6527 |
|
|
);
|
6528 |
|
|
|
6529 |
|
|
end STRUCTURE;
|
6530 |
|
|
|
6531 |
|
|
-- synthesis translate_on
|