| 1 |
2 |
NikosAl |
##############################################################
|
| 2 |
|
|
#
|
| 3 |
|
|
# Xilinx Core Generator version K.39
|
| 4 |
|
|
# Date: Fri Jul 24 12:35:16 2009
|
| 5 |
|
|
#
|
| 6 |
|
|
##############################################################
|
| 7 |
|
|
#
|
| 8 |
|
|
# This file contains the customisation parameters for a
|
| 9 |
|
|
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
| 10 |
|
|
# that you do not manually alter this file as it may cause
|
| 11 |
|
|
# unexpected and unsupported behavior.
|
| 12 |
|
|
#
|
| 13 |
|
|
##############################################################
|
| 14 |
|
|
#
|
| 15 |
|
|
# BEGIN Project Options
|
| 16 |
|
|
SET addpads = False
|
| 17 |
|
|
SET asysymbol = False
|
| 18 |
|
|
SET busformat = BusFormatAngleBracketNotRipped
|
| 19 |
|
|
SET createndf = False
|
| 20 |
|
|
SET designentry = VHDL
|
| 21 |
|
|
SET device = xc5vsx95t
|
| 22 |
|
|
SET devicefamily = virtex5
|
| 23 |
|
|
SET flowvendor = Other
|
| 24 |
|
|
SET formalverification = False
|
| 25 |
|
|
SET foundationsym = False
|
| 26 |
|
|
SET implementationfiletype = Ngc
|
| 27 |
|
|
SET package = ff1136
|
| 28 |
|
|
SET removerpms = False
|
| 29 |
|
|
SET simulationfiles = Structural
|
| 30 |
|
|
SET speedgrade = -1
|
| 31 |
|
|
SET verilogsim = False
|
| 32 |
|
|
SET vhdlsim = True
|
| 33 |
|
|
# END Project Options
|
| 34 |
|
|
# BEGIN Select
|
| 35 |
|
|
SELECT Block_Memory_Generator family Xilinx,_Inc. 2.8
|
| 36 |
|
|
# END Select
|
| 37 |
|
|
# BEGIN Parameters
|
| 38 |
|
|
CSET algorithm=Minimum_Area
|
| 39 |
|
|
CSET assume_synchronous_clk=false
|
| 40 |
|
|
CSET byte_size=9
|
| 41 |
|
|
CSET coe_file="C:/Documents and Settings/Administrator/Desktop/Felsenstein Coprocessor/Logarithm LUT based/HW Implementation/Coregen/ICSILog Mantissa LUTs/ICSILog ManLut V2 2048 COE/mant_LUT.coe"
|
| 42 |
|
|
CSET collision_warnings=ALL
|
| 43 |
|
|
CSET component_name=mant_lut_MEM
|
| 44 |
|
|
CSET disable_collision_warnings=false
|
| 45 |
|
|
CSET disable_out_of_range_warnings=false
|
| 46 |
|
|
CSET ecc=false
|
| 47 |
|
|
CSET enable_a=Always_Enabled
|
| 48 |
|
|
CSET enable_b=Always_Enabled
|
| 49 |
|
|
CSET fill_remaining_memory_locations=false
|
| 50 |
|
|
CSET load_init_file=true
|
| 51 |
|
|
CSET memory_type=Single_Port_ROM
|
| 52 |
|
|
CSET operating_mode_a=WRITE_FIRST
|
| 53 |
|
|
CSET operating_mode_b=WRITE_FIRST
|
| 54 |
|
|
CSET output_reset_value_a=0
|
| 55 |
|
|
CSET output_reset_value_b=0
|
| 56 |
|
|
CSET pipeline_stages=0
|
| 57 |
|
|
CSET primitive=8kx2
|
| 58 |
|
|
CSET read_width_a=27
|
| 59 |
|
|
CSET read_width_b=27
|
| 60 |
|
|
CSET register_porta_output_of_memory_core=false
|
| 61 |
|
|
CSET register_porta_output_of_memory_primitives=false
|
| 62 |
|
|
CSET register_portb_output_of_memory_core=false
|
| 63 |
|
|
CSET register_portb_output_of_memory_primitives=false
|
| 64 |
|
|
CSET remaining_memory_locations=0
|
| 65 |
|
|
CSET single_bit_ecc=false
|
| 66 |
|
|
CSET use_byte_write_enable=false
|
| 67 |
|
|
CSET use_ramb16bwer_reset_behavior=false
|
| 68 |
|
|
CSET use_regcea_pin=false
|
| 69 |
|
|
CSET use_regceb_pin=false
|
| 70 |
|
|
CSET use_ssra_pin=false
|
| 71 |
|
|
CSET use_ssrb_pin=false
|
| 72 |
|
|
CSET write_depth_a=2048
|
| 73 |
|
|
CSET write_width_a=27
|
| 74 |
|
|
CSET write_width_b=27
|
| 75 |
|
|
# END Parameters
|
| 76 |
|
|
GENERATE
|
| 77 |
|
|
# CRC: 243c7e97
|
| 78 |
|
|
|
