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[/] [fp_log/] [trunk/] [LAU/] [Virtex 4/] [DP-LAU/] [dp_fp_log_v2.vhd] - Blame information for rev 2

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----------------------------------------------------------------------------------
-- Company: TUM - Technischen Universit�t M�nchen
-- Engineer: N.Alachiotis
-- 
-- Create Date:    11:03:31 06/24/2009 
-- Design Name:    DP-LAU (Double Precision Logarithm Approximation Unit)
-- Module Name:    dp_fp_log_v2 - Behavioral 
-- Project Name:   
-- Target Devices: Virtex 5 SX
-- Tool versions: Xilinx ISE 10.1
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity dp_fp_log_v2 is
    Port ( rst : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           valid_in : in  STD_LOGIC;
           input_val : in  STD_LOGIC_VECTOR (63 downto 0);
           valid_out : out  STD_LOGIC;
           output_val : out  STD_LOGIC_VECTOR (63 downto 0));
end dp_fp_log_v2;
 
architecture Behavioral of dp_fp_log_v2 is
 
component reg_64b_1c is
  port (
    sclr : in STD_LOGIC := 'X';
    clk : in STD_LOGIC := 'X';
    d : in STD_LOGIC_VECTOR ( 63 downto 0 );
    q : out STD_LOGIC_VECTOR ( 63 downto 0 )
  );
end component;
 
component reg_1b_1c is
  port (
    sclr : in STD_LOGIC := 'X';
    clk : in STD_LOGIC := 'X';
    d : in STD_LOGIC_VECTOR ( 0 downto 0 );
    q : out STD_LOGIC_VECTOR ( 0 downto 0 )
  );
end component;
 
signal valid_output_1bvec_in, valid_output_1bvec_out : std_logic_vector(0 downto 0);
signal tmp_valid_out : std_logic;
 
component reg_1b_2c is
  port (
    sclr : in STD_LOGIC := 'X';
    clk : in STD_LOGIC := 'X';
    d : in STD_LOGIC_VECTOR ( 0 downto 0 );
    q : out STD_LOGIC_VECTOR ( 0 downto 0 )
  );
end component;
 
component reg_32b_8c is
  port (
    sclr : in STD_LOGIC := 'X';
    clk : in STD_LOGIC := 'X';
    d : in STD_LOGIC_VECTOR ( 31 downto 0 );
    q : out STD_LOGIC_VECTOR ( 31 downto 0 )
  );
end component;
 
component reg_32b_1c is
  port (
    sclr : in STD_LOGIC := 'X';
    clk : in STD_LOGIC := 'X';
    d : in STD_LOGIC_VECTOR ( 31 downto 0 );
    q : out STD_LOGIC_VECTOR ( 31 downto 0 )
  );
end component;
 
signal input_val_valid_reg : std_logic_Vector (63 downto 0);
 
constant log_base_e_of_2 : std_logic_vector(31 downto 0):="00111111001100010111001000011000";
 
component special_case_detector is
    Port ( rst : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           input_val : in  STD_LOGIC_VECTOR (63 downto 0);
                          special_val_sel : out STD_LOGIC;
                          output_special_val : out STD_LOGIC_VECTOR(31 downto 0));
end component;
 
signal scd_out_special_val_sel , scd_out_special_val_sel_reg : std_logic;
signal scd_out_special_val_sel_1bvec , scd_out_special_val_sel_reg_1bvec : std_logic_vector(0 downto 0);
signal scd_out_output_special_val , scd_out_output_special_val_reg: std_logic_vector(31 downto 0);
 
signal scd_out_special_val_sel_reg_vec , scd_out_special_val_not_sel_reg_vec,
       temp_final_result ,
                 temp_final_result_reg: std_logic_vector(31 downto 0);
 
 
 
component Construct_sp_fp_mult_factor is
    Port ( rst : in  STD_LOGIC;
           clk : in  STD_LOGIC;
                          input_exponent : in  STD_LOGIC_VECTOR (10 downto 0);
           sp_fp_mult_fact : out  STD_LOGIC_VECTOR (31 downto 0));
end component;
 
signal csfmf_sp_fp_mult_fact : std_logic_vector(31 downto 0);
 
 
component sp_fp_mult is
  port (
    sclr : in STD_LOGIC := 'X';
    rdy : out STD_LOGIC;
    operation_nd : in STD_LOGIC := 'X';
    clk : in STD_LOGIC := 'X';
    a : in STD_LOGIC_VECTOR ( 31 downto 0 );
    b : in STD_LOGIC_VECTOR ( 31 downto 0 );
    result : out STD_LOGIC_VECTOR ( 31 downto 0 )
  );
end component;
 
signal mult_result : std_logic_vector(31 downto 0);
signal mult_valid_out : std_logic;
 
 
signal tmp_valid_in_vec_in1,tmp_valid_in_vec_out1,
                 tmp_valid_in_vec_in2,tmp_valid_in_vec_out2: std_logic_vector(0 downto 0);
 
component Construct_sp_fp_add_offset is
  Port ( rst : in  STD_LOGIC;
         clk : in  STD_LOGIC;
         lut_index : in  STD_LOGIC_VECTOR(12 downto 0);
         sp_fp_add_offset : out  STD_LOGIC_VECTOR (31 downto 0));
end component;
 
signal sp_fp_val_offset_reg_in , sp_fp_val_offset_reg_out: std_logic_vector(31 downto 0);
 
component sp_fp_add is
  port (
    sclr : in STD_LOGIC := 'X';
    rdy : out STD_LOGIC;
    operation_nd : in STD_LOGIC := 'X';
    clk : in STD_LOGIC := 'X';
    a : in STD_LOGIC_VECTOR ( 31 downto 0 );
    b : in STD_LOGIC_VECTOR ( 31 downto 0 );
    result : out STD_LOGIC_VECTOR ( 31 downto 0 )
  );
end component;
 
signal add_result : std_logic_vector(31 downto 0);
signal add_valid_out : std_logic;
 
signal no_special_case_result_32b : std_logic_Vector(31 downto 0);
 
component reg_1b_18c is
  port (
    sclr : in STD_LOGIC := 'X';
    clk : in STD_LOGIC := 'X';
    d : in STD_LOGIC_VECTOR ( 0 downto 0 );
    q : out STD_LOGIC_VECTOR ( 0 downto 0 )
  );
end component;
 
component reg_32b_18c is
  port (
    sclr : in STD_LOGIC := 'X';
    clk : in STD_LOGIC := 'X';
    d : in STD_LOGIC_VECTOR ( 31 downto 0 );
    q : out STD_LOGIC_VECTOR ( 31 downto 0 )
  );
end component;
 
component reg_33b_1c is
  port (
    sclr : in STD_LOGIC := 'X';
    clk : in STD_LOGIC := 'X';
    d : in STD_LOGIC_VECTOR ( 32 downto 0 );
    q : out STD_LOGIC_VECTOR ( 32 downto 0 )
  );
end component;
 
signal tmp_final_output_vec , tmp_final_output_vec_out : std_logic_vector(32 downto 0);
 
signal rst_reg_in , rst_reg_out : std_logic_vector(0 downto 0);
 
begin
 
rst_reg_in(0) <=rst;
Reset_Register : reg_1b_1c port map (rst, clk, rst_reg_in, rst_reg_out);
 
 
Valid_Input_Pipeline_Reg : reg_64b_1c port map (rst, clk, input_val, input_val_valid_reg);
 
tmp_valid_in_vec_in1(0)<=valid_in;
Valid_Input_Pipeline_Reg1 : reg_1b_1c port map (rst, clk, tmp_valid_in_vec_in1, tmp_valid_in_vec_out1);
 
-- Special Case Detector
special_case_detector_port_map: special_case_detector port map (
rst,
clk,
input_val_valid_reg,
scd_out_special_val_sel,
scd_out_output_special_val
);
 
-- Construct_sp_fp_mult_factor
Construct_sp_fp_mult_factor_port_map : Construct_sp_fp_mult_factor port map (
rst,
clk,
input_val_valid_reg(62 downto 52),
csfmf_sp_fp_mult_fact
);
 
-- Multiplier with constant port b : log10(2)
Valid_Input_Pipeline_Reg2 : reg_1b_2c port map (rst, clk, tmp_valid_in_vec_out1, tmp_valid_in_vec_out2);
 
sp_fp_mult_port_map : sp_fp_mult port map (
rst,
mult_valid_out,
tmp_valid_in_vec_out2(0),
clk,
csfmf_sp_fp_mult_fact,
log_base_e_of_2,
mult_result
);
 
 
-- Construct sp_fp_add_offset
Construct_sp_fp_add_offset_port_map: Construct_sp_fp_add_offset port map (
rst,
clk,
input_val_valid_reg(51 downto 39),
sp_fp_val_offset_reg_in
 
);
 
-- Pipeline Register for sp_fp_val_offset
val_offset_pipeline_reg : reg_32b_8c port map(rst,clk,sp_fp_val_offset_reg_in,sp_fp_val_offset_reg_out);
 
-- Final adder
sp_fp_add_port_map : sp_fp_add port map (
rst_reg_out(0),
tmp_valid_out,
mult_valid_out,
clk,
mult_result,
sp_fp_val_offset_reg_out,
no_special_case_result_32b
);
 
valid_output_1bvec_in(0) <= tmp_valid_out ;
reg_1b_1c_port_map_for_valid_out : reg_1b_1c port map (rst_reg_out(0), clk, valid_output_1bvec_in , valid_output_1bvec_out );
valid_out<=valid_output_1bvec_out(0);
 
-- Pipeline Register for special case value selection
scd_out_special_val_sel_1bvec(0)<=scd_out_special_val_sel;
reg_1b_21c_port_map : reg_1b_18c port map (rst_reg_out(0), clk, scd_out_special_val_sel_1bvec , scd_out_special_val_sel_reg_1bvec );
reg_32b_21c_port_map: reg_32b_18c port map (rst_reg_out(0),clk,scd_out_output_special_val,scd_out_output_special_val_reg);
 
 
scd_out_special_val_sel_reg_vec<=(others=>scd_out_special_val_sel_reg_1bvec(0));
scd_out_special_val_not_sel_reg_vec<=(others=>not scd_out_special_val_sel_reg_1bvec(0));
 
 
temp_final_result<= (scd_out_special_val_sel_reg_vec and scd_out_output_special_val_reg) or
                                                  (scd_out_special_val_not_sel_reg_vec and no_special_case_result_32b) ;
 
 
reg_32b_1c_port_map : reg_32b_1c port map (rst_reg_out(0), clk, temp_final_result , temp_final_result_reg );
 
 
-- Single to Double
output_val(63)<=temp_final_result_reg(31);
output_val(62)<=temp_final_result_reg(30);
output_val(61 downto 59)<=(others=>temp_final_result_reg(29));
output_val(58 downto 52)<=temp_final_result_reg(29 downto 23);
output_val(51 downto 29)<=temp_final_result_reg(22 downto 0);
output_val(28 downto 0)<=(others=>'0');
 
end Behavioral;
 

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Subversion Repositories fp_log

[/] [fp_log/] [trunk/] [LAU/] [Virtex 4/] [DP-LAU/] [dp_fp_log_v2.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	NikosAl	`----------------------------------------------------------------------------------`
2			`-- Company: TUM - Technischen Universit�t M�nchen`
3			`-- Engineer: N.Alachiotis`
4			`--`
5			`-- Create Date: 11:03:31 06/24/2009`
6			`-- Design Name: DP-LAU (Double Precision Logarithm Approximation Unit)`
7			`-- Module Name: dp_fp_log_v2 - Behavioral`
8			`-- Project Name:`
9			`-- Target Devices: Virtex 5 SX`
10			`-- Tool versions: Xilinx ISE 10.1`
11			`-- Description:`
12			`--`
13			`-- Dependencies:`
14			`--`
15			`-- Revision:`
16			`-- Revision 0.01 - File Created`
17			`-- Additional Comments:`
18			`--`
19			`----------------------------------------------------------------------------------`
20			`library IEEE;`
21			`use IEEE.STD_LOGIC_1164.ALL;`
22			`use IEEE.STD_LOGIC_ARITH.ALL;`
23			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
24
25			`---- Uncomment the following library declaration if instantiating`
26			`---- any Xilinx primitives in this code.`
27			`--library UNISIM;`
28			`--use UNISIM.VComponents.all;`
29
30			`entity dp_fp_log_v2 is`
31			`Port ( rst : in STD_LOGIC;`
32			`clk : in STD_LOGIC;`
33			`valid_in : in STD_LOGIC;`
34			`input_val : in STD_LOGIC_VECTOR (63 downto 0);`
35			`valid_out : out STD_LOGIC;`
36			`output_val : out STD_LOGIC_VECTOR (63 downto 0));`
37			`end dp_fp_log_v2;`
38
39			`architecture Behavioral of dp_fp_log_v2 is`
40
41			`component reg_64b_1c is`
42			`port (`
43			`sclr : in STD_LOGIC := 'X';`
44			`clk : in STD_LOGIC := 'X';`
45			`d : in STD_LOGIC_VECTOR ( 63 downto 0 );`
46			`q : out STD_LOGIC_VECTOR ( 63 downto 0 )`
47			`);`
48			`end component;`
49
50			`component reg_1b_1c is`
51			`port (`
52			`sclr : in STD_LOGIC := 'X';`
53			`clk : in STD_LOGIC := 'X';`
54			`d : in STD_LOGIC_VECTOR ( 0 downto 0 );`
55			`q : out STD_LOGIC_VECTOR ( 0 downto 0 )`
56			`);`
57			`end component;`
58
59			`signal valid_output_1bvec_in, valid_output_1bvec_out : std_logic_vector(0 downto 0);`
60			`signal tmp_valid_out : std_logic;`
61
62			`component reg_1b_2c is`
63			`port (`
64			`sclr : in STD_LOGIC := 'X';`
65			`clk : in STD_LOGIC := 'X';`
66			`d : in STD_LOGIC_VECTOR ( 0 downto 0 );`
67			`q : out STD_LOGIC_VECTOR ( 0 downto 0 )`
68			`);`
69			`end component;`
70
71			`component reg_32b_8c is`
72			`port (`
73			`sclr : in STD_LOGIC := 'X';`
74			`clk : in STD_LOGIC := 'X';`
75			`d : in STD_LOGIC_VECTOR ( 31 downto 0 );`
76			`q : out STD_LOGIC_VECTOR ( 31 downto 0 )`
77			`);`
78			`end component;`
79
80			`component reg_32b_1c is`
81			`port (`
82			`sclr : in STD_LOGIC := 'X';`
83			`clk : in STD_LOGIC := 'X';`
84			`d : in STD_LOGIC_VECTOR ( 31 downto 0 );`
85			`q : out STD_LOGIC_VECTOR ( 31 downto 0 )`
86			`);`
87			`end component;`
88
89			`signal input_val_valid_reg : std_logic_Vector (63 downto 0);`
90
91			`constant log_base_e_of_2 : std_logic_vector(31 downto 0):="00111111001100010111001000011000";`
92
93			`component special_case_detector is`
94			`Port ( rst : in STD_LOGIC;`
95			`clk : in STD_LOGIC;`
96			`input_val : in STD_LOGIC_VECTOR (63 downto 0);`
97			`special_val_sel : out STD_LOGIC;`
98			`output_special_val : out STD_LOGIC_VECTOR(31 downto 0));`
99			`end component;`
100
101			`signal scd_out_special_val_sel , scd_out_special_val_sel_reg : std_logic;`
102			`signal scd_out_special_val_sel_1bvec , scd_out_special_val_sel_reg_1bvec : std_logic_vector(0 downto 0);`
103			`signal scd_out_output_special_val , scd_out_output_special_val_reg: std_logic_vector(31 downto 0);`
104
105			`signal scd_out_special_val_sel_reg_vec , scd_out_special_val_not_sel_reg_vec,`
106			`temp_final_result ,`
107			`temp_final_result_reg: std_logic_vector(31 downto 0);`
108
109
110
111			`component Construct_sp_fp_mult_factor is`
112			`Port ( rst : in STD_LOGIC;`
113			`clk : in STD_LOGIC;`
114			`input_exponent : in STD_LOGIC_VECTOR (10 downto 0);`
115			`sp_fp_mult_fact : out STD_LOGIC_VECTOR (31 downto 0));`
116			`end component;`
117
118			`signal csfmf_sp_fp_mult_fact : std_logic_vector(31 downto 0);`
119
120
121			`component sp_fp_mult is`
122			`port (`
123			`sclr : in STD_LOGIC := 'X';`
124			`rdy : out STD_LOGIC;`
125			`operation_nd : in STD_LOGIC := 'X';`
126			`clk : in STD_LOGIC := 'X';`
127			`a : in STD_LOGIC_VECTOR ( 31 downto 0 );`
128			`b : in STD_LOGIC_VECTOR ( 31 downto 0 );`
129			`result : out STD_LOGIC_VECTOR ( 31 downto 0 )`
130			`);`
131			`end component;`
132
133			`signal mult_result : std_logic_vector(31 downto 0);`
134			`signal mult_valid_out : std_logic;`
135
136
137			`signal tmp_valid_in_vec_in1,tmp_valid_in_vec_out1,`
138			`tmp_valid_in_vec_in2,tmp_valid_in_vec_out2: std_logic_vector(0 downto 0);`
139
140			`component Construct_sp_fp_add_offset is`
141			`Port ( rst : in STD_LOGIC;`
142			`clk : in STD_LOGIC;`
143			`lut_index : in STD_LOGIC_VECTOR(12 downto 0);`
144			`sp_fp_add_offset : out STD_LOGIC_VECTOR (31 downto 0));`
145			`end component;`
146
147			`signal sp_fp_val_offset_reg_in , sp_fp_val_offset_reg_out: std_logic_vector(31 downto 0);`
148
149			`component sp_fp_add is`
150			`port (`
151			`sclr : in STD_LOGIC := 'X';`
152			`rdy : out STD_LOGIC;`
153			`operation_nd : in STD_LOGIC := 'X';`
154			`clk : in STD_LOGIC := 'X';`
155			`a : in STD_LOGIC_VECTOR ( 31 downto 0 );`
156			`b : in STD_LOGIC_VECTOR ( 31 downto 0 );`
157			`result : out STD_LOGIC_VECTOR ( 31 downto 0 )`
158			`);`
159			`end component;`
160
161			`signal add_result : std_logic_vector(31 downto 0);`
162			`signal add_valid_out : std_logic;`
163
164			`signal no_special_case_result_32b : std_logic_Vector(31 downto 0);`
165
166			`component reg_1b_18c is`
167			`port (`
168			`sclr : in STD_LOGIC := 'X';`
169			`clk : in STD_LOGIC := 'X';`
170			`d : in STD_LOGIC_VECTOR ( 0 downto 0 );`
171			`q : out STD_LOGIC_VECTOR ( 0 downto 0 )`
172			`);`
173			`end component;`
174
175			`component reg_32b_18c is`
176			`port (`
177			`sclr : in STD_LOGIC := 'X';`
178			`clk : in STD_LOGIC := 'X';`
179			`d : in STD_LOGIC_VECTOR ( 31 downto 0 );`
180			`q : out STD_LOGIC_VECTOR ( 31 downto 0 )`
181			`);`
182			`end component;`
183
184			`component reg_33b_1c is`
185			`port (`
186			`sclr : in STD_LOGIC := 'X';`
187			`clk : in STD_LOGIC := 'X';`
188			`d : in STD_LOGIC_VECTOR ( 32 downto 0 );`
189			`q : out STD_LOGIC_VECTOR ( 32 downto 0 )`
190			`);`
191			`end component;`
192
193			`signal tmp_final_output_vec , tmp_final_output_vec_out : std_logic_vector(32 downto 0);`
194
195			`signal rst_reg_in , rst_reg_out : std_logic_vector(0 downto 0);`
196
197			`begin`
198
199			`rst_reg_in(0) <=rst;`
200			`Reset_Register : reg_1b_1c port map (rst, clk, rst_reg_in, rst_reg_out);`
201
202
203			`Valid_Input_Pipeline_Reg : reg_64b_1c port map (rst, clk, input_val, input_val_valid_reg);`
204
205			`tmp_valid_in_vec_in1(0)<=valid_in;`
206			`Valid_Input_Pipeline_Reg1 : reg_1b_1c port map (rst, clk, tmp_valid_in_vec_in1, tmp_valid_in_vec_out1);`
207
208			`-- Special Case Detector`
209			`special_case_detector_port_map: special_case_detector port map (`
210			`rst,`
211			`clk,`
212			`input_val_valid_reg,`
213			`scd_out_special_val_sel,`
214			`scd_out_output_special_val`
215			`);`
216
217			`-- Construct_sp_fp_mult_factor`
218			`Construct_sp_fp_mult_factor_port_map : Construct_sp_fp_mult_factor port map (`
219			`rst,`
220			`clk,`
221			`input_val_valid_reg(62 downto 52),`
222			`csfmf_sp_fp_mult_fact`
223			`);`
224
225			`-- Multiplier with constant port b : log10(2)`
226			`Valid_Input_Pipeline_Reg2 : reg_1b_2c port map (rst, clk, tmp_valid_in_vec_out1, tmp_valid_in_vec_out2);`
227
228			`sp_fp_mult_port_map : sp_fp_mult port map (`
229			`rst,`
230			`mult_valid_out,`
231			`tmp_valid_in_vec_out2(0),`
232			`clk,`
233			`csfmf_sp_fp_mult_fact,`
234			`log_base_e_of_2,`
235			`mult_result`
236			`);`
237
238
239			`-- Construct sp_fp_add_offset`
240			`Construct_sp_fp_add_offset_port_map: Construct_sp_fp_add_offset port map (`
241			`rst,`
242			`clk,`
243			`input_val_valid_reg(51 downto 39),`
244			`sp_fp_val_offset_reg_in`
245
246			`);`
247
248			`-- Pipeline Register for sp_fp_val_offset`
249			`val_offset_pipeline_reg : reg_32b_8c port map(rst,clk,sp_fp_val_offset_reg_in,sp_fp_val_offset_reg_out);`
250
251			`-- Final adder`
252			`sp_fp_add_port_map : sp_fp_add port map (`
253			`rst_reg_out(0),`
254			`tmp_valid_out,`
255			`mult_valid_out,`
256			`clk,`
257			`mult_result,`
258			`sp_fp_val_offset_reg_out,`
259			`no_special_case_result_32b`
260			`);`
261
262			`valid_output_1bvec_in(0) <= tmp_valid_out ;`
263			`reg_1b_1c_port_map_for_valid_out : reg_1b_1c port map (rst_reg_out(0), clk, valid_output_1bvec_in , valid_output_1bvec_out );`
264			`valid_out<=valid_output_1bvec_out(0);`
265
266			`-- Pipeline Register for special case value selection`
267			`scd_out_special_val_sel_1bvec(0)<=scd_out_special_val_sel;`
268			`reg_1b_21c_port_map : reg_1b_18c port map (rst_reg_out(0), clk, scd_out_special_val_sel_1bvec , scd_out_special_val_sel_reg_1bvec );`
269			`reg_32b_21c_port_map: reg_32b_18c port map (rst_reg_out(0),clk,scd_out_output_special_val,scd_out_output_special_val_reg);`
270
271
272			`scd_out_special_val_sel_reg_vec<=(others=>scd_out_special_val_sel_reg_1bvec(0));`
273			`scd_out_special_val_not_sel_reg_vec<=(others=>not scd_out_special_val_sel_reg_1bvec(0));`
274
275
276			`temp_final_result<= (scd_out_special_val_sel_reg_vec and scd_out_output_special_val_reg) or`
277			`(scd_out_special_val_not_sel_reg_vec and no_special_case_result_32b) ;`
278
279
280			`reg_32b_1c_port_map : reg_32b_1c port map (rst_reg_out(0), clk, temp_final_result , temp_final_result_reg );`
281
282
283			`-- Single to Double`
284			`output_val(63)<=temp_final_result_reg(31);`
285			`output_val(62)<=temp_final_result_reg(30);`
286			`output_val(61 downto 59)<=(others=>temp_final_result_reg(29));`
287			`output_val(58 downto 52)<=temp_final_result_reg(29 downto 23);`
288			`output_val(51 downto 29)<=temp_final_result_reg(22 downto 0);`
289			`output_val(28 downto 0)<=(others=>'0');`
290
291			`end Behavioral;`
292