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NikosAl |
##############################################################
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#
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# Xilinx Core Generator version K.39
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# Date: Fri Sep 18 12:12:25 2009
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#
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##############################################################
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#
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# that you do not manually alter this file as it may cause
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# unexpected and unsupported behavior.
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#
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##############################################################
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#
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# BEGIN Project Options
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SET addpads = False
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SET asysymbol = False
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = False
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SET designentry = VHDL
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SET device = xc4vsx55
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SET devicefamily = virtex4
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SET flowvendor = Other
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SET formalverification = False
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SET foundationsym = False
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SET implementationfiletype = Ngc
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SET package = ff1148
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SET removerpms = False
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SET simulationfiles = Structural
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SET speedgrade = -12
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SET verilogsim = False
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SET vhdlsim = True
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# END Project Options
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# BEGIN Select
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SELECT Block_Memory_Generator family Xilinx,_Inc. 2.8
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# END Select
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# BEGIN Parameters
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CSET algorithm=Minimum_Area
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CSET assume_synchronous_clk=false
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CSET byte_size=9
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CSET coe_file="C:/Documents and Settings/Administrator/Desktop/Felsenstein Coprocessor/Logarithm LUT based/HW Implementation/Coregen2/ICSILog Mantissa LUTs/ICSILog v1 mantissa LUT 4096/ICSILog_v1_4096/mant_lut.coe"
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CSET collision_warnings=ALL
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CSET component_name=mant_lut_MEM
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CSET disable_collision_warnings=false
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CSET disable_out_of_range_warnings=false
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CSET ecc=false
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CSET enable_a=Always_Enabled
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CSET enable_b=Always_Enabled
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CSET fill_remaining_memory_locations=false
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CSET load_init_file=true
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CSET memory_type=Single_Port_ROM
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CSET operating_mode_a=WRITE_FIRST
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CSET operating_mode_b=WRITE_FIRST
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CSET output_reset_value_a=0
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CSET output_reset_value_b=0
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CSET pipeline_stages=0
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CSET primitive=8kx2
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CSET read_width_a=27
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CSET read_width_b=27
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CSET register_porta_output_of_memory_core=false
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CSET register_porta_output_of_memory_primitives=false
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CSET register_portb_output_of_memory_core=false
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CSET register_portb_output_of_memory_primitives=false
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CSET remaining_memory_locations=0
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CSET single_bit_ecc=false
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CSET use_byte_write_enable=false
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CSET use_ramb16bwer_reset_behavior=false
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CSET use_regcea_pin=false
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CSET use_regceb_pin=false
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CSET use_ssra_pin=false
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CSET use_ssrb_pin=false
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CSET write_depth_a=4096
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CSET write_width_a=27
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CSET write_width_b=27
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# END Parameters
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GENERATE
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# CRC: b05d6b35
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