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[/] [fp_log/] [trunk/] [LAU/] [Virtex 4/] [SP-LAU/] [exp_lut_MEM.vhd] - Blame information for rev 2

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Line No. Rev Author Line
1 2 NikosAl 
--------------------------------------------------------------------------------
2 
-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
3 
--------------------------------------------------------------------------------
4 
--   ____  ____
5 
--  /   /\/   /
6 
-- /___/  \  /    Vendor: Xilinx
7 
-- \   \   \/     Version: K.39
8 
--  \   \         Application: netgen
9 
--  /   /         Filename: exp_lut_MEM.vhd
10 
-- /___/   /\     Timestamp: Fri Sep 18 13:18:00 2009
11 
-- \   \  /  \
12 
--  \___\/\___\
13 
--
14 
-- Command      : -intstyle ise -w -sim -ofmt vhdl "C:\Documents and Settings\Administrator\Desktop\Felsenstein Coprocessor\Logarithm LUT based\HW Implementation\Coregen\tmp\_cg\exp_lut_MEM.ngc" "C:\Documents and Settings\Administrator\Desktop\Felsenstein Coprocessor\Logarithm LUT based\HW Implementation\Coregen\tmp\_cg\exp_lut_MEM.vhd"
15 
-- Device       : 4vsx55ff1148-12
16 
-- Input file   : C:/Documents and Settings/Administrator/Desktop/Felsenstein Coprocessor/Logarithm LUT based/HW Implementation/Coregen/tmp/_cg/exp_lut_MEM.ngc
17 
-- Output file  : C:/Documents and Settings/Administrator/Desktop/Felsenstein Coprocessor/Logarithm LUT based/HW Implementation/Coregen/tmp/_cg/exp_lut_MEM.vhd
18 
-- # of Entities        : 1
19 
-- Design Name  : exp_lut_MEM
20 
-- Xilinx       : C:\Xilinx\10.1\ISE
21 
--
22 
-- Purpose:
23 
--     This VHDL netlist is a verification model and uses simulation
24 
--     primitives which may not represent the true implementation of the
25 
--     device, however the netlist is functionally correct and should not
26 
--     be modified. This file cannot be synthesized and should only be used
27 
--     with supported simulation tools.
28 
--
29 
-- Reference:
30 
--     Development System Reference Guide, Chapter 23
31 
--     Synthesis and Simulation Design Guide, Chapter 6
32 
--
33 
--------------------------------------------------------------------------------
34 
 
35 
 
36 
-- synthesis translate_off
37 
library IEEE;
38 
use IEEE.STD_LOGIC_1164.ALL;
39 
library UNISIM;
40 
use UNISIM.VCOMPONENTS.ALL;
41 
use UNISIM.VPKG.ALL;
42 
 
43 
entity exp_lut_MEM is
44 
  port (
45 
    clka : in STD_LOGIC := 'X';
46 
    addra : in STD_LOGIC_VECTOR ( 6 downto 0 );
47 
    douta : out STD_LOGIC_VECTOR ( 8 downto 0 )
48 
  );
49 
end exp_lut_MEM;
50 
 
51 
architecture STRUCTURE of exp_lut_MEM is
52 
  signal BU2_N1 : STD_LOGIC;
53 
  signal NLW_VCC_P_UNCONNECTED : STD_LOGIC;
54 
  signal NLW_GND_G_UNCONNECTED : STD_LOGIC;
55 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
56 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
57 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_31_UNCONNECTED : STD_LOGIC;
58 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_30_UNCONNECTED : STD_LOGIC;
59 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_29_UNCONNECTED : STD_LOGIC;
60 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_28_UNCONNECTED : STD_LOGIC;
61 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_27_UNCONNECTED : STD_LOGIC;
62 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_26_UNCONNECTED : STD_LOGIC;
63 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_25_UNCONNECTED : STD_LOGIC;
64 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_23_UNCONNECTED : STD_LOGIC;
65 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_22_UNCONNECTED : STD_LOGIC;
66 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_21_UNCONNECTED : STD_LOGIC;
67 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_20_UNCONNECTED : STD_LOGIC;
68 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_19_UNCONNECTED : STD_LOGIC;
69 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_18_UNCONNECTED : STD_LOGIC;
70 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_17_UNCONNECTED : STD_LOGIC;
71 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_15_UNCONNECTED : STD_LOGIC;
72 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_14_UNCONNECTED : STD_LOGIC;
73 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_13_UNCONNECTED : STD_LOGIC;
74 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_12_UNCONNECTED : STD_LOGIC;
75 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_11_UNCONNECTED : STD_LOGIC;
76 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_10_UNCONNECTED : STD_LOGIC;
77 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_9_UNCONNECTED : STD_LOGIC;
78 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_7_UNCONNECTED : STD_LOGIC;
79 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_6_UNCONNECTED : STD_LOGIC;
80 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_5_UNCONNECTED : STD_LOGIC;
81 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_4_UNCONNECTED : STD_LOGIC;
82 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_3_UNCONNECTED : STD_LOGIC;
83 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_2_UNCONNECTED : STD_LOGIC;
84 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_31_UNCONNECTED : STD_LOGIC;
85 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_30_UNCONNECTED : STD_LOGIC;
86 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_29_UNCONNECTED : STD_LOGIC;
87 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_28_UNCONNECTED : STD_LOGIC;
88 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_27_UNCONNECTED : STD_LOGIC;
89 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_26_UNCONNECTED : STD_LOGIC;
90 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_25_UNCONNECTED : STD_LOGIC;
91 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_23_UNCONNECTED : STD_LOGIC;
92 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_22_UNCONNECTED : STD_LOGIC;
93 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_21_UNCONNECTED : STD_LOGIC;
94 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_20_UNCONNECTED : STD_LOGIC;
95 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_19_UNCONNECTED : STD_LOGIC;
96 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_18_UNCONNECTED : STD_LOGIC;
97 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_17_UNCONNECTED : STD_LOGIC;
98 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_15_UNCONNECTED : STD_LOGIC;
99 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_14_UNCONNECTED : STD_LOGIC;
100 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_13_UNCONNECTED : STD_LOGIC;
101 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_12_UNCONNECTED : STD_LOGIC;
102 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_11_UNCONNECTED : STD_LOGIC;
103 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_10_UNCONNECTED : STD_LOGIC;
104 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_9_UNCONNECTED : STD_LOGIC;
105 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_7_UNCONNECTED : STD_LOGIC;
106 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_6_UNCONNECTED : STD_LOGIC;
107 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_5_UNCONNECTED : STD_LOGIC;
108 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_4_UNCONNECTED : STD_LOGIC;
109 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_3_UNCONNECTED : STD_LOGIC;
110 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_2_UNCONNECTED : STD_LOGIC;
111 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_1_UNCONNECTED : STD_LOGIC;
112 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOPA_3_UNCONNECTED : STD_LOGIC;
113 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOPA_2_UNCONNECTED : STD_LOGIC;
114 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOPA_1_UNCONNECTED : STD_LOGIC;
115 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOPA_0_UNCONNECTED : STD_LOGIC;
116 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOPB_3_UNCONNECTED : STD_LOGIC;
117 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOPB_2_UNCONNECTED : STD_LOGIC;
118 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOPB_1_UNCONNECTED : STD_LOGIC;
119 
  signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOPB_0_UNCONNECTED : STD_LOGIC;
120 
  signal addra_2 : STD_LOGIC_VECTOR ( 6 downto 0 );
121 
  signal douta_3 : STD_LOGIC_VECTOR ( 8 downto 0 );
122 
  signal BU2_doutb : STD_LOGIC_VECTOR ( 0 downto 0 );
123 
begin
124 
  addra_2(6) <= addra(6);
125 
  addra_2(5) <= addra(5);
126 
  addra_2(4) <= addra(4);
127 
  addra_2(3) <= addra(3);
128 
  addra_2(2) <= addra(2);
129 
  addra_2(1) <= addra(1);
130 
  addra_2(0) <= addra(0);
131 
  douta(8) <= douta_3(8);
132 
  douta(7) <= douta_3(7);
133 
  douta(6) <= douta_3(6);
134 
  douta(5) <= douta_3(5);
135 
  douta(4) <= douta_3(4);
136 
  douta(3) <= douta_3(3);
137 
  douta(2) <= douta_3(2);
138 
  douta(1) <= douta_3(1);
139 
  douta(0) <= douta_3(0);
140 
  VCC_0 : VCC
141 
    port map (
142 
      P => NLW_VCC_P_UNCONNECTED
143 
    );
144 
  GND_1 : GND
145 
    port map (
146 
      G => NLW_GND_G_UNCONNECTED
147 
    );
148 
  BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP : RAMB16
149 
    generic map(
150 
      DOA_REG => 0,
151 
      DOB_REG => 0,
152 
      INIT_A => X"000000000",
153 
      INIT_B => X"000000000",
154 
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
155 
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
156 
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
157 
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
158 
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
159 
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
160 
      SRVAL_A => X"000000000",
161 
      INIT_00 => X"0100010101010100010001010101010101000101010101020100010101010103",
162 
      INIT_01 => X"0100010101010000010001010101000101000101010100020100010101010003",
163 
      INIT_02 => X"0100010101000100010001010100010101000101010001020100010101000103",
164 
      INIT_03 => X"0100010101000000010001010100000101000101010000020100010101000003",
165 
      INIT_04 => X"0100010100010100010001010001010101000101000101020100010100010103",
166 
      INIT_05 => X"0100010100010000010001010001000101000101000100020100010100010003",
167 
      INIT_06 => X"0100010100000100010001010000010101000101000001020100010100000103",
168 
      INIT_07 => X"0100010100000000010001010000000101000101000000020100010100000003",
169 
      INIT_08 => X"0100010001010100010001000101010101000100010101020100010001010103",
170 
      INIT_09 => X"0100010001010000010001000101000101000100010100020100010001010003",
171 
      INIT_0A => X"0100010001000100010001000100010101000100010001020100010001000103",
172 
      INIT_0B => X"0100010001000000010001000100000101000100010000020100010001000003",
173 
      INIT_0C => X"0100010000010100010001000001010101000100000101020100010000010103",
174 
      INIT_0D => X"0100010000010000010001000001000101000100000100020100010000010003",
175 
      INIT_0E => X"0100010000000100010001000000010101000100000001020100010000000103",
176 
      INIT_0F => X"0100010000000000010001000000000101000100000000020100010000000003",
177 
      INIT_10 => X"0100000101010000010000010101000201000001010101000100000101010102",
178 
      INIT_11 => X"0100000101000000010000010100000201000001010001000100000101000102",
179 
      INIT_12 => X"0100000100010000010000010001000201000001000101000100000100010102",
180 
      INIT_13 => X"0100000100000000010000010000000201000001000001000100000100000102",
181 
      INIT_14 => X"0100000001010000010000000101000201000000010101000100000001010102",
182 
      INIT_15 => X"0100000001000000010000000100000201000000010001000100000001000102",
183 
      INIT_16 => X"0100000000010000010000000001000201000000000101000100000000010102",
184 
      INIT_17 => X"0100000000000000010000000000000201000000000001000100000000000102",
185 
      INIT_18 => X"0001010101000000000101010100010000010101010100000001010101010100",
186 
      INIT_19 => X"0001010100000000000101010000010000010101000100000001010100010100",
187 
      INIT_1A => X"0001010001000000000101000100010000010100010100000001010001010100",
188 
      INIT_1B => X"0001010000000000000101000000010000010100000100000001010000010100",
189 
      INIT_1C => X"0001000100000000000100010001000000010001010000000001000101010000",
190 
      INIT_1D => X"0001000000000000000100000001000000010000010000000001000001010000",
191 
      INIT_1E => X"0000010000000000000001000100000000000101000000000000010101000000",
192 
      INIT_1F => X"0000000000000000010101000000000000000000000000000000000100000000",
193 
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
194 
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
195 
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
196 
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
197 
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
198 
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
199 
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
200 
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
201 
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
202 
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
203 
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
204 
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
205 
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
206 
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
207 
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
208 
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
209 
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
210 
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
211 
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
212 
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
213 
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
214 
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
215 
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
216 
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
217 
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
218 
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
219 
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
220 
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
221 
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
222 
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
223 
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
224 
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
225 
      INIT_FILE => "NONE",
226 
      INVERT_CLK_DOA_REG => FALSE,
227 
      INVERT_CLK_DOB_REG => FALSE,
228 
      RAM_EXTENSION_A => "NONE",
229 
      RAM_EXTENSION_B => "NONE",
230 
      READ_WIDTH_A => 36,
231 
      READ_WIDTH_B => 36,
232 
      SIM_COLLISION_CHECK => "ALL",
233 
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
234 
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
235 
      WRITE_MODE_A => "WRITE_FIRST",
236 
      WRITE_MODE_B => "WRITE_FIRST",
237 
      WRITE_WIDTH_A => 36,
238 
      WRITE_WIDTH_B => 36,
239 
      SRVAL_B => X"000000000"
240 
    )
241 
    port map (
242 
      CASCADEINA => BU2_doutb(0),
243 
      CASCADEINB => BU2_doutb(0),
244 
      CLKA => clka,
245 
      CLKB => clka,
246 
      ENA => BU2_N1,
247 
      REGCEA => BU2_doutb(0),
248 
      REGCEB => BU2_doutb(0),
249 
      ENB => BU2_N1,
250 
      SSRA => BU2_doutb(0),
251 
      SSRB => BU2_doutb(0),
252 
      CASCADEOUTA => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_CASCADEOUTA_UNCONNECTED,
253 
      CASCADEOUTB => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_CASCADEOUTB_UNCONNECTED,
254 
      ADDRA(14) => BU2_doutb(0),
255 
      ADDRA(13) => BU2_doutb(0),
256 
      ADDRA(12) => addra_2(6),
257 
      ADDRA(11) => addra_2(5),
258 
      ADDRA(10) => addra_2(4),
259 
      ADDRA(9) => addra_2(3),
260 
      ADDRA(8) => addra_2(2),
261 
      ADDRA(7) => addra_2(1),
262 
      ADDRA(6) => addra_2(0),
263 
      ADDRA(5) => BU2_doutb(0),
264 
      ADDRA(4) => BU2_doutb(0),
265 
      ADDRA(3) => BU2_doutb(0),
266 
      ADDRA(2) => BU2_doutb(0),
267 
      ADDRA(1) => BU2_doutb(0),
268 
      ADDRA(0) => BU2_doutb(0),
269 
      ADDRB(14) => BU2_doutb(0),
270 
      ADDRB(13) => BU2_doutb(0),
271 
      ADDRB(12) => addra_2(6),
272 
      ADDRB(11) => addra_2(5),
273 
      ADDRB(10) => addra_2(4),
274 
      ADDRB(9) => addra_2(3),
275 
      ADDRB(8) => addra_2(2),
276 
      ADDRB(7) => addra_2(1),
277 
      ADDRB(6) => addra_2(0),
278 
      ADDRB(5) => BU2_N1,
279 
      ADDRB(4) => BU2_doutb(0),
280 
      ADDRB(3) => BU2_doutb(0),
281 
      ADDRB(2) => BU2_doutb(0),
282 
      ADDRB(1) => BU2_doutb(0),
283 
      ADDRB(0) => BU2_doutb(0),
284 
      DIA(31) => BU2_doutb(0),
285 
      DIA(30) => BU2_doutb(0),
286 
      DIA(29) => BU2_doutb(0),
287 
      DIA(28) => BU2_doutb(0),
288 
      DIA(27) => BU2_doutb(0),
289 
      DIA(26) => BU2_doutb(0),
290 
      DIA(25) => BU2_doutb(0),
291 
      DIA(24) => BU2_doutb(0),
292 
      DIA(23) => BU2_doutb(0),
293 
      DIA(22) => BU2_doutb(0),
294 
      DIA(21) => BU2_doutb(0),
295 
      DIA(20) => BU2_doutb(0),
296 
      DIA(19) => BU2_doutb(0),
297 
      DIA(18) => BU2_doutb(0),
298 
      DIA(17) => BU2_doutb(0),
299 
      DIA(16) => BU2_doutb(0),
300 
      DIA(15) => BU2_doutb(0),
301 
      DIA(14) => BU2_doutb(0),
302 
      DIA(13) => BU2_doutb(0),
303 
      DIA(12) => BU2_doutb(0),
304 
      DIA(11) => BU2_doutb(0),
305 
      DIA(10) => BU2_doutb(0),
306 
      DIA(9) => BU2_doutb(0),
307 
      DIA(8) => BU2_doutb(0),
308 
      DIA(7) => BU2_doutb(0),
309 
      DIA(6) => BU2_doutb(0),
310 
      DIA(5) => BU2_doutb(0),
311 
      DIA(4) => BU2_doutb(0),
312 
      DIA(3) => BU2_doutb(0),
313 
      DIA(2) => BU2_doutb(0),
314 
      DIA(1) => BU2_doutb(0),
315 
      DIA(0) => BU2_doutb(0),
316 
      DIB(31) => BU2_doutb(0),
317 
      DIB(30) => BU2_doutb(0),
318 
      DIB(29) => BU2_doutb(0),
319 
      DIB(28) => BU2_doutb(0),
320 
      DIB(27) => BU2_doutb(0),
321 
      DIB(26) => BU2_doutb(0),
322 
      DIB(25) => BU2_doutb(0),
323 
      DIB(24) => BU2_doutb(0),
324 
      DIB(23) => BU2_doutb(0),
325 
      DIB(22) => BU2_doutb(0),
326 
      DIB(21) => BU2_doutb(0),
327 
      DIB(20) => BU2_doutb(0),
328 
      DIB(19) => BU2_doutb(0),
329 
      DIB(18) => BU2_doutb(0),
330 
      DIB(17) => BU2_doutb(0),
331 
      DIB(16) => BU2_doutb(0),
332 
      DIB(15) => BU2_doutb(0),
333 
      DIB(14) => BU2_doutb(0),
334 
      DIB(13) => BU2_doutb(0),
335 
      DIB(12) => BU2_doutb(0),
336 
      DIB(11) => BU2_doutb(0),
337 
      DIB(10) => BU2_doutb(0),
338 
      DIB(9) => BU2_doutb(0),
339 
      DIB(8) => BU2_doutb(0),
340 
      DIB(7) => BU2_doutb(0),
341 
      DIB(6) => BU2_doutb(0),
342 
      DIB(5) => BU2_doutb(0),
343 
      DIB(4) => BU2_doutb(0),
344 
      DIB(3) => BU2_doutb(0),
345 
      DIB(2) => BU2_doutb(0),
346 
      DIB(1) => BU2_doutb(0),
347 
      DIB(0) => BU2_doutb(0),
348 
      DIPA(3) => BU2_doutb(0),
349 
      DIPA(2) => BU2_doutb(0),
350 
      DIPA(1) => BU2_doutb(0),
351 
      DIPA(0) => BU2_doutb(0),
352 
      DIPB(3) => BU2_doutb(0),
353 
      DIPB(2) => BU2_doutb(0),
354 
      DIPB(1) => BU2_doutb(0),
355 
      DIPB(0) => BU2_doutb(0),
356 
      WEA(3) => BU2_doutb(0),
357 
      WEA(2) => BU2_doutb(0),
358 
      WEA(1) => BU2_doutb(0),
359 
      WEA(0) => BU2_doutb(0),
360 
      WEB(3) => BU2_doutb(0),
361 
      WEB(2) => BU2_doutb(0),
362 
      WEB(1) => BU2_doutb(0),
363 
      WEB(0) => BU2_doutb(0),
364 
      DOA(31) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_31_UNCONNECTED,
365 
      DOA(30) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_30_UNCONNECTED,
366 
      DOA(29) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_29_UNCONNECTED,
367 
      DOA(28) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_28_UNCONNECTED,
368 
      DOA(27) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_27_UNCONNECTED,
369 
      DOA(26) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_26_UNCONNECTED,
370 
      DOA(25) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_25_UNCONNECTED,
371 
      DOA(24) => douta_3(4),
372 
      DOA(23) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_23_UNCONNECTED,
373 
      DOA(22) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_22_UNCONNECTED,
374 
      DOA(21) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_21_UNCONNECTED,
375 
      DOA(20) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_20_UNCONNECTED,
376 
      DOA(19) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_19_UNCONNECTED,
377 
      DOA(18) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_18_UNCONNECTED,
378 
      DOA(17) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_17_UNCONNECTED,
379 
      DOA(16) => douta_3(3),
380 
      DOA(15) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_15_UNCONNECTED,
381 
      DOA(14) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_14_UNCONNECTED,
382 
      DOA(13) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_13_UNCONNECTED,
383 
      DOA(12) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_12_UNCONNECTED,
384 
      DOA(11) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_11_UNCONNECTED,
385 
      DOA(10) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_10_UNCONNECTED,
386 
      DOA(9) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_9_UNCONNECTED,
387 
      DOA(8) => douta_3(2),
388 
      DOA(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_7_UNCONNECTED,
389 
      DOA(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_6_UNCONNECTED,
390 
      DOA(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_5_UNCONNECTED,
391 
      DOA(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_4_UNCONNECTED,
392 
      DOA(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_3_UNCONNECTED,
393 
      DOA(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOA_2_UNCONNECTED,
394 
      DOA(1) => douta_3(1),
395 
      DOA(0) => douta_3(0),
396 
      DOB(31) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_31_UNCONNECTED,
397 
      DOB(30) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_30_UNCONNECTED,
398 
      DOB(29) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_29_UNCONNECTED,
399 
      DOB(28) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_28_UNCONNECTED,
400 
      DOB(27) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_27_UNCONNECTED,
401 
      DOB(26) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_26_UNCONNECTED,
402 
      DOB(25) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_25_UNCONNECTED,
403 
      DOB(24) => douta_3(8),
404 
      DOB(23) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_23_UNCONNECTED,
405 
      DOB(22) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_22_UNCONNECTED,
406 
      DOB(21) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_21_UNCONNECTED,
407 
      DOB(20) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_20_UNCONNECTED,
408 
      DOB(19) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_19_UNCONNECTED,
409 
      DOB(18) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_18_UNCONNECTED,
410 
      DOB(17) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_17_UNCONNECTED,
411 
      DOB(16) => douta_3(7),
412 
      DOB(15) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_15_UNCONNECTED,
413 
      DOB(14) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_14_UNCONNECTED,
414 
      DOB(13) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_13_UNCONNECTED,
415 
      DOB(12) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_12_UNCONNECTED,
416 
      DOB(11) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_11_UNCONNECTED,
417 
      DOB(10) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_10_UNCONNECTED,
418 
      DOB(9) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_9_UNCONNECTED,
419 
      DOB(8) => douta_3(6),
420 
      DOB(7) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_7_UNCONNECTED,
421 
      DOB(6) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_6_UNCONNECTED,
422 
      DOB(5) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_5_UNCONNECTED,
423 
      DOB(4) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_4_UNCONNECTED,
424 
      DOB(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_3_UNCONNECTED,
425 
      DOB(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_2_UNCONNECTED,
426 
      DOB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOB_1_UNCONNECTED,
427 
      DOB(0) => douta_3(5),
428 
      DOPA(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOPA_3_UNCONNECTED,
429 
      DOPA(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOPA_2_UNCONNECTED,
430 
      DOPA(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOPA_1_UNCONNECTED,
431 
      DOPA(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOPA_0_UNCONNECTED,
432 
      DOPB(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOPB_3_UNCONNECTED,
433 
      DOPB(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOPB_2_UNCONNECTED,
434 
      DOPB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOPB_1_UNCONNECTED,
435 
      DOPB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v4_init_ram_SP_WIDE_PRIM_SP_DOPB_0_UNCONNECTED
436 
    );
437 
  BU2_XST_VCC : VCC
438 
    port map (
439 
      P => BU2_N1
440 
    );
441 
  BU2_XST_GND : GND
442 
    port map (
443 
      G => BU2_doutb(0)
444 
    );
445 
 
446 
end STRUCTURE;
447 
 
448 
-- synthesis translate_on

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