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[/] [fp_log/] [trunk/] [LAU/] [Virtex 5/] [DP-LAU/] [comp_eq_111111111.vhd] - Blame information for rev 2

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1 2 NikosAl
--------------------------------------------------------------------------------
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-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
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--------------------------------------------------------------------------------
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--   ____  ____
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--  /   /\/   /
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-- /___/  \  /    Vendor: Xilinx
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-- \   \   \/     Version: K.39
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--  \   \         Application: netgen
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--  /   /         Filename: comp_eq_111111111.vhd
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-- /___/   /\     Timestamp: Mon Jun 22 15:25:08 2009
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-- \   \  /  \ 
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--  \___\/\___\
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--             
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-- Command      : -intstyle ise -w -sim -ofmt vhdl "C:\Documents and Settings\Administrator\Desktop\Felsenstein Coprocessor\Logarithm LUT based\HW Implementation\Coregen\tmp\_cg\comp_eq_111111111.ngc" "C:\Documents and Settings\Administrator\Desktop\Felsenstein Coprocessor\Logarithm LUT based\HW Implementation\Coregen\tmp\_cg\comp_eq_111111111.vhd" 
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-- Device       : 5vsx95tff1136-2
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-- Input file   : C:/Documents and Settings/Administrator/Desktop/Felsenstein Coprocessor/Logarithm LUT based/HW Implementation/Coregen/tmp/_cg/comp_eq_111111111.ngc
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-- Output file  : C:/Documents and Settings/Administrator/Desktop/Felsenstein Coprocessor/Logarithm LUT based/HW Implementation/Coregen/tmp/_cg/comp_eq_111111111.vhd
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-- # of Entities        : 1
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-- Design Name  : comp_eq_111111111
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-- Xilinx       : C:\Xilinx\10.1\ISE
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--             
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-- Purpose:    
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--     This VHDL netlist is a verification model and uses simulation 
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--     primitives which may not represent the true implementation of the 
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--     device, however the netlist is functionally correct and should not 
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--     be modified. This file cannot be synthesized and should only be used 
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--     with supported simulation tools.
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--             
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-- Reference:  
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--     Development System Reference Guide, Chapter 23
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--     Synthesis and Simulation Design Guide, Chapter 6
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--             
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--------------------------------------------------------------------------------
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-- synthesis translate_off
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library UNISIM;
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use UNISIM.VCOMPONENTS.ALL;
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use UNISIM.VPKG.ALL;
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entity comp_eq_111111111 is
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  port (
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    sclr : in STD_LOGIC := 'X';
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    qa_eq_b : out STD_LOGIC;
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    clk : in STD_LOGIC := 'X';
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    a : in STD_LOGIC_VECTOR ( 8 downto 0 )
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  );
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end comp_eq_111111111;
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architecture STRUCTURE of comp_eq_111111111 is
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  signal BU2_N01 : STD_LOGIC;
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  signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result : STD_LOGIC;
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  signal BU2_a_ge_b : STD_LOGIC;
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  signal NLW_VCC_P_UNCONNECTED : STD_LOGIC;
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  signal NLW_GND_G_UNCONNECTED : STD_LOGIC;
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  signal a_2 : STD_LOGIC_VECTOR ( 8 downto 0 );
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begin
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  a_2(8) <= a(8);
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  a_2(7) <= a(7);
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  a_2(6) <= a(6);
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  a_2(5) <= a(5);
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  a_2(4) <= a(4);
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  a_2(3) <= a(3);
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  a_2(2) <= a(2);
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  a_2(1) <= a(1);
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  a_2(0) <= a(0);
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  VCC_0 : VCC
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    port map (
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      P => NLW_VCC_P_UNCONNECTED
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    );
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  GND_1 : GND
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    port map (
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      G => NLW_GND_G_UNCONNECTED
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    );
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  BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o :
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LUT6
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    generic map(
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      INIT => X"8000000000000000"
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    )
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    port map (
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      I0 => a_2(8),
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      I1 => a_2(7),
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      I2 => a_2(6),
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      I3 => a_2(5),
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      I4 => a_2(4),
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      I5 => BU2_N01,
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      O => BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result
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    );
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  BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o_SW0 :
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LUT4
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    generic map(
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      INIT => X"8000"
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    )
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    port map (
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      I0 => a_2(3),
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      I1 => a_2(2),
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      I2 => a_2(1),
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      I3 => a_2(0),
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      O => BU2_N01
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    );
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  BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_gen_output_reg_output_reg_fd_output_1 : FDR
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    generic map(
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      INIT => '0'
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    )
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    port map (
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      C => clk,
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      D => BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result,
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      R => sclr,
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      Q => qa_eq_b
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    );
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  BU2_XST_GND : GND
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    port map (
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      G => BU2_a_ge_b
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    );
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end STRUCTURE;
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-- synthesis translate_on

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