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--------------------------------------------------------------------------------

-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.

--------------------------------------------------------------------------------

--   ____  ____

--  /   /\/   /

-- /___/  \  /    Vendor: Xilinx

-- \   \   \/     Version: K.39

--  \   \         Application: netgen

--  /   /         Filename: comp_eq_51zeros.vhd

-- /___/   /\     Timestamp: Tue Jun 23 15:22:22 2009

-- \   \  /  \ 

--  \___\/\___\

--             

-- Command      : -intstyle ise -w -sim -ofmt vhdl "C:\Documents and Settings\Administrator\Desktop\Felsenstein Coprocessor\Logarithm LUT based\HW Implementation\Coregen\tmp\_cg\comp_eq_51zeros.ngc" "C:\Documents and Settings\Administrator\Desktop\Felsenstein Coprocessor\Logarithm LUT based\HW Implementation\Coregen\tmp\_cg\comp_eq_51zeros.vhd" 

-- Device       : 5vsx95tff1136-2

-- Input file   : C:/Documents and Settings/Administrator/Desktop/Felsenstein Coprocessor/Logarithm LUT based/HW Implementation/Coregen/tmp/_cg/comp_eq_51zeros.ngc

-- Output file  : C:/Documents and Settings/Administrator/Desktop/Felsenstein Coprocessor/Logarithm LUT based/HW Implementation/Coregen/tmp/_cg/comp_eq_51zeros.vhd

-- # of Entities        : 1

-- Design Name  : comp_eq_51zeros

-- Xilinx       : C:\Xilinx\10.1\ISE

--             

-- Purpose:    

--     This VHDL netlist is a verification model and uses simulation 

--     primitives which may not represent the true implementation of the 

--     device, however the netlist is functionally correct and should not 

--     be modified. This file cannot be synthesized and should only be used 

--     with supported simulation tools.

--             

-- Reference:  

--     Development System Reference Guide, Chapter 23

--     Synthesis and Simulation Design Guide, Chapter 6

--             

--------------------------------------------------------------------------------

-- synthesis translate_off

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;

use UNISIM.VCOMPONENTS.ALL;

use UNISIM.VPKG.ALL;

entity comp_eq_51zeros is

  port (

    sclr : in STD_LOGIC := 'X';

    qa_eq_b : out STD_LOGIC;

    clk : in STD_LOGIC := 'X';

    a : in STD_LOGIC_VECTOR ( 50 downto 0 )

  );

end comp_eq_51zeros;

architecture STRUCTURE of comp_eq_51zeros is

  signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and0000276_67 : STD_LOGIC;

  signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and0000240_66 : STD_LOGIC;

  signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and0000164_65 : STD_LOGIC;

  signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and0000128_64 : STD_LOGIC;

  signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000071_63 : STD_LOGIC;

  signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000035_62 : STD_LOGIC;

  signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_1_and000095_61 : STD_LOGIC;

  signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_1_and000024_60 : STD_LOGIC;

  signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result : STD_LOGIC;

  signal BU2_N1 : STD_LOGIC;

  signal BU2_a_ge_b : STD_LOGIC;

  signal NLW_VCC_P_UNCONNECTED : STD_LOGIC;

  signal NLW_GND_G_UNCONNECTED : STD_LOGIC;

  signal a_2 : STD_LOGIC_VECTOR ( 50 downto 0 );

  signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o : STD_LOGIC_VECTOR ( 1 downto 0 );

  signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_async_o : STD_LOGIC_VECTOR ( 1 downto 1 );

begin

  a_2(50) <= a(50);

  a_2(49) <= a(49);

  a_2(48) <= a(48);

  a_2(47) <= a(47);

  a_2(46) <= a(46);

  a_2(45) <= a(45);

  a_2(44) <= a(44);

  a_2(43) <= a(43);

  a_2(42) <= a(42);

  a_2(41) <= a(41);

  a_2(40) <= a(40);

  a_2(39) <= a(39);

  a_2(38) <= a(38);

  a_2(37) <= a(37);

  a_2(36) <= a(36);

  a_2(35) <= a(35);

  a_2(34) <= a(34);

  a_2(33) <= a(33);

  a_2(32) <= a(32);

  a_2(31) <= a(31);

  a_2(30) <= a(30);

  a_2(29) <= a(29);

  a_2(28) <= a(28);

  a_2(27) <= a(27);

  a_2(26) <= a(26);

  a_2(25) <= a(25);

  a_2(24) <= a(24);

  a_2(23) <= a(23);

  a_2(22) <= a(22);

  a_2(21) <= a(21);

  a_2(20) <= a(20);

  a_2(19) <= a(19);

  a_2(18) <= a(18);

  a_2(17) <= a(17);

  a_2(16) <= a(16);

  a_2(15) <= a(15);

  a_2(14) <= a(14);

  a_2(13) <= a(13);

  a_2(12) <= a(12);

  a_2(11) <= a(11);

  a_2(10) <= a(10);

  a_2(9) <= a(9);

  a_2(8) <= a(8);

  a_2(7) <= a(7);

  a_2(6) <= a(6);

  a_2(5) <= a(5);

  a_2(4) <= a(4);

  a_2(3) <= a(3);

  a_2(2) <= a(2);

  a_2(1) <= a(1);

  a_2(0) <= a(0);

  VCC_0 : VCC

    port map (

      P => NLW_VCC_P_UNCONNECTED

    );

  GND_1 : GND

    port map (

      G => NLW_GND_G_UNCONNECTED

    );

  BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_1_and000099 :

LUT6

    generic map(

      INIT => X"0000000000000008"

    )

    port map (

      I0 =>

BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_1_and000024_60

,

      I1 =>

BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_1_and000095_61

,

      I2 => a_2(37),

      I3 => a_2(38),

      I4 => a_2(36),

      I5 => a_2(39),

      O =>

BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o(1)

    );

  BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and0000302 :

LUT6

    generic map(

      INIT => X"8000000000000000"

    )

    port map (

      I0 =>

BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000035_62

,

      I1 =>

BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000071_63

,

      I2 =>

BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and0000128_64

,

      I3 =>

BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and0000164_65

,

      I4 =>

BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and0000240_66

,

      I5 =>

BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and0000276_67

,

      O =>

BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o(0)

    );

  BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and0000276 :

LUT6

    generic map(

      INIT => X"0000000000000001"

    )

    port map (

      I0 => a_2(22),

      I1 => a_2(23),

      I2 => a_2(21),

      I3 => a_2(20),

      I4 => a_2(19),

      I5 => a_2(18),

      O =>

BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and0000276_67

    );

  BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and0000240 :

LUT6

    generic map(

      INIT => X"0000000000000001"

    )

    port map (

      I0 => a_2(16),

      I1 => a_2(17),

      I2 => a_2(15),

      I3 => a_2(14),

      I4 => a_2(13),

      I5 => a_2(12),

      O =>

BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and0000240_66

    );

  BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and0000164 :

LUT6

    generic map(

      INIT => X"0000000000000001"

    )

    port map (

      I0 => a_2(10),

      I1 => a_2(11),

      I2 => a_2(9),

      I3 => a_2(8),

      I4 => a_2(7),

      I5 => a_2(6),

      O =>

BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and0000164_65

    );

  BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and0000128 :

LUT6

    generic map(

      INIT => X"0000000000000001"

    )

    port map (

      I0 => a_2(4),

      I1 => a_2(5),

      I2 => a_2(3),

      I3 => a_2(2),

      I4 => a_2(1),

      I5 => a_2(0),

      O =>

BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and0000128_64

    );

  BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000071 :

LUT6

    generic map(

      INIT => X"0000000000000001"

    )

    port map (

      I0 => a_2(34),

      I1 => a_2(35),

      I2 => a_2(33),

      I3 => a_2(32),

      I4 => a_2(31),

      I5 => a_2(30),

      O =>

BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000071_63

    );

  BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000035 :

LUT6

    generic map(

      INIT => X"0000000000000001"

    )

    port map (

      I0 => a_2(28),

      I1 => a_2(29),

      I2 => a_2(27),

      I3 => a_2(26),

      I4 => a_2(25),

      I5 => a_2(24),

      O =>

BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000035_62

    );

  BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_1_and000095 :

LUT6

    generic map(

      INIT => X"0000000000000001"

    )

    port map (

      I0 => a_2(49),

      I1 => a_2(50),

      I2 => a_2(48),

      I3 => a_2(47),

      I4 => a_2(46),

      I5 => a_2(45),

      O =>

BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_1_and000095_61

    );

  BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_1_and000024 :

LUT5

    generic map(

      INIT => X"00000001"

    )

    port map (

      I0 => a_2(43),

      I1 => a_2(44),

      I2 => a_2(42),

      I3 => a_2(41),

      I4 => a_2(40),

      O =>

BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_1_and000024_60

    );

  BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_opt_carry_tile_and_or_carry_muxs_0_i_mux :

MUXCY

    port map (

      CI =>

BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_async_o(1)

,

      DI => BU2_a_ge_b,

      S =>

BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o(0)

,

      O => BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result

    );

  BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_opt_carry_tile_and_or_carry_muxs_1_i_mux :

MUXCY

    port map (

      CI => BU2_N1,

      DI => BU2_a_ge_b,

      S =>

BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o(1)

,

      O =>

BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_async_o(1)

    );

  BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_gen_output_reg_output_reg_fd_output_1 : FDR

    generic map(

      INIT => '0'

    )

    port map (

      C => clk,

      D => BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result,

      R => sclr,

      Q => qa_eq_b

    );

  BU2_XST_VCC : VCC

    port map (

      P => BU2_N1

    );

  BU2_XST_GND : GND

    port map (

      G => BU2_a_ge_b

    );

end STRUCTURE;

-- synthesis translate_on