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[/] [fp_log/] [trunk/] [LAU/] [Virtex 5/] [DP-LAU/] [comp_eq_51zeros.xco] - Blame information for rev 2

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Line No. Rev Author Line
1 2 NikosAl
##############################################################
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#
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# Xilinx Core Generator version K.39
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# Date: Tue Jun 23 13:22:22 2009
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#
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##############################################################
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#
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#  This file contains the customisation parameters for a
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#  Xilinx CORE Generator IP GUI. It is strongly recommended
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#  that you do not manually alter this file as it may cause
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#  unexpected and unsupported behavior.
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#
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##############################################################
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#
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# BEGIN Project Options
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SET addpads = False
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SET asysymbol = False
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = False
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SET designentry = VHDL
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SET device = xc5vsx95t
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SET devicefamily = virtex5
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SET flowvendor = Other
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SET formalverification = False
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SET foundationsym = False
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SET implementationfiletype = Ngc
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SET package = ff1136
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SET removerpms = False
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SET simulationfiles = Structural
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SET speedgrade = -2
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SET verilogsim = False
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SET vhdlsim = True
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# END Project Options
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# BEGIN Select
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SELECT Comparator family Xilinx,_Inc. 9.0
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# END Select
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# BEGIN Parameters
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CSET aclr=false
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CSET ainitval=0
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CSET aset=false
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CSET ce=false
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CSET cepriority=Sync_Overrides_CE
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CSET component_name=comp_eq_51zeros
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CSET constantbport=true
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CSET constantbportvalue=000000000000000000000000000000000000000000000000000
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CSET datatype=Unsigned
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CSET nonregisteredoutput=false
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CSET operation=eq
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CSET pipelinestages=0
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CSET radix=2
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CSET registeredoutput=true
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CSET sclr=true
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CSET sset=false
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CSET syncctrlpriority=Reset_Overrides_Set
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CSET width=51
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# END Parameters
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GENERATE
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# CRC: b2f01aa4
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