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#

# Xilinx Core Generator version K.39

# Date: Tue Jun 23 13:22:22 2009

#

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#

#  This file contains the customisation parameters for a

#  Xilinx CORE Generator IP GUI. It is strongly recommended

#  that you do not manually alter this file as it may cause

#  unexpected and unsupported behavior.

#

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#

# BEGIN Project Options

SET addpads = False

SET asysymbol = False

SET busformat = BusFormatAngleBracketNotRipped

SET createndf = False

SET designentry = VHDL

SET device = xc5vsx95t

SET devicefamily = virtex5

SET flowvendor = Other

SET formalverification = False

SET foundationsym = False

SET implementationfiletype = Ngc

SET package = ff1136

SET removerpms = False

SET simulationfiles = Structural

SET speedgrade = -2

SET verilogsim = False

SET vhdlsim = True

# END Project Options

# BEGIN Select

SELECT Comparator family Xilinx,_Inc. 9.0

# END Select

# BEGIN Parameters

CSET aclr=false

CSET ainitval=0

CSET aset=false

CSET ce=false

CSET cepriority=Sync_Overrides_CE

CSET component_name=comp_eq_51zeros

CSET constantbport=true

CSET constantbportvalue=000000000000000000000000000000000000000000000000000

CSET datatype=Unsigned

CSET nonregisteredoutput=false

CSET operation=eq

CSET pipelinestages=0

CSET radix=2

CSET registeredoutput=true

CSET sclr=true

CSET sset=false

CSET syncctrlpriority=Reset_Overrides_Set

CSET width=51

# END Parameters

GENERATE

# CRC: b2f01aa4