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[/] [fp_log/] [trunk/] [LAU/] [Virtex 5/] [DP-LAU/] [reg_1b_2c.vhd] - Blame information for rev 2

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1 2 NikosAl
--------------------------------------------------------------------------------
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-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
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--------------------------------------------------------------------------------
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--   ____  ____
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--  /   /\/   /
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-- /___/  \  /    Vendor: Xilinx
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-- \   \   \/     Version: K.39
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--  \   \         Application: netgen
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--  /   /         Filename: reg_1b_2c.vhd
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-- /___/   /\     Timestamp: Wed Jun 24 13:07:26 2009
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-- \   \  /  \ 
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--  \___\/\___\
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--             
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-- Command      : -intstyle ise -w -sim -ofmt vhdl "C:\Documents and Settings\Administrator\Desktop\Felsenstein Coprocessor\Logarithm LUT based\HW Implementation\Coregen\tmp\_cg\reg_1b_2c.ngc" "C:\Documents and Settings\Administrator\Desktop\Felsenstein Coprocessor\Logarithm LUT based\HW Implementation\Coregen\tmp\_cg\reg_1b_2c.vhd" 
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-- Device       : 5vsx95tff1136-2
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-- Input file   : C:/Documents and Settings/Administrator/Desktop/Felsenstein Coprocessor/Logarithm LUT based/HW Implementation/Coregen/tmp/_cg/reg_1b_2c.ngc
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-- Output file  : C:/Documents and Settings/Administrator/Desktop/Felsenstein Coprocessor/Logarithm LUT based/HW Implementation/Coregen/tmp/_cg/reg_1b_2c.vhd
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-- # of Entities        : 1
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-- Design Name  : reg_1b_2c
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-- Xilinx       : C:\Xilinx\10.1\ISE
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--             
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-- Purpose:    
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--     This VHDL netlist is a verification model and uses simulation 
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--     primitives which may not represent the true implementation of the 
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--     device, however the netlist is functionally correct and should not 
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--     be modified. This file cannot be synthesized and should only be used 
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--     with supported simulation tools.
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--             
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-- Reference:  
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--     Development System Reference Guide, Chapter 23
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--     Synthesis and Simulation Design Guide, Chapter 6
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--             
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--------------------------------------------------------------------------------
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-- synthesis translate_off
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library UNISIM;
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use UNISIM.VCOMPONENTS.ALL;
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use UNISIM.VPKG.ALL;
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entity reg_1b_2c is
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  port (
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    sclr : in STD_LOGIC := 'X';
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    clk : in STD_LOGIC := 'X';
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    d : in STD_LOGIC_VECTOR ( 0 downto 0 );
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    q : out STD_LOGIC_VECTOR ( 0 downto 0 )
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  );
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end reg_1b_2c;
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architecture STRUCTURE of reg_1b_2c is
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  signal BU2_sset : STD_LOGIC;
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  signal BU2_sinit : STD_LOGIC;
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  signal BU2_ainit : STD_LOGIC;
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  signal BU2_aclr : STD_LOGIC;
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  signal BU2_ce : STD_LOGIC;
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  signal BU2_aset : STD_LOGIC;
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  signal BU2_U0_srl_sig_0_4 : STD_LOGIC;
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  signal NLW_VCC_P_UNCONNECTED : STD_LOGIC;
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  signal NLW_GND_G_UNCONNECTED : STD_LOGIC;
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  signal d_2 : STD_LOGIC_VECTOR ( 0 downto 0 );
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  signal q_3 : STD_LOGIC_VECTOR ( 0 downto 0 );
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  signal BU2_a : STD_LOGIC_VECTOR ( 3 downto 0 );
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begin
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  d_2(0) <= d(0);
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  q(0) <= q_3(0);
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  VCC_0 : VCC
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    port map (
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      P => NLW_VCC_P_UNCONNECTED
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    );
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  GND_1 : GND
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    port map (
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      G => NLW_GND_G_UNCONNECTED
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    );
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  BU2_U0_gen_output_regs_output_regs_fd_output_1 : FDR
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    generic map(
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      INIT => '0'
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    )
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    port map (
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      C => clk,
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      D => BU2_U0_srl_sig_0_4,
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      R => sclr,
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      Q => q_3(0)
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    );
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  BU2_U0_srl_sig_0 : FD
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    generic map(
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      INIT => '0'
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    )
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    port map (
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      C => clk,
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      D => d_2(0),
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      Q => BU2_U0_srl_sig_0_4
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    );
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end STRUCTURE;
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-- synthesis translate_on

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