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[/] [fp_log/] [trunk/] [LAU/] [Virtex 5/] [DP-LAU/] [reg_32b_18c.vhd] - Blame information for rev 2

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Line No. Rev Author Line
1 2 NikosAl 
--------------------------------------------------------------------------------
2 
-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
3 
--------------------------------------------------------------------------------
4 
--   ____  ____
5 
--  /   /\/   /
6 
-- /___/  \  /    Vendor: Xilinx
7 
-- \   \   \/     Version: K.39
8 
--  \   \         Application: netgen
9 
--  /   /         Filename: reg_32b_18c.vhd
10 
-- /___/   /\     Timestamp: Wed Jun 24 18:00:33 2009
11 
-- \   \  /  \
12 
--  \___\/\___\
13 
--
14 
-- Command      : -intstyle ise -w -sim -ofmt vhdl "C:\Documents and Settings\Administrator\Desktop\Felsenstein Coprocessor\Logarithm LUT based\HW Implementation\Coregen\tmp\_cg\reg_32b_18c.ngc" "C:\Documents and Settings\Administrator\Desktop\Felsenstein Coprocessor\Logarithm LUT based\HW Implementation\Coregen\tmp\_cg\reg_32b_18c.vhd"
15 
-- Device       : 5vsx95tff1136-2
16 
-- Input file   : C:/Documents and Settings/Administrator/Desktop/Felsenstein Coprocessor/Logarithm LUT based/HW Implementation/Coregen/tmp/_cg/reg_32b_18c.ngc
17 
-- Output file  : C:/Documents and Settings/Administrator/Desktop/Felsenstein Coprocessor/Logarithm LUT based/HW Implementation/Coregen/tmp/_cg/reg_32b_18c.vhd
18 
-- # of Entities        : 1
19 
-- Design Name  : reg_32b_18c
20 
-- Xilinx       : C:\Xilinx\10.1\ISE
21 
--
22 
-- Purpose:
23 
--     This VHDL netlist is a verification model and uses simulation
24 
--     primitives which may not represent the true implementation of the
25 
--     device, however the netlist is functionally correct and should not
26 
--     be modified. This file cannot be synthesized and should only be used
27 
--     with supported simulation tools.
28 
--
29 
-- Reference:
30 
--     Development System Reference Guide, Chapter 23
31 
--     Synthesis and Simulation Design Guide, Chapter 6
32 
--
33 
--------------------------------------------------------------------------------
34 
 
35 
 
36 
-- synthesis translate_off
37 
library IEEE;
38 
use IEEE.STD_LOGIC_1164.ALL;
39 
library UNISIM;
40 
use UNISIM.VCOMPONENTS.ALL;
41 
use UNISIM.VPKG.ALL;
42 
 
43 
entity reg_32b_18c is
44 
  port (
45 
    sclr : in STD_LOGIC := 'X';
46 
    clk : in STD_LOGIC := 'X';
47 
    d : in STD_LOGIC_VECTOR ( 31 downto 0 );
48 
    q : out STD_LOGIC_VECTOR ( 31 downto 0 )
49 
  );
50 
end reg_32b_18c;
51 
 
52 
architecture STRUCTURE of reg_32b_18c is
53 
  signal BU2_sset : STD_LOGIC;
54 
  signal BU2_sinit : STD_LOGIC;
55 
  signal BU2_ainit : STD_LOGIC;
56 
  signal BU2_aclr : STD_LOGIC;
57 
  signal BU2_ce : STD_LOGIC;
58 
  signal BU2_aset : STD_LOGIC;
59 
  signal BU2_U0_Mshreg_srl_sig_16_31_130 : STD_LOGIC;
60 
  signal BU2_U0_Mshreg_srl_sig_16_30_129 : STD_LOGIC;
61 
  signal BU2_U0_Mshreg_srl_sig_16_29_128 : STD_LOGIC;
62 
  signal BU2_U0_Mshreg_srl_sig_16_28_127 : STD_LOGIC;
63 
  signal BU2_U0_Mshreg_srl_sig_16_27_126 : STD_LOGIC;
64 
  signal BU2_U0_Mshreg_srl_sig_16_26_125 : STD_LOGIC;
65 
  signal BU2_U0_Mshreg_srl_sig_16_25_124 : STD_LOGIC;
66 
  signal BU2_U0_Mshreg_srl_sig_16_24_123 : STD_LOGIC;
67 
  signal BU2_U0_Mshreg_srl_sig_16_23_122 : STD_LOGIC;
68 
  signal BU2_U0_Mshreg_srl_sig_16_22_121 : STD_LOGIC;
69 
  signal BU2_U0_Mshreg_srl_sig_16_21_120 : STD_LOGIC;
70 
  signal BU2_U0_Mshreg_srl_sig_16_20_119 : STD_LOGIC;
71 
  signal BU2_U0_Mshreg_srl_sig_16_19_118 : STD_LOGIC;
72 
  signal BU2_U0_Mshreg_srl_sig_16_18_117 : STD_LOGIC;
73 
  signal BU2_U0_Mshreg_srl_sig_16_17_116 : STD_LOGIC;
74 
  signal BU2_U0_Mshreg_srl_sig_16_16_115 : STD_LOGIC;
75 
  signal BU2_U0_Mshreg_srl_sig_16_15_114 : STD_LOGIC;
76 
  signal BU2_U0_Mshreg_srl_sig_16_14_113 : STD_LOGIC;
77 
  signal BU2_U0_Mshreg_srl_sig_16_13_112 : STD_LOGIC;
78 
  signal BU2_U0_Mshreg_srl_sig_16_12_111 : STD_LOGIC;
79 
  signal BU2_U0_Mshreg_srl_sig_16_11_110 : STD_LOGIC;
80 
  signal BU2_U0_Mshreg_srl_sig_16_10_109 : STD_LOGIC;
81 
  signal BU2_U0_Mshreg_srl_sig_16_9_108 : STD_LOGIC;
82 
  signal BU2_U0_Mshreg_srl_sig_16_8_107 : STD_LOGIC;
83 
  signal BU2_U0_Mshreg_srl_sig_16_7_106 : STD_LOGIC;
84 
  signal BU2_U0_Mshreg_srl_sig_16_6_105 : STD_LOGIC;
85 
  signal BU2_U0_Mshreg_srl_sig_16_5_104 : STD_LOGIC;
86 
  signal BU2_U0_Mshreg_srl_sig_16_4_103 : STD_LOGIC;
87 
  signal BU2_U0_Mshreg_srl_sig_16_3_102 : STD_LOGIC;
88 
  signal BU2_U0_Mshreg_srl_sig_16_2_101 : STD_LOGIC;
89 
  signal BU2_U0_Mshreg_srl_sig_16_1_100 : STD_LOGIC;
90 
  signal BU2_U0_Mshreg_srl_sig_16_0_99 : STD_LOGIC;
91 
  signal BU2_U0_N1 : STD_LOGIC;
92 
  signal BU2_U0_srl_sig_16_31_97 : STD_LOGIC;
93 
  signal BU2_U0_srl_sig_16_30_96 : STD_LOGIC;
94 
  signal BU2_U0_srl_sig_16_29_95 : STD_LOGIC;
95 
  signal BU2_U0_srl_sig_16_28_94 : STD_LOGIC;
96 
  signal BU2_U0_srl_sig_16_27_93 : STD_LOGIC;
97 
  signal BU2_U0_srl_sig_16_26_92 : STD_LOGIC;
98 
  signal BU2_U0_srl_sig_16_25_91 : STD_LOGIC;
99 
  signal BU2_U0_srl_sig_16_24_90 : STD_LOGIC;
100 
  signal BU2_U0_srl_sig_16_23_89 : STD_LOGIC;
101 
  signal BU2_U0_srl_sig_16_22_88 : STD_LOGIC;
102 
  signal BU2_U0_srl_sig_16_21_87 : STD_LOGIC;
103 
  signal BU2_U0_srl_sig_16_20_86 : STD_LOGIC;
104 
  signal BU2_U0_srl_sig_16_19_85 : STD_LOGIC;
105 
  signal BU2_U0_srl_sig_16_18_84 : STD_LOGIC;
106 
  signal BU2_U0_srl_sig_16_17_83 : STD_LOGIC;
107 
  signal BU2_U0_srl_sig_16_16_82 : STD_LOGIC;
108 
  signal BU2_U0_srl_sig_16_15_81 : STD_LOGIC;
109 
  signal BU2_U0_srl_sig_16_14_80 : STD_LOGIC;
110 
  signal BU2_U0_srl_sig_16_13_79 : STD_LOGIC;
111 
  signal BU2_U0_srl_sig_16_12_78 : STD_LOGIC;
112 
  signal BU2_U0_srl_sig_16_11_77 : STD_LOGIC;
113 
  signal BU2_U0_srl_sig_16_10_76 : STD_LOGIC;
114 
  signal BU2_U0_srl_sig_16_9_75 : STD_LOGIC;
115 
  signal BU2_U0_srl_sig_16_8_74 : STD_LOGIC;
116 
  signal BU2_U0_srl_sig_16_7_73 : STD_LOGIC;
117 
  signal BU2_U0_srl_sig_16_6_72 : STD_LOGIC;
118 
  signal BU2_U0_srl_sig_16_5_71 : STD_LOGIC;
119 
  signal BU2_U0_srl_sig_16_4_70 : STD_LOGIC;
120 
  signal BU2_U0_srl_sig_16_3_69 : STD_LOGIC;
121 
  signal BU2_U0_srl_sig_16_2_68 : STD_LOGIC;
122 
  signal BU2_U0_srl_sig_16_1_67 : STD_LOGIC;
123 
  signal BU2_U0_srl_sig_16_0_66 : STD_LOGIC;
124 
  signal NLW_VCC_P_UNCONNECTED : STD_LOGIC;
125 
  signal NLW_GND_G_UNCONNECTED : STD_LOGIC;
126 
  signal NLW_BU2_U0_Mshreg_srl_sig_16_31_Q15_UNCONNECTED : STD_LOGIC;
127 
  signal NLW_BU2_U0_Mshreg_srl_sig_16_30_Q15_UNCONNECTED : STD_LOGIC;
128 
  signal NLW_BU2_U0_Mshreg_srl_sig_16_29_Q15_UNCONNECTED : STD_LOGIC;
129 
  signal NLW_BU2_U0_Mshreg_srl_sig_16_28_Q15_UNCONNECTED : STD_LOGIC;
130 
  signal NLW_BU2_U0_Mshreg_srl_sig_16_27_Q15_UNCONNECTED : STD_LOGIC;
131 
  signal NLW_BU2_U0_Mshreg_srl_sig_16_26_Q15_UNCONNECTED : STD_LOGIC;
132 
  signal NLW_BU2_U0_Mshreg_srl_sig_16_25_Q15_UNCONNECTED : STD_LOGIC;
133 
  signal NLW_BU2_U0_Mshreg_srl_sig_16_24_Q15_UNCONNECTED : STD_LOGIC;
134 
  signal NLW_BU2_U0_Mshreg_srl_sig_16_23_Q15_UNCONNECTED : STD_LOGIC;
135 
  signal NLW_BU2_U0_Mshreg_srl_sig_16_22_Q15_UNCONNECTED : STD_LOGIC;
136 
  signal NLW_BU2_U0_Mshreg_srl_sig_16_21_Q15_UNCONNECTED : STD_LOGIC;
137 
  signal NLW_BU2_U0_Mshreg_srl_sig_16_20_Q15_UNCONNECTED : STD_LOGIC;
138 
  signal NLW_BU2_U0_Mshreg_srl_sig_16_19_Q15_UNCONNECTED : STD_LOGIC;
139 
  signal NLW_BU2_U0_Mshreg_srl_sig_16_18_Q15_UNCONNECTED : STD_LOGIC;
140 
  signal NLW_BU2_U0_Mshreg_srl_sig_16_17_Q15_UNCONNECTED : STD_LOGIC;
141 
  signal NLW_BU2_U0_Mshreg_srl_sig_16_16_Q15_UNCONNECTED : STD_LOGIC;
142 
  signal NLW_BU2_U0_Mshreg_srl_sig_16_15_Q15_UNCONNECTED : STD_LOGIC;
143 
  signal NLW_BU2_U0_Mshreg_srl_sig_16_14_Q15_UNCONNECTED : STD_LOGIC;
144 
  signal NLW_BU2_U0_Mshreg_srl_sig_16_13_Q15_UNCONNECTED : STD_LOGIC;
145 
  signal NLW_BU2_U0_Mshreg_srl_sig_16_12_Q15_UNCONNECTED : STD_LOGIC;
146 
  signal NLW_BU2_U0_Mshreg_srl_sig_16_11_Q15_UNCONNECTED : STD_LOGIC;
147 
  signal NLW_BU2_U0_Mshreg_srl_sig_16_10_Q15_UNCONNECTED : STD_LOGIC;
148 
  signal NLW_BU2_U0_Mshreg_srl_sig_16_9_Q15_UNCONNECTED : STD_LOGIC;
149 
  signal NLW_BU2_U0_Mshreg_srl_sig_16_8_Q15_UNCONNECTED : STD_LOGIC;
150 
  signal NLW_BU2_U0_Mshreg_srl_sig_16_7_Q15_UNCONNECTED : STD_LOGIC;
151 
  signal NLW_BU2_U0_Mshreg_srl_sig_16_6_Q15_UNCONNECTED : STD_LOGIC;
152 
  signal NLW_BU2_U0_Mshreg_srl_sig_16_5_Q15_UNCONNECTED : STD_LOGIC;
153 
  signal NLW_BU2_U0_Mshreg_srl_sig_16_4_Q15_UNCONNECTED : STD_LOGIC;
154 
  signal NLW_BU2_U0_Mshreg_srl_sig_16_3_Q15_UNCONNECTED : STD_LOGIC;
155 
  signal NLW_BU2_U0_Mshreg_srl_sig_16_2_Q15_UNCONNECTED : STD_LOGIC;
156 
  signal NLW_BU2_U0_Mshreg_srl_sig_16_1_Q15_UNCONNECTED : STD_LOGIC;
157 
  signal NLW_BU2_U0_Mshreg_srl_sig_16_0_Q15_UNCONNECTED : STD_LOGIC;
158 
  signal d_2 : STD_LOGIC_VECTOR ( 31 downto 0 );
159 
  signal q_3 : STD_LOGIC_VECTOR ( 31 downto 0 );
160 
  signal BU2_a : STD_LOGIC_VECTOR ( 3 downto 0 );
161 
begin
162 
  d_2(31) <= d(31);
163 
  d_2(30) <= d(30);
164 
  d_2(29) <= d(29);
165 
  d_2(28) <= d(28);
166 
  d_2(27) <= d(27);
167 
  d_2(26) <= d(26);
168 
  d_2(25) <= d(25);
169 
  d_2(24) <= d(24);
170 
  d_2(23) <= d(23);
171 
  d_2(22) <= d(22);
172 
  d_2(21) <= d(21);
173 
  d_2(20) <= d(20);
174 
  d_2(19) <= d(19);
175 
  d_2(18) <= d(18);
176 
  d_2(17) <= d(17);
177 
  d_2(16) <= d(16);
178 
  d_2(15) <= d(15);
179 
  d_2(14) <= d(14);
180 
  d_2(13) <= d(13);
181 
  d_2(12) <= d(12);
182 
  d_2(11) <= d(11);
183 
  d_2(10) <= d(10);
184 
  d_2(9) <= d(9);
185 
  d_2(8) <= d(8);
186 
  d_2(7) <= d(7);
187 
  d_2(6) <= d(6);
188 
  d_2(5) <= d(5);
189 
  d_2(4) <= d(4);
190 
  d_2(3) <= d(3);
191 
  d_2(2) <= d(2);
192 
  d_2(1) <= d(1);
193 
  d_2(0) <= d(0);
194 
  q(31) <= q_3(31);
195 
  q(30) <= q_3(30);
196 
  q(29) <= q_3(29);
197 
  q(28) <= q_3(28);
198 
  q(27) <= q_3(27);
199 
  q(26) <= q_3(26);
200 
  q(25) <= q_3(25);
201 
  q(24) <= q_3(24);
202 
  q(23) <= q_3(23);
203 
  q(22) <= q_3(22);
204 
  q(21) <= q_3(21);
205 
  q(20) <= q_3(20);
206 
  q(19) <= q_3(19);
207 
  q(18) <= q_3(18);
208 
  q(17) <= q_3(17);
209 
  q(16) <= q_3(16);
210 
  q(15) <= q_3(15);
211 
  q(14) <= q_3(14);
212 
  q(13) <= q_3(13);
213 
  q(12) <= q_3(12);
214 
  q(11) <= q_3(11);
215 
  q(10) <= q_3(10);
216 
  q(9) <= q_3(9);
217 
  q(8) <= q_3(8);
218 
  q(7) <= q_3(7);
219 
  q(6) <= q_3(6);
220 
  q(5) <= q_3(5);
221 
  q(4) <= q_3(4);
222 
  q(3) <= q_3(3);
223 
  q(2) <= q_3(2);
224 
  q(1) <= q_3(1);
225 
  q(0) <= q_3(0);
226 
  VCC_0 : VCC
227 
    port map (
228 
      P => NLW_VCC_P_UNCONNECTED
229 
    );
230 
  GND_1 : GND
231 
    port map (
232 
      G => NLW_GND_G_UNCONNECTED
233 
    );
234 
  BU2_U0_srl_sig_16_31 : FDE
235 
    generic map(
236 
      INIT => '0'
237 
    )
238 
    port map (
239 
      C => clk,
240 
      CE => BU2_U0_N1,
241 
      D => BU2_U0_Mshreg_srl_sig_16_31_130,
242 
      Q => BU2_U0_srl_sig_16_31_97
243 
    );
244 
  BU2_U0_Mshreg_srl_sig_16_31 : SRLC16E
245 
    generic map(
246 
      INIT => X"0000"
247 
    )
248 
    port map (
249 
      A0 => BU2_U0_N1,
250 
      A1 => BU2_U0_N1,
251 
      A2 => BU2_U0_N1,
252 
      A3 => BU2_U0_N1,
253 
      CE => BU2_U0_N1,
254 
      CLK => clk,
255 
      D => d_2(31),
256 
      Q => BU2_U0_Mshreg_srl_sig_16_31_130,
257 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_16_31_Q15_UNCONNECTED
258 
    );
259 
  BU2_U0_srl_sig_16_30 : FDE
260 
    generic map(
261 
      INIT => '0'
262 
    )
263 
    port map (
264 
      C => clk,
265 
      CE => BU2_U0_N1,
266 
      D => BU2_U0_Mshreg_srl_sig_16_30_129,
267 
      Q => BU2_U0_srl_sig_16_30_96
268 
    );
269 
  BU2_U0_Mshreg_srl_sig_16_30 : SRLC16E
270 
    generic map(
271 
      INIT => X"0000"
272 
    )
273 
    port map (
274 
      A0 => BU2_U0_N1,
275 
      A1 => BU2_U0_N1,
276 
      A2 => BU2_U0_N1,
277 
      A3 => BU2_U0_N1,
278 
      CE => BU2_U0_N1,
279 
      CLK => clk,
280 
      D => d_2(30),
281 
      Q => BU2_U0_Mshreg_srl_sig_16_30_129,
282 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_16_30_Q15_UNCONNECTED
283 
    );
284 
  BU2_U0_srl_sig_16_29 : FDE
285 
    generic map(
286 
      INIT => '0'
287 
    )
288 
    port map (
289 
      C => clk,
290 
      CE => BU2_U0_N1,
291 
      D => BU2_U0_Mshreg_srl_sig_16_29_128,
292 
      Q => BU2_U0_srl_sig_16_29_95
293 
    );
294 
  BU2_U0_Mshreg_srl_sig_16_29 : SRLC16E
295 
    generic map(
296 
      INIT => X"0000"
297 
    )
298 
    port map (
299 
      A0 => BU2_U0_N1,
300 
      A1 => BU2_U0_N1,
301 
      A2 => BU2_U0_N1,
302 
      A3 => BU2_U0_N1,
303 
      CE => BU2_U0_N1,
304 
      CLK => clk,
305 
      D => d_2(29),
306 
      Q => BU2_U0_Mshreg_srl_sig_16_29_128,
307 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_16_29_Q15_UNCONNECTED
308 
    );
309 
  BU2_U0_srl_sig_16_28 : FDE
310 
    generic map(
311 
      INIT => '0'
312 
    )
313 
    port map (
314 
      C => clk,
315 
      CE => BU2_U0_N1,
316 
      D => BU2_U0_Mshreg_srl_sig_16_28_127,
317 
      Q => BU2_U0_srl_sig_16_28_94
318 
    );
319 
  BU2_U0_Mshreg_srl_sig_16_28 : SRLC16E
320 
    generic map(
321 
      INIT => X"0000"
322 
    )
323 
    port map (
324 
      A0 => BU2_U0_N1,
325 
      A1 => BU2_U0_N1,
326 
      A2 => BU2_U0_N1,
327 
      A3 => BU2_U0_N1,
328 
      CE => BU2_U0_N1,
329 
      CLK => clk,
330 
      D => d_2(28),
331 
      Q => BU2_U0_Mshreg_srl_sig_16_28_127,
332 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_16_28_Q15_UNCONNECTED
333 
    );
334 
  BU2_U0_srl_sig_16_27 : FDE
335 
    generic map(
336 
      INIT => '0'
337 
    )
338 
    port map (
339 
      C => clk,
340 
      CE => BU2_U0_N1,
341 
      D => BU2_U0_Mshreg_srl_sig_16_27_126,
342 
      Q => BU2_U0_srl_sig_16_27_93
343 
    );
344 
  BU2_U0_Mshreg_srl_sig_16_27 : SRLC16E
345 
    generic map(
346 
      INIT => X"0000"
347 
    )
348 
    port map (
349 
      A0 => BU2_U0_N1,
350 
      A1 => BU2_U0_N1,
351 
      A2 => BU2_U0_N1,
352 
      A3 => BU2_U0_N1,
353 
      CE => BU2_U0_N1,
354 
      CLK => clk,
355 
      D => d_2(27),
356 
      Q => BU2_U0_Mshreg_srl_sig_16_27_126,
357 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_16_27_Q15_UNCONNECTED
358 
    );
359 
  BU2_U0_srl_sig_16_26 : FDE
360 
    generic map(
361 
      INIT => '0'
362 
    )
363 
    port map (
364 
      C => clk,
365 
      CE => BU2_U0_N1,
366 
      D => BU2_U0_Mshreg_srl_sig_16_26_125,
367 
      Q => BU2_U0_srl_sig_16_26_92
368 
    );
369 
  BU2_U0_Mshreg_srl_sig_16_26 : SRLC16E
370 
    generic map(
371 
      INIT => X"0000"
372 
    )
373 
    port map (
374 
      A0 => BU2_U0_N1,
375 
      A1 => BU2_U0_N1,
376 
      A2 => BU2_U0_N1,
377 
      A3 => BU2_U0_N1,
378 
      CE => BU2_U0_N1,
379 
      CLK => clk,
380 
      D => d_2(26),
381 
      Q => BU2_U0_Mshreg_srl_sig_16_26_125,
382 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_16_26_Q15_UNCONNECTED
383 
    );
384 
  BU2_U0_srl_sig_16_25 : FDE
385 
    generic map(
386 
      INIT => '0'
387 
    )
388 
    port map (
389 
      C => clk,
390 
      CE => BU2_U0_N1,
391 
      D => BU2_U0_Mshreg_srl_sig_16_25_124,
392 
      Q => BU2_U0_srl_sig_16_25_91
393 
    );
394 
  BU2_U0_Mshreg_srl_sig_16_25 : SRLC16E
395 
    generic map(
396 
      INIT => X"0000"
397 
    )
398 
    port map (
399 
      A0 => BU2_U0_N1,
400 
      A1 => BU2_U0_N1,
401 
      A2 => BU2_U0_N1,
402 
      A3 => BU2_U0_N1,
403 
      CE => BU2_U0_N1,
404 
      CLK => clk,
405 
      D => d_2(25),
406 
      Q => BU2_U0_Mshreg_srl_sig_16_25_124,
407 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_16_25_Q15_UNCONNECTED
408 
    );
409 
  BU2_U0_srl_sig_16_24 : FDE
410 
    generic map(
411 
      INIT => '0'
412 
    )
413 
    port map (
414 
      C => clk,
415 
      CE => BU2_U0_N1,
416 
      D => BU2_U0_Mshreg_srl_sig_16_24_123,
417 
      Q => BU2_U0_srl_sig_16_24_90
418 
    );
419 
  BU2_U0_Mshreg_srl_sig_16_24 : SRLC16E
420 
    generic map(
421 
      INIT => X"0000"
422 
    )
423 
    port map (
424 
      A0 => BU2_U0_N1,
425 
      A1 => BU2_U0_N1,
426 
      A2 => BU2_U0_N1,
427 
      A3 => BU2_U0_N1,
428 
      CE => BU2_U0_N1,
429 
      CLK => clk,
430 
      D => d_2(24),
431 
      Q => BU2_U0_Mshreg_srl_sig_16_24_123,
432 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_16_24_Q15_UNCONNECTED
433 
    );
434 
  BU2_U0_srl_sig_16_23 : FDE
435 
    generic map(
436 
      INIT => '0'
437 
    )
438 
    port map (
439 
      C => clk,
440 
      CE => BU2_U0_N1,
441 
      D => BU2_U0_Mshreg_srl_sig_16_23_122,
442 
      Q => BU2_U0_srl_sig_16_23_89
443 
    );
444 
  BU2_U0_Mshreg_srl_sig_16_23 : SRLC16E
445 
    generic map(
446 
      INIT => X"0000"
447 
    )
448 
    port map (
449 
      A0 => BU2_U0_N1,
450 
      A1 => BU2_U0_N1,
451 
      A2 => BU2_U0_N1,
452 
      A3 => BU2_U0_N1,
453 
      CE => BU2_U0_N1,
454 
      CLK => clk,
455 
      D => d_2(23),
456 
      Q => BU2_U0_Mshreg_srl_sig_16_23_122,
457 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_16_23_Q15_UNCONNECTED
458 
    );
459 
  BU2_U0_srl_sig_16_22 : FDE
460 
    generic map(
461 
      INIT => '0'
462 
    )
463 
    port map (
464 
      C => clk,
465 
      CE => BU2_U0_N1,
466 
      D => BU2_U0_Mshreg_srl_sig_16_22_121,
467 
      Q => BU2_U0_srl_sig_16_22_88
468 
    );
469 
  BU2_U0_Mshreg_srl_sig_16_22 : SRLC16E
470 
    generic map(
471 
      INIT => X"0000"
472 
    )
473 
    port map (
474 
      A0 => BU2_U0_N1,
475 
      A1 => BU2_U0_N1,
476 
      A2 => BU2_U0_N1,
477 
      A3 => BU2_U0_N1,
478 
      CE => BU2_U0_N1,
479 
      CLK => clk,
480 
      D => d_2(22),
481 
      Q => BU2_U0_Mshreg_srl_sig_16_22_121,
482 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_16_22_Q15_UNCONNECTED
483 
    );
484 
  BU2_U0_srl_sig_16_21 : FDE
485 
    generic map(
486 
      INIT => '0'
487 
    )
488 
    port map (
489 
      C => clk,
490 
      CE => BU2_U0_N1,
491 
      D => BU2_U0_Mshreg_srl_sig_16_21_120,
492 
      Q => BU2_U0_srl_sig_16_21_87
493 
    );
494 
  BU2_U0_Mshreg_srl_sig_16_21 : SRLC16E
495 
    generic map(
496 
      INIT => X"0000"
497 
    )
498 
    port map (
499 
      A0 => BU2_U0_N1,
500 
      A1 => BU2_U0_N1,
501 
      A2 => BU2_U0_N1,
502 
      A3 => BU2_U0_N1,
503 
      CE => BU2_U0_N1,
504 
      CLK => clk,
505 
      D => d_2(21),
506 
      Q => BU2_U0_Mshreg_srl_sig_16_21_120,
507 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_16_21_Q15_UNCONNECTED
508 
    );
509 
  BU2_U0_srl_sig_16_20 : FDE
510 
    generic map(
511 
      INIT => '0'
512 
    )
513 
    port map (
514 
      C => clk,
515 
      CE => BU2_U0_N1,
516 
      D => BU2_U0_Mshreg_srl_sig_16_20_119,
517 
      Q => BU2_U0_srl_sig_16_20_86
518 
    );
519 
  BU2_U0_Mshreg_srl_sig_16_20 : SRLC16E
520 
    generic map(
521 
      INIT => X"0000"
522 
    )
523 
    port map (
524 
      A0 => BU2_U0_N1,
525 
      A1 => BU2_U0_N1,
526 
      A2 => BU2_U0_N1,
527 
      A3 => BU2_U0_N1,
528 
      CE => BU2_U0_N1,
529 
      CLK => clk,
530 
      D => d_2(20),
531 
      Q => BU2_U0_Mshreg_srl_sig_16_20_119,
532 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_16_20_Q15_UNCONNECTED
533 
    );
534 
  BU2_U0_srl_sig_16_19 : FDE
535 
    generic map(
536 
      INIT => '0'
537 
    )
538 
    port map (
539 
      C => clk,
540 
      CE => BU2_U0_N1,
541 
      D => BU2_U0_Mshreg_srl_sig_16_19_118,
542 
      Q => BU2_U0_srl_sig_16_19_85
543 
    );
544 
  BU2_U0_Mshreg_srl_sig_16_19 : SRLC16E
545 
    generic map(
546 
      INIT => X"0000"
547 
    )
548 
    port map (
549 
      A0 => BU2_U0_N1,
550 
      A1 => BU2_U0_N1,
551 
      A2 => BU2_U0_N1,
552 
      A3 => BU2_U0_N1,
553 
      CE => BU2_U0_N1,
554 
      CLK => clk,
555 
      D => d_2(19),
556 
      Q => BU2_U0_Mshreg_srl_sig_16_19_118,
557 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_16_19_Q15_UNCONNECTED
558 
    );
559 
  BU2_U0_srl_sig_16_18 : FDE
560 
    generic map(
561 
      INIT => '0'
562 
    )
563 
    port map (
564 
      C => clk,
565 
      CE => BU2_U0_N1,
566 
      D => BU2_U0_Mshreg_srl_sig_16_18_117,
567 
      Q => BU2_U0_srl_sig_16_18_84
568 
    );
569 
  BU2_U0_Mshreg_srl_sig_16_18 : SRLC16E
570 
    generic map(
571 
      INIT => X"0000"
572 
    )
573 
    port map (
574 
      A0 => BU2_U0_N1,
575 
      A1 => BU2_U0_N1,
576 
      A2 => BU2_U0_N1,
577 
      A3 => BU2_U0_N1,
578 
      CE => BU2_U0_N1,
579 
      CLK => clk,
580 
      D => d_2(18),
581 
      Q => BU2_U0_Mshreg_srl_sig_16_18_117,
582 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_16_18_Q15_UNCONNECTED
583 
    );
584 
  BU2_U0_srl_sig_16_17 : FDE
585 
    generic map(
586 
      INIT => '0'
587 
    )
588 
    port map (
589 
      C => clk,
590 
      CE => BU2_U0_N1,
591 
      D => BU2_U0_Mshreg_srl_sig_16_17_116,
592 
      Q => BU2_U0_srl_sig_16_17_83
593 
    );
594 
  BU2_U0_Mshreg_srl_sig_16_17 : SRLC16E
595 
    generic map(
596 
      INIT => X"0000"
597 
    )
598 
    port map (
599 
      A0 => BU2_U0_N1,
600 
      A1 => BU2_U0_N1,
601 
      A2 => BU2_U0_N1,
602 
      A3 => BU2_U0_N1,
603 
      CE => BU2_U0_N1,
604 
      CLK => clk,
605 
      D => d_2(17),
606 
      Q => BU2_U0_Mshreg_srl_sig_16_17_116,
607 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_16_17_Q15_UNCONNECTED
608 
    );
609 
  BU2_U0_srl_sig_16_16 : FDE
610 
    generic map(
611 
      INIT => '0'
612 
    )
613 
    port map (
614 
      C => clk,
615 
      CE => BU2_U0_N1,
616 
      D => BU2_U0_Mshreg_srl_sig_16_16_115,
617 
      Q => BU2_U0_srl_sig_16_16_82
618 
    );
619 
  BU2_U0_Mshreg_srl_sig_16_16 : SRLC16E
620 
    generic map(
621 
      INIT => X"0000"
622 
    )
623 
    port map (
624 
      A0 => BU2_U0_N1,
625 
      A1 => BU2_U0_N1,
626 
      A2 => BU2_U0_N1,
627 
      A3 => BU2_U0_N1,
628 
      CE => BU2_U0_N1,
629 
      CLK => clk,
630 
      D => d_2(16),
631 
      Q => BU2_U0_Mshreg_srl_sig_16_16_115,
632 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_16_16_Q15_UNCONNECTED
633 
    );
634 
  BU2_U0_srl_sig_16_15 : FDE
635 
    generic map(
636 
      INIT => '0'
637 
    )
638 
    port map (
639 
      C => clk,
640 
      CE => BU2_U0_N1,
641 
      D => BU2_U0_Mshreg_srl_sig_16_15_114,
642 
      Q => BU2_U0_srl_sig_16_15_81
643 
    );
644 
  BU2_U0_Mshreg_srl_sig_16_15 : SRLC16E
645 
    generic map(
646 
      INIT => X"0000"
647 
    )
648 
    port map (
649 
      A0 => BU2_U0_N1,
650 
      A1 => BU2_U0_N1,
651 
      A2 => BU2_U0_N1,
652 
      A3 => BU2_U0_N1,
653 
      CE => BU2_U0_N1,
654 
      CLK => clk,
655 
      D => d_2(15),
656 
      Q => BU2_U0_Mshreg_srl_sig_16_15_114,
657 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_16_15_Q15_UNCONNECTED
658 
    );
659 
  BU2_U0_srl_sig_16_14 : FDE
660 
    generic map(
661 
      INIT => '0'
662 
    )
663 
    port map (
664 
      C => clk,
665 
      CE => BU2_U0_N1,
666 
      D => BU2_U0_Mshreg_srl_sig_16_14_113,
667 
      Q => BU2_U0_srl_sig_16_14_80
668 
    );
669 
  BU2_U0_Mshreg_srl_sig_16_14 : SRLC16E
670 
    generic map(
671 
      INIT => X"0000"
672 
    )
673 
    port map (
674 
      A0 => BU2_U0_N1,
675 
      A1 => BU2_U0_N1,
676 
      A2 => BU2_U0_N1,
677 
      A3 => BU2_U0_N1,
678 
      CE => BU2_U0_N1,
679 
      CLK => clk,
680 
      D => d_2(14),
681 
      Q => BU2_U0_Mshreg_srl_sig_16_14_113,
682 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_16_14_Q15_UNCONNECTED
683 
    );
684 
  BU2_U0_srl_sig_16_13 : FDE
685 
    generic map(
686 
      INIT => '0'
687 
    )
688 
    port map (
689 
      C => clk,
690 
      CE => BU2_U0_N1,
691 
      D => BU2_U0_Mshreg_srl_sig_16_13_112,
692 
      Q => BU2_U0_srl_sig_16_13_79
693 
    );
694 
  BU2_U0_Mshreg_srl_sig_16_13 : SRLC16E
695 
    generic map(
696 
      INIT => X"0000"
697 
    )
698 
    port map (
699 
      A0 => BU2_U0_N1,
700 
      A1 => BU2_U0_N1,
701 
      A2 => BU2_U0_N1,
702 
      A3 => BU2_U0_N1,
703 
      CE => BU2_U0_N1,
704 
      CLK => clk,
705 
      D => d_2(13),
706 
      Q => BU2_U0_Mshreg_srl_sig_16_13_112,
707 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_16_13_Q15_UNCONNECTED
708 
    );
709 
  BU2_U0_srl_sig_16_12 : FDE
710 
    generic map(
711 
      INIT => '0'
712 
    )
713 
    port map (
714 
      C => clk,
715 
      CE => BU2_U0_N1,
716 
      D => BU2_U0_Mshreg_srl_sig_16_12_111,
717 
      Q => BU2_U0_srl_sig_16_12_78
718 
    );
719 
  BU2_U0_Mshreg_srl_sig_16_12 : SRLC16E
720 
    generic map(
721 
      INIT => X"0000"
722 
    )
723 
    port map (
724 
      A0 => BU2_U0_N1,
725 
      A1 => BU2_U0_N1,
726 
      A2 => BU2_U0_N1,
727 
      A3 => BU2_U0_N1,
728 
      CE => BU2_U0_N1,
729 
      CLK => clk,
730 
      D => d_2(12),
731 
      Q => BU2_U0_Mshreg_srl_sig_16_12_111,
732 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_16_12_Q15_UNCONNECTED
733 
    );
734 
  BU2_U0_srl_sig_16_11 : FDE
735 
    generic map(
736 
      INIT => '0'
737 
    )
738 
    port map (
739 
      C => clk,
740 
      CE => BU2_U0_N1,
741 
      D => BU2_U0_Mshreg_srl_sig_16_11_110,
742 
      Q => BU2_U0_srl_sig_16_11_77
743 
    );
744 
  BU2_U0_Mshreg_srl_sig_16_11 : SRLC16E
745 
    generic map(
746 
      INIT => X"0000"
747 
    )
748 
    port map (
749 
      A0 => BU2_U0_N1,
750 
      A1 => BU2_U0_N1,
751 
      A2 => BU2_U0_N1,
752 
      A3 => BU2_U0_N1,
753 
      CE => BU2_U0_N1,
754 
      CLK => clk,
755 
      D => d_2(11),
756 
      Q => BU2_U0_Mshreg_srl_sig_16_11_110,
757 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_16_11_Q15_UNCONNECTED
758 
    );
759 
  BU2_U0_srl_sig_16_10 : FDE
760 
    generic map(
761 
      INIT => '0'
762 
    )
763 
    port map (
764 
      C => clk,
765 
      CE => BU2_U0_N1,
766 
      D => BU2_U0_Mshreg_srl_sig_16_10_109,
767 
      Q => BU2_U0_srl_sig_16_10_76
768 
    );
769 
  BU2_U0_Mshreg_srl_sig_16_10 : SRLC16E
770 
    generic map(
771 
      INIT => X"0000"
772 
    )
773 
    port map (
774 
      A0 => BU2_U0_N1,
775 
      A1 => BU2_U0_N1,
776 
      A2 => BU2_U0_N1,
777 
      A3 => BU2_U0_N1,
778 
      CE => BU2_U0_N1,
779 
      CLK => clk,
780 
      D => d_2(10),
781 
      Q => BU2_U0_Mshreg_srl_sig_16_10_109,
782 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_16_10_Q15_UNCONNECTED
783 
    );
784 
  BU2_U0_srl_sig_16_9 : FDE
785 
    generic map(
786 
      INIT => '0'
787 
    )
788 
    port map (
789 
      C => clk,
790 
      CE => BU2_U0_N1,
791 
      D => BU2_U0_Mshreg_srl_sig_16_9_108,
792 
      Q => BU2_U0_srl_sig_16_9_75
793 
    );
794 
  BU2_U0_Mshreg_srl_sig_16_9 : SRLC16E
795 
    generic map(
796 
      INIT => X"0000"
797 
    )
798 
    port map (
799 
      A0 => BU2_U0_N1,
800 
      A1 => BU2_U0_N1,
801 
      A2 => BU2_U0_N1,
802 
      A3 => BU2_U0_N1,
803 
      CE => BU2_U0_N1,
804 
      CLK => clk,
805 
      D => d_2(9),
806 
      Q => BU2_U0_Mshreg_srl_sig_16_9_108,
807 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_16_9_Q15_UNCONNECTED
808 
    );
809 
  BU2_U0_srl_sig_16_8 : FDE
810 
    generic map(
811 
      INIT => '0'
812 
    )
813 
    port map (
814 
      C => clk,
815 
      CE => BU2_U0_N1,
816 
      D => BU2_U0_Mshreg_srl_sig_16_8_107,
817 
      Q => BU2_U0_srl_sig_16_8_74
818 
    );
819 
  BU2_U0_Mshreg_srl_sig_16_8 : SRLC16E
820 
    generic map(
821 
      INIT => X"0000"
822 
    )
823 
    port map (
824 
      A0 => BU2_U0_N1,
825 
      A1 => BU2_U0_N1,
826 
      A2 => BU2_U0_N1,
827 
      A3 => BU2_U0_N1,
828 
      CE => BU2_U0_N1,
829 
      CLK => clk,
830 
      D => d_2(8),
831 
      Q => BU2_U0_Mshreg_srl_sig_16_8_107,
832 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_16_8_Q15_UNCONNECTED
833 
    );
834 
  BU2_U0_srl_sig_16_7 : FDE
835 
    generic map(
836 
      INIT => '0'
837 
    )
838 
    port map (
839 
      C => clk,
840 
      CE => BU2_U0_N1,
841 
      D => BU2_U0_Mshreg_srl_sig_16_7_106,
842 
      Q => BU2_U0_srl_sig_16_7_73
843 
    );
844 
  BU2_U0_Mshreg_srl_sig_16_7 : SRLC16E
845 
    generic map(
846 
      INIT => X"0000"
847 
    )
848 
    port map (
849 
      A0 => BU2_U0_N1,
850 
      A1 => BU2_U0_N1,
851 
      A2 => BU2_U0_N1,
852 
      A3 => BU2_U0_N1,
853 
      CE => BU2_U0_N1,
854 
      CLK => clk,
855 
      D => d_2(7),
856 
      Q => BU2_U0_Mshreg_srl_sig_16_7_106,
857 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_16_7_Q15_UNCONNECTED
858 
    );
859 
  BU2_U0_srl_sig_16_6 : FDE
860 
    generic map(
861 
      INIT => '0'
862 
    )
863 
    port map (
864 
      C => clk,
865 
      CE => BU2_U0_N1,
866 
      D => BU2_U0_Mshreg_srl_sig_16_6_105,
867 
      Q => BU2_U0_srl_sig_16_6_72
868 
    );
869 
  BU2_U0_Mshreg_srl_sig_16_6 : SRLC16E
870 
    generic map(
871 
      INIT => X"0000"
872 
    )
873 
    port map (
874 
      A0 => BU2_U0_N1,
875 
      A1 => BU2_U0_N1,
876 
      A2 => BU2_U0_N1,
877 
      A3 => BU2_U0_N1,
878 
      CE => BU2_U0_N1,
879 
      CLK => clk,
880 
      D => d_2(6),
881 
      Q => BU2_U0_Mshreg_srl_sig_16_6_105,
882 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_16_6_Q15_UNCONNECTED
883 
    );
884 
  BU2_U0_srl_sig_16_5 : FDE
885 
    generic map(
886 
      INIT => '0'
887 
    )
888 
    port map (
889 
      C => clk,
890 
      CE => BU2_U0_N1,
891 
      D => BU2_U0_Mshreg_srl_sig_16_5_104,
892 
      Q => BU2_U0_srl_sig_16_5_71
893 
    );
894 
  BU2_U0_Mshreg_srl_sig_16_5 : SRLC16E
895 
    generic map(
896 
      INIT => X"0000"
897 
    )
898 
    port map (
899 
      A0 => BU2_U0_N1,
900 
      A1 => BU2_U0_N1,
901 
      A2 => BU2_U0_N1,
902 
      A3 => BU2_U0_N1,
903 
      CE => BU2_U0_N1,
904 
      CLK => clk,
905 
      D => d_2(5),
906 
      Q => BU2_U0_Mshreg_srl_sig_16_5_104,
907 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_16_5_Q15_UNCONNECTED
908 
    );
909 
  BU2_U0_srl_sig_16_4 : FDE
910 
    generic map(
911 
      INIT => '0'
912 
    )
913 
    port map (
914 
      C => clk,
915 
      CE => BU2_U0_N1,
916 
      D => BU2_U0_Mshreg_srl_sig_16_4_103,
917 
      Q => BU2_U0_srl_sig_16_4_70
918 
    );
919 
  BU2_U0_Mshreg_srl_sig_16_4 : SRLC16E
920 
    generic map(
921 
      INIT => X"0000"
922 
    )
923 
    port map (
924 
      A0 => BU2_U0_N1,
925 
      A1 => BU2_U0_N1,
926 
      A2 => BU2_U0_N1,
927 
      A3 => BU2_U0_N1,
928 
      CE => BU2_U0_N1,
929 
      CLK => clk,
930 
      D => d_2(4),
931 
      Q => BU2_U0_Mshreg_srl_sig_16_4_103,
932 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_16_4_Q15_UNCONNECTED
933 
    );
934 
  BU2_U0_srl_sig_16_3 : FDE
935 
    generic map(
936 
      INIT => '0'
937 
    )
938 
    port map (
939 
      C => clk,
940 
      CE => BU2_U0_N1,
941 
      D => BU2_U0_Mshreg_srl_sig_16_3_102,
942 
      Q => BU2_U0_srl_sig_16_3_69
943 
    );
944 
  BU2_U0_Mshreg_srl_sig_16_3 : SRLC16E
945 
    generic map(
946 
      INIT => X"0000"
947 
    )
948 
    port map (
949 
      A0 => BU2_U0_N1,
950 
      A1 => BU2_U0_N1,
951 
      A2 => BU2_U0_N1,
952 
      A3 => BU2_U0_N1,
953 
      CE => BU2_U0_N1,
954 
      CLK => clk,
955 
      D => d_2(3),
956 
      Q => BU2_U0_Mshreg_srl_sig_16_3_102,
957 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_16_3_Q15_UNCONNECTED
958 
    );
959 
  BU2_U0_srl_sig_16_2 : FDE
960 
    generic map(
961 
      INIT => '0'
962 
    )
963 
    port map (
964 
      C => clk,
965 
      CE => BU2_U0_N1,
966 
      D => BU2_U0_Mshreg_srl_sig_16_2_101,
967 
      Q => BU2_U0_srl_sig_16_2_68
968 
    );
969 
  BU2_U0_Mshreg_srl_sig_16_2 : SRLC16E
970 
    generic map(
971 
      INIT => X"0000"
972 
    )
973 
    port map (
974 
      A0 => BU2_U0_N1,
975 
      A1 => BU2_U0_N1,
976 
      A2 => BU2_U0_N1,
977 
      A3 => BU2_U0_N1,
978 
      CE => BU2_U0_N1,
979 
      CLK => clk,
980 
      D => d_2(2),
981 
      Q => BU2_U0_Mshreg_srl_sig_16_2_101,
982 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_16_2_Q15_UNCONNECTED
983 
    );
984 
  BU2_U0_srl_sig_16_1 : FDE
985 
    generic map(
986 
      INIT => '0'
987 
    )
988 
    port map (
989 
      C => clk,
990 
      CE => BU2_U0_N1,
991 
      D => BU2_U0_Mshreg_srl_sig_16_1_100,
992 
      Q => BU2_U0_srl_sig_16_1_67
993 
    );
994 
  BU2_U0_Mshreg_srl_sig_16_1 : SRLC16E
995 
    generic map(
996 
      INIT => X"0000"
997 
    )
998 
    port map (
999 
      A0 => BU2_U0_N1,
1000 
      A1 => BU2_U0_N1,
1001 
      A2 => BU2_U0_N1,
1002 
      A3 => BU2_U0_N1,
1003 
      CE => BU2_U0_N1,
1004 
      CLK => clk,
1005 
      D => d_2(1),
1006 
      Q => BU2_U0_Mshreg_srl_sig_16_1_100,
1007 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_16_1_Q15_UNCONNECTED
1008 
    );
1009 
  BU2_U0_srl_sig_16_0 : FDE
1010 
    generic map(
1011 
      INIT => '0'
1012 
    )
1013 
    port map (
1014 
      C => clk,
1015 
      CE => BU2_U0_N1,
1016 
      D => BU2_U0_Mshreg_srl_sig_16_0_99,
1017 
      Q => BU2_U0_srl_sig_16_0_66
1018 
    );
1019 
  BU2_U0_Mshreg_srl_sig_16_0 : SRLC16E
1020 
    generic map(
1021 
      INIT => X"0000"
1022 
    )
1023 
    port map (
1024 
      A0 => BU2_U0_N1,
1025 
      A1 => BU2_U0_N1,
1026 
      A2 => BU2_U0_N1,
1027 
      A3 => BU2_U0_N1,
1028 
      CE => BU2_U0_N1,
1029 
      CLK => clk,
1030 
      D => d_2(0),
1031 
      Q => BU2_U0_Mshreg_srl_sig_16_0_99,
1032 
      Q15 => NLW_BU2_U0_Mshreg_srl_sig_16_0_Q15_UNCONNECTED
1033 
    );
1034 
  BU2_U0_XST_VCC : VCC
1035 
    port map (
1036 
      P => BU2_U0_N1
1037 
    );
1038 
  BU2_U0_gen_output_regs_output_regs_fd_output_32 : FDR
1039 
    generic map(
1040 
      INIT => '0'
1041 
    )
1042 
    port map (
1043 
      C => clk,
1044 
      D => BU2_U0_srl_sig_16_31_97,
1045 
      R => sclr,
1046 
      Q => q_3(31)
1047 
    );
1048 
  BU2_U0_gen_output_regs_output_regs_fd_output_31 : FDR
1049 
    generic map(
1050 
      INIT => '0'
1051 
    )
1052 
    port map (
1053 
      C => clk,
1054 
      D => BU2_U0_srl_sig_16_30_96,
1055 
      R => sclr,
1056 
      Q => q_3(30)
1057 
    );
1058 
  BU2_U0_gen_output_regs_output_regs_fd_output_30 : FDR
1059 
    generic map(
1060 
      INIT => '0'
1061 
    )
1062 
    port map (
1063 
      C => clk,
1064 
      D => BU2_U0_srl_sig_16_29_95,
1065 
      R => sclr,
1066 
      Q => q_3(29)
1067 
    );
1068 
  BU2_U0_gen_output_regs_output_regs_fd_output_29 : FDR
1069 
    generic map(
1070 
      INIT => '0'
1071 
    )
1072 
    port map (
1073 
      C => clk,
1074 
      D => BU2_U0_srl_sig_16_28_94,
1075 
      R => sclr,
1076 
      Q => q_3(28)
1077 
    );
1078 
  BU2_U0_gen_output_regs_output_regs_fd_output_28 : FDR
1079 
    generic map(
1080 
      INIT => '0'
1081 
    )
1082 
    port map (
1083 
      C => clk,
1084 
      D => BU2_U0_srl_sig_16_27_93,
1085 
      R => sclr,
1086 
      Q => q_3(27)
1087 
    );
1088 
  BU2_U0_gen_output_regs_output_regs_fd_output_27 : FDR
1089 
    generic map(
1090 
      INIT => '0'
1091 
    )
1092 
    port map (
1093 
      C => clk,
1094 
      D => BU2_U0_srl_sig_16_26_92,
1095 
      R => sclr,
1096 
      Q => q_3(26)
1097 
    );
1098 
  BU2_U0_gen_output_regs_output_regs_fd_output_26 : FDR
1099 
    generic map(
1100 
      INIT => '0'
1101 
    )
1102 
    port map (
1103 
      C => clk,
1104 
      D => BU2_U0_srl_sig_16_25_91,
1105 
      R => sclr,
1106 
      Q => q_3(25)
1107 
    );
1108 
  BU2_U0_gen_output_regs_output_regs_fd_output_25 : FDR
1109 
    generic map(
1110 
      INIT => '0'
1111 
    )
1112 
    port map (
1113 
      C => clk,
1114 
      D => BU2_U0_srl_sig_16_24_90,
1115 
      R => sclr,
1116 
      Q => q_3(24)
1117 
    );
1118 
  BU2_U0_gen_output_regs_output_regs_fd_output_24 : FDR
1119 
    generic map(
1120 
      INIT => '0'
1121 
    )
1122 
    port map (
1123 
      C => clk,
1124 
      D => BU2_U0_srl_sig_16_23_89,
1125 
      R => sclr,
1126 
      Q => q_3(23)
1127 
    );
1128 
  BU2_U0_gen_output_regs_output_regs_fd_output_23 : FDR
1129 
    generic map(
1130 
      INIT => '0'
1131 
    )
1132 
    port map (
1133 
      C => clk,
1134 
      D => BU2_U0_srl_sig_16_22_88,
1135 
      R => sclr,
1136 
      Q => q_3(22)
1137 
    );
1138 
  BU2_U0_gen_output_regs_output_regs_fd_output_22 : FDR
1139 
    generic map(
1140 
      INIT => '0'
1141 
    )
1142 
    port map (
1143 
      C => clk,
1144 
      D => BU2_U0_srl_sig_16_21_87,
1145 
      R => sclr,
1146 
      Q => q_3(21)
1147 
    );
1148 
  BU2_U0_gen_output_regs_output_regs_fd_output_21 : FDR
1149 
    generic map(
1150 
      INIT => '0'
1151 
    )
1152 
    port map (
1153 
      C => clk,
1154 
      D => BU2_U0_srl_sig_16_20_86,
1155 
      R => sclr,
1156 
      Q => q_3(20)
1157 
    );
1158 
  BU2_U0_gen_output_regs_output_regs_fd_output_20 : FDR
1159 
    generic map(
1160 
      INIT => '0'
1161 
    )
1162 
    port map (
1163 
      C => clk,
1164 
      D => BU2_U0_srl_sig_16_19_85,
1165 
      R => sclr,
1166 
      Q => q_3(19)
1167 
    );
1168 
  BU2_U0_gen_output_regs_output_regs_fd_output_19 : FDR
1169 
    generic map(
1170 
      INIT => '0'
1171 
    )
1172 
    port map (
1173 
      C => clk,
1174 
      D => BU2_U0_srl_sig_16_18_84,
1175 
      R => sclr,
1176 
      Q => q_3(18)
1177 
    );
1178 
  BU2_U0_gen_output_regs_output_regs_fd_output_18 : FDR
1179 
    generic map(
1180 
      INIT => '0'
1181 
    )
1182 
    port map (
1183 
      C => clk,
1184 
      D => BU2_U0_srl_sig_16_17_83,
1185 
      R => sclr,
1186 
      Q => q_3(17)
1187 
    );
1188 
  BU2_U0_gen_output_regs_output_regs_fd_output_17 : FDR
1189 
    generic map(
1190 
      INIT => '0'
1191 
    )
1192 
    port map (
1193 
      C => clk,
1194 
      D => BU2_U0_srl_sig_16_16_82,
1195 
      R => sclr,
1196 
      Q => q_3(16)
1197 
    );
1198 
  BU2_U0_gen_output_regs_output_regs_fd_output_16 : FDR
1199 
    generic map(
1200 
      INIT => '0'
1201 
    )
1202 
    port map (
1203 
      C => clk,
1204 
      D => BU2_U0_srl_sig_16_15_81,
1205 
      R => sclr,
1206 
      Q => q_3(15)
1207 
    );
1208 
  BU2_U0_gen_output_regs_output_regs_fd_output_15 : FDR
1209 
    generic map(
1210 
      INIT => '0'
1211 
    )
1212 
    port map (
1213 
      C => clk,
1214 
      D => BU2_U0_srl_sig_16_14_80,
1215 
      R => sclr,
1216 
      Q => q_3(14)
1217 
    );
1218 
  BU2_U0_gen_output_regs_output_regs_fd_output_14 : FDR
1219 
    generic map(
1220 
      INIT => '0'
1221 
    )
1222 
    port map (
1223 
      C => clk,
1224 
      D => BU2_U0_srl_sig_16_13_79,
1225 
      R => sclr,
1226 
      Q => q_3(13)
1227 
    );
1228 
  BU2_U0_gen_output_regs_output_regs_fd_output_13 : FDR
1229 
    generic map(
1230 
      INIT => '0'
1231 
    )
1232 
    port map (
1233 
      C => clk,
1234 
      D => BU2_U0_srl_sig_16_12_78,
1235 
      R => sclr,
1236 
      Q => q_3(12)
1237 
    );
1238 
  BU2_U0_gen_output_regs_output_regs_fd_output_12 : FDR
1239 
    generic map(
1240 
      INIT => '0'
1241 
    )
1242 
    port map (
1243 
      C => clk,
1244 
      D => BU2_U0_srl_sig_16_11_77,
1245 
      R => sclr,
1246 
      Q => q_3(11)
1247 
    );
1248 
  BU2_U0_gen_output_regs_output_regs_fd_output_11 : FDR
1249 
    generic map(
1250 
      INIT => '0'
1251 
    )
1252 
    port map (
1253 
      C => clk,
1254 
      D => BU2_U0_srl_sig_16_10_76,
1255 
      R => sclr,
1256 
      Q => q_3(10)
1257 
    );
1258 
  BU2_U0_gen_output_regs_output_regs_fd_output_10 : FDR
1259 
    generic map(
1260 
      INIT => '0'
1261 
    )
1262 
    port map (
1263 
      C => clk,
1264 
      D => BU2_U0_srl_sig_16_9_75,
1265 
      R => sclr,
1266 
      Q => q_3(9)
1267 
    );
1268 
  BU2_U0_gen_output_regs_output_regs_fd_output_9 : FDR
1269 
    generic map(
1270 
      INIT => '0'
1271 
    )
1272 
    port map (
1273 
      C => clk,
1274 
      D => BU2_U0_srl_sig_16_8_74,
1275 
      R => sclr,
1276 
      Q => q_3(8)
1277 
    );
1278 
  BU2_U0_gen_output_regs_output_regs_fd_output_8 : FDR
1279 
    generic map(
1280 
      INIT => '0'
1281 
    )
1282 
    port map (
1283 
      C => clk,
1284 
      D => BU2_U0_srl_sig_16_7_73,
1285 
      R => sclr,
1286 
      Q => q_3(7)
1287 
    );
1288 
  BU2_U0_gen_output_regs_output_regs_fd_output_7 : FDR
1289 
    generic map(
1290 
      INIT => '0'
1291 
    )
1292 
    port map (
1293 
      C => clk,
1294 
      D => BU2_U0_srl_sig_16_6_72,
1295 
      R => sclr,
1296 
      Q => q_3(6)
1297 
    );
1298 
  BU2_U0_gen_output_regs_output_regs_fd_output_6 : FDR
1299 
    generic map(
1300 
      INIT => '0'
1301 
    )
1302 
    port map (
1303 
      C => clk,
1304 
      D => BU2_U0_srl_sig_16_5_71,
1305 
      R => sclr,
1306 
      Q => q_3(5)
1307 
    );
1308 
  BU2_U0_gen_output_regs_output_regs_fd_output_5 : FDR
1309 
    generic map(
1310 
      INIT => '0'
1311 
    )
1312 
    port map (
1313 
      C => clk,
1314 
      D => BU2_U0_srl_sig_16_4_70,
1315 
      R => sclr,
1316 
      Q => q_3(4)
1317 
    );
1318 
  BU2_U0_gen_output_regs_output_regs_fd_output_4 : FDR
1319 
    generic map(
1320 
      INIT => '0'
1321 
    )
1322 
    port map (
1323 
      C => clk,
1324 
      D => BU2_U0_srl_sig_16_3_69,
1325 
      R => sclr,
1326 
      Q => q_3(3)
1327 
    );
1328 
  BU2_U0_gen_output_regs_output_regs_fd_output_3 : FDR
1329 
    generic map(
1330 
      INIT => '0'
1331 
    )
1332 
    port map (
1333 
      C => clk,
1334 
      D => BU2_U0_srl_sig_16_2_68,
1335 
      R => sclr,
1336 
      Q => q_3(2)
1337 
    );
1338 
  BU2_U0_gen_output_regs_output_regs_fd_output_2 : FDR
1339 
    generic map(
1340 
      INIT => '0'
1341 
    )
1342 
    port map (
1343 
      C => clk,
1344 
      D => BU2_U0_srl_sig_16_1_67,
1345 
      R => sclr,
1346 
      Q => q_3(1)
1347 
    );
1348 
  BU2_U0_gen_output_regs_output_regs_fd_output_1 : FDR
1349 
    generic map(
1350 
      INIT => '0'
1351 
    )
1352 
    port map (
1353 
      C => clk,
1354 
      D => BU2_U0_srl_sig_16_0_66,
1355 
      R => sclr,
1356 
      Q => q_3(0)
1357 
    );
1358 
 
1359 
end STRUCTURE;
1360 
 
1361 
-- synthesis translate_on

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