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--------------------------------------------------------------------------------
-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: K.39
--  \   \         Application: netgen
--  /   /         Filename: reg_32b_1c.vhd
-- /___/   /\     Timestamp: Tue Jun 23 13:23:32 2009
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command      : -intstyle ise -w -sim -ofmt vhdl "C:\Documents and Settings\Administrator\Desktop\Felsenstein Coprocessor\Logarithm LUT based\HW Implementation\Coregen\tmp\_cg\reg_32b_1c.ngc" "C:\Documents and Settings\Administrator\Desktop\Felsenstein Coprocessor\Logarithm LUT based\HW Implementation\Coregen\tmp\_cg\reg_32b_1c.vhd" 
-- Device       : 5vsx95tff1136-2
-- Input file   : C:/Documents and Settings/Administrator/Desktop/Felsenstein Coprocessor/Logarithm LUT based/HW Implementation/Coregen/tmp/_cg/reg_32b_1c.ngc
-- Output file  : C:/Documents and Settings/Administrator/Desktop/Felsenstein Coprocessor/Logarithm LUT based/HW Implementation/Coregen/tmp/_cg/reg_32b_1c.vhd
-- # of Entities        : 1
-- Design Name  : reg_32b_1c
-- Xilinx       : C:\Xilinx\10.1\ISE
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Simulation Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------
 
 
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
 
entity reg_32b_1c is
  port (
    sclr : in STD_LOGIC := 'X';
    clk : in STD_LOGIC := 'X';
    d : in STD_LOGIC_VECTOR ( 31 downto 0 );
    q : out STD_LOGIC_VECTOR ( 31 downto 0 )
  );
end reg_32b_1c;
 
architecture STRUCTURE of reg_32b_1c is
  signal BU2_sset : STD_LOGIC;
  signal BU2_sinit : STD_LOGIC;
  signal BU2_ainit : STD_LOGIC;
  signal BU2_aclr : STD_LOGIC;
  signal BU2_ce : STD_LOGIC;
  signal BU2_aset : STD_LOGIC;
  signal NLW_VCC_P_UNCONNECTED : STD_LOGIC;
  signal NLW_GND_G_UNCONNECTED : STD_LOGIC;
  signal d_2 : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal q_3 : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal BU2_a : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
  d_2(31) <= d(31);
  d_2(30) <= d(30);
  d_2(29) <= d(29);
  d_2(28) <= d(28);
  d_2(27) <= d(27);
  d_2(26) <= d(26);
  d_2(25) <= d(25);
  d_2(24) <= d(24);
  d_2(23) <= d(23);
  d_2(22) <= d(22);
  d_2(21) <= d(21);
  d_2(20) <= d(20);
  d_2(19) <= d(19);
  d_2(18) <= d(18);
  d_2(17) <= d(17);
  d_2(16) <= d(16);
  d_2(15) <= d(15);
  d_2(14) <= d(14);
  d_2(13) <= d(13);
  d_2(12) <= d(12);
  d_2(11) <= d(11);
  d_2(10) <= d(10);
  d_2(9) <= d(9);
  d_2(8) <= d(8);
  d_2(7) <= d(7);
  d_2(6) <= d(6);
  d_2(5) <= d(5);
  d_2(4) <= d(4);
  d_2(3) <= d(3);
  d_2(2) <= d(2);
  d_2(1) <= d(1);
  d_2(0) <= d(0);
  q(31) <= q_3(31);
  q(30) <= q_3(30);
  q(29) <= q_3(29);
  q(28) <= q_3(28);
  q(27) <= q_3(27);
  q(26) <= q_3(26);
  q(25) <= q_3(25);
  q(24) <= q_3(24);
  q(23) <= q_3(23);
  q(22) <= q_3(22);
  q(21) <= q_3(21);
  q(20) <= q_3(20);
  q(19) <= q_3(19);
  q(18) <= q_3(18);
  q(17) <= q_3(17);
  q(16) <= q_3(16);
  q(15) <= q_3(15);
  q(14) <= q_3(14);
  q(13) <= q_3(13);
  q(12) <= q_3(12);
  q(11) <= q_3(11);
  q(10) <= q_3(10);
  q(9) <= q_3(9);
  q(8) <= q_3(8);
  q(7) <= q_3(7);
  q(6) <= q_3(6);
  q(5) <= q_3(5);
  q(4) <= q_3(4);
  q(3) <= q_3(3);
  q(2) <= q_3(2);
  q(1) <= q_3(1);
  q(0) <= q_3(0);
  VCC_0 : VCC
    port map (
      P => NLW_VCC_P_UNCONNECTED
    );
  GND_1 : GND
    port map (
      G => NLW_GND_G_UNCONNECTED
    );
  BU2_U0_gen_output_regs_output_regs_fd_output_32 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => d_2(31),
      R => sclr,
      Q => q_3(31)
    );
  BU2_U0_gen_output_regs_output_regs_fd_output_31 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => d_2(30),
      R => sclr,
      Q => q_3(30)
    );
  BU2_U0_gen_output_regs_output_regs_fd_output_30 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => d_2(29),
      R => sclr,
      Q => q_3(29)
    );
  BU2_U0_gen_output_regs_output_regs_fd_output_29 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => d_2(28),
      R => sclr,
      Q => q_3(28)
    );
  BU2_U0_gen_output_regs_output_regs_fd_output_28 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => d_2(27),
      R => sclr,
      Q => q_3(27)
    );
  BU2_U0_gen_output_regs_output_regs_fd_output_27 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => d_2(26),
      R => sclr,
      Q => q_3(26)
    );
  BU2_U0_gen_output_regs_output_regs_fd_output_26 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => d_2(25),
      R => sclr,
      Q => q_3(25)
    );
  BU2_U0_gen_output_regs_output_regs_fd_output_25 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => d_2(24),
      R => sclr,
      Q => q_3(24)
    );
  BU2_U0_gen_output_regs_output_regs_fd_output_24 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => d_2(23),
      R => sclr,
      Q => q_3(23)
    );
  BU2_U0_gen_output_regs_output_regs_fd_output_23 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => d_2(22),
      R => sclr,
      Q => q_3(22)
    );
  BU2_U0_gen_output_regs_output_regs_fd_output_22 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => d_2(21),
      R => sclr,
      Q => q_3(21)
    );
  BU2_U0_gen_output_regs_output_regs_fd_output_21 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => d_2(20),
      R => sclr,
      Q => q_3(20)
    );
  BU2_U0_gen_output_regs_output_regs_fd_output_20 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => d_2(19),
      R => sclr,
      Q => q_3(19)
    );
  BU2_U0_gen_output_regs_output_regs_fd_output_19 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => d_2(18),
      R => sclr,
      Q => q_3(18)
    );
  BU2_U0_gen_output_regs_output_regs_fd_output_18 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => d_2(17),
      R => sclr,
      Q => q_3(17)
    );
  BU2_U0_gen_output_regs_output_regs_fd_output_17 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => d_2(16),
      R => sclr,
      Q => q_3(16)
    );
  BU2_U0_gen_output_regs_output_regs_fd_output_16 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => d_2(15),
      R => sclr,
      Q => q_3(15)
    );
  BU2_U0_gen_output_regs_output_regs_fd_output_15 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => d_2(14),
      R => sclr,
      Q => q_3(14)
    );
  BU2_U0_gen_output_regs_output_regs_fd_output_14 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => d_2(13),
      R => sclr,
      Q => q_3(13)
    );
  BU2_U0_gen_output_regs_output_regs_fd_output_13 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => d_2(12),
      R => sclr,
      Q => q_3(12)
    );
  BU2_U0_gen_output_regs_output_regs_fd_output_12 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => d_2(11),
      R => sclr,
      Q => q_3(11)
    );
  BU2_U0_gen_output_regs_output_regs_fd_output_11 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => d_2(10),
      R => sclr,
      Q => q_3(10)
    );
  BU2_U0_gen_output_regs_output_regs_fd_output_10 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => d_2(9),
      R => sclr,
      Q => q_3(9)
    );
  BU2_U0_gen_output_regs_output_regs_fd_output_9 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => d_2(8),
      R => sclr,
      Q => q_3(8)
    );
  BU2_U0_gen_output_regs_output_regs_fd_output_8 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => d_2(7),
      R => sclr,
      Q => q_3(7)
    );
  BU2_U0_gen_output_regs_output_regs_fd_output_7 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => d_2(6),
      R => sclr,
      Q => q_3(6)
    );
  BU2_U0_gen_output_regs_output_regs_fd_output_6 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => d_2(5),
      R => sclr,
      Q => q_3(5)
    );
  BU2_U0_gen_output_regs_output_regs_fd_output_5 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => d_2(4),
      R => sclr,
      Q => q_3(4)
    );
  BU2_U0_gen_output_regs_output_regs_fd_output_4 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => d_2(3),
      R => sclr,
      Q => q_3(3)
    );
  BU2_U0_gen_output_regs_output_regs_fd_output_3 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => d_2(2),
      R => sclr,
      Q => q_3(2)
    );
  BU2_U0_gen_output_regs_output_regs_fd_output_2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => d_2(1),
      R => sclr,
      Q => q_3(1)
    );
  BU2_U0_gen_output_regs_output_regs_fd_output_1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => clk,
      D => d_2(0),
      R => sclr,
      Q => q_3(0)
    );
 
end STRUCTURE;
 
-- synthesis translate_on

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[/] [fp_log/] [trunk/] [LAU/] [Virtex 5/] [DP-LAU/] [reg_32b_1c.vhd] - Blame information for rev 3

Line No.	Rev	Author	Line
1	2	NikosAl	`--------------------------------------------------------------------------------`
2			`-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.`
3			`--------------------------------------------------------------------------------`
4			`-- ____ ____`
5			`-- / /\/ /`
6			`-- /___/ \ / Vendor: Xilinx`
7			`-- \ \ \/ Version: K.39`
8			`-- \ \ Application: netgen`
9			`-- / / Filename: reg_32b_1c.vhd`
10			`-- /___/ /\ Timestamp: Tue Jun 23 13:23:32 2009`
11			`-- \ \ / \`
12			`-- \___\/\___\`
13			`--`
14			`-- Command : -intstyle ise -w -sim -ofmt vhdl "C:\Documents and Settings\Administrator\Desktop\Felsenstein Coprocessor\Logarithm LUT based\HW Implementation\Coregen\tmp\_cg\reg_32b_1c.ngc" "C:\Documents and Settings\Administrator\Desktop\Felsenstein Coprocessor\Logarithm LUT based\HW Implementation\Coregen\tmp\_cg\reg_32b_1c.vhd"`
15			`-- Device : 5vsx95tff1136-2`
16			`-- Input file : C:/Documents and Settings/Administrator/Desktop/Felsenstein Coprocessor/Logarithm LUT based/HW Implementation/Coregen/tmp/_cg/reg_32b_1c.ngc`
17			`-- Output file : C:/Documents and Settings/Administrator/Desktop/Felsenstein Coprocessor/Logarithm LUT based/HW Implementation/Coregen/tmp/_cg/reg_32b_1c.vhd`
18			`-- # of Entities : 1`
19			`-- Design Name : reg_32b_1c`
20			`-- Xilinx : C:\Xilinx\10.1\ISE`
21			`--`
22			`-- Purpose:`
23			`-- This VHDL netlist is a verification model and uses simulation`
24			`-- primitives which may not represent the true implementation of the`
25			`-- device, however the netlist is functionally correct and should not`
26			`-- be modified. This file cannot be synthesized and should only be used`
27			`-- with supported simulation tools.`
28			`--`
29			`-- Reference:`
30			`-- Development System Reference Guide, Chapter 23`
31			`-- Synthesis and Simulation Design Guide, Chapter 6`
32			`--`
33			`--------------------------------------------------------------------------------`
34
35
36			`-- synthesis translate_off`
37			`library IEEE;`
38			`use IEEE.STD_LOGIC_1164.ALL;`
39			`library UNISIM;`
40			`use UNISIM.VCOMPONENTS.ALL;`
41			`use UNISIM.VPKG.ALL;`
42
43			`entity reg_32b_1c is`
44			`port (`
45			`sclr : in STD_LOGIC := 'X';`
46			`clk : in STD_LOGIC := 'X';`
47			`d : in STD_LOGIC_VECTOR ( 31 downto 0 );`
48			`q : out STD_LOGIC_VECTOR ( 31 downto 0 )`
49			`);`
50			`end reg_32b_1c;`
51
52			`architecture STRUCTURE of reg_32b_1c is`
53			`signal BU2_sset : STD_LOGIC;`
54			`signal BU2_sinit : STD_LOGIC;`
55			`signal BU2_ainit : STD_LOGIC;`
56			`signal BU2_aclr : STD_LOGIC;`
57			`signal BU2_ce : STD_LOGIC;`
58			`signal BU2_aset : STD_LOGIC;`
59			`signal NLW_VCC_P_UNCONNECTED : STD_LOGIC;`
60			`signal NLW_GND_G_UNCONNECTED : STD_LOGIC;`
61			`signal d_2 : STD_LOGIC_VECTOR ( 31 downto 0 );`
62			`signal q_3 : STD_LOGIC_VECTOR ( 31 downto 0 );`
63			`signal BU2_a : STD_LOGIC_VECTOR ( 3 downto 0 );`
64			`begin`
65			`d_2(31) <= d(31);`
66			`d_2(30) <= d(30);`
67			`d_2(29) <= d(29);`
68			`d_2(28) <= d(28);`
69			`d_2(27) <= d(27);`
70			`d_2(26) <= d(26);`
71			`d_2(25) <= d(25);`
72			`d_2(24) <= d(24);`
73			`d_2(23) <= d(23);`
74			`d_2(22) <= d(22);`
75			`d_2(21) <= d(21);`
76			`d_2(20) <= d(20);`
77			`d_2(19) <= d(19);`
78			`d_2(18) <= d(18);`
79			`d_2(17) <= d(17);`
80			`d_2(16) <= d(16);`
81			`d_2(15) <= d(15);`
82			`d_2(14) <= d(14);`
83			`d_2(13) <= d(13);`
84			`d_2(12) <= d(12);`
85			`d_2(11) <= d(11);`
86			`d_2(10) <= d(10);`
87			`d_2(9) <= d(9);`
88			`d_2(8) <= d(8);`
89			`d_2(7) <= d(7);`
90			`d_2(6) <= d(6);`
91			`d_2(5) <= d(5);`
92			`d_2(4) <= d(4);`
93			`d_2(3) <= d(3);`
94			`d_2(2) <= d(2);`
95			`d_2(1) <= d(1);`
96			`d_2(0) <= d(0);`
97			`q(31) <= q_3(31);`
98			`q(30) <= q_3(30);`
99			`q(29) <= q_3(29);`
100			`q(28) <= q_3(28);`
101			`q(27) <= q_3(27);`
102			`q(26) <= q_3(26);`
103			`q(25) <= q_3(25);`
104			`q(24) <= q_3(24);`
105			`q(23) <= q_3(23);`
106			`q(22) <= q_3(22);`
107			`q(21) <= q_3(21);`
108			`q(20) <= q_3(20);`
109			`q(19) <= q_3(19);`
110			`q(18) <= q_3(18);`
111			`q(17) <= q_3(17);`
112			`q(16) <= q_3(16);`
113			`q(15) <= q_3(15);`
114			`q(14) <= q_3(14);`
115			`q(13) <= q_3(13);`
116			`q(12) <= q_3(12);`
117			`q(11) <= q_3(11);`
118			`q(10) <= q_3(10);`
119			`q(9) <= q_3(9);`
120			`q(8) <= q_3(8);`
121			`q(7) <= q_3(7);`
122			`q(6) <= q_3(6);`
123			`q(5) <= q_3(5);`
124			`q(4) <= q_3(4);`
125			`q(3) <= q_3(3);`
126			`q(2) <= q_3(2);`
127			`q(1) <= q_3(1);`
128			`q(0) <= q_3(0);`
129			`VCC_0 : VCC`
130			`port map (`
131			`P => NLW_VCC_P_UNCONNECTED`
132			`);`
133			`GND_1 : GND`
134			`port map (`
135			`G => NLW_GND_G_UNCONNECTED`
136			`);`
137			`BU2_U0_gen_output_regs_output_regs_fd_output_32 : FDR`
138			`generic map(`
139			`INIT => '0'`
140			`)`
141			`port map (`
142			`C => clk,`
143			`D => d_2(31),`
144			`R => sclr,`
145			`Q => q_3(31)`
146			`);`
147			`BU2_U0_gen_output_regs_output_regs_fd_output_31 : FDR`
148			`generic map(`
149			`INIT => '0'`
150			`)`
151			`port map (`
152			`C => clk,`
153			`D => d_2(30),`
154			`R => sclr,`
155			`Q => q_3(30)`
156			`);`
157			`BU2_U0_gen_output_regs_output_regs_fd_output_30 : FDR`
158			`generic map(`
159			`INIT => '0'`
160			`)`
161			`port map (`
162			`C => clk,`
163			`D => d_2(29),`
164			`R => sclr,`
165			`Q => q_3(29)`
166			`);`
167			`BU2_U0_gen_output_regs_output_regs_fd_output_29 : FDR`
168			`generic map(`
169			`INIT => '0'`
170			`)`
171			`port map (`
172			`C => clk,`
173			`D => d_2(28),`
174			`R => sclr,`
175			`Q => q_3(28)`
176			`);`
177			`BU2_U0_gen_output_regs_output_regs_fd_output_28 : FDR`
178			`generic map(`
179			`INIT => '0'`
180			`)`
181			`port map (`
182			`C => clk,`
183			`D => d_2(27),`
184			`R => sclr,`
185			`Q => q_3(27)`
186			`);`
187			`BU2_U0_gen_output_regs_output_regs_fd_output_27 : FDR`
188			`generic map(`
189			`INIT => '0'`
190			`)`
191			`port map (`
192			`C => clk,`
193			`D => d_2(26),`
194			`R => sclr,`
195			`Q => q_3(26)`
196			`);`
197			`BU2_U0_gen_output_regs_output_regs_fd_output_26 : FDR`
198			`generic map(`
199			`INIT => '0'`
200			`)`
201			`port map (`
202			`C => clk,`
203			`D => d_2(25),`
204			`R => sclr,`
205			`Q => q_3(25)`
206			`);`
207			`BU2_U0_gen_output_regs_output_regs_fd_output_25 : FDR`
208			`generic map(`
209			`INIT => '0'`
210			`)`
211			`port map (`
212			`C => clk,`
213			`D => d_2(24),`
214			`R => sclr,`
215			`Q => q_3(24)`
216			`);`
217			`BU2_U0_gen_output_regs_output_regs_fd_output_24 : FDR`
218			`generic map(`
219			`INIT => '0'`
220			`)`
221			`port map (`
222			`C => clk,`
223			`D => d_2(23),`
224			`R => sclr,`
225			`Q => q_3(23)`
226			`);`
227			`BU2_U0_gen_output_regs_output_regs_fd_output_23 : FDR`
228			`generic map(`
229			`INIT => '0'`
230			`)`
231			`port map (`
232			`C => clk,`
233			`D => d_2(22),`
234			`R => sclr,`
235			`Q => q_3(22)`
236			`);`
237			`BU2_U0_gen_output_regs_output_regs_fd_output_22 : FDR`
238			`generic map(`
239			`INIT => '0'`
240			`)`
241			`port map (`
242			`C => clk,`
243			`D => d_2(21),`
244			`R => sclr,`
245			`Q => q_3(21)`
246			`);`
247			`BU2_U0_gen_output_regs_output_regs_fd_output_21 : FDR`
248			`generic map(`
249			`INIT => '0'`
250			`)`
251			`port map (`
252			`C => clk,`
253			`D => d_2(20),`
254			`R => sclr,`
255			`Q => q_3(20)`
256			`);`
257			`BU2_U0_gen_output_regs_output_regs_fd_output_20 : FDR`
258			`generic map(`
259			`INIT => '0'`
260			`)`
261			`port map (`
262			`C => clk,`
263			`D => d_2(19),`
264			`R => sclr,`
265			`Q => q_3(19)`
266			`);`
267			`BU2_U0_gen_output_regs_output_regs_fd_output_19 : FDR`
268			`generic map(`
269			`INIT => '0'`
270			`)`
271			`port map (`
272			`C => clk,`
273			`D => d_2(18),`
274			`R => sclr,`
275			`Q => q_3(18)`
276			`);`
277			`BU2_U0_gen_output_regs_output_regs_fd_output_18 : FDR`
278			`generic map(`
279			`INIT => '0'`
280			`)`
281			`port map (`
282			`C => clk,`
283			`D => d_2(17),`
284			`R => sclr,`
285			`Q => q_3(17)`
286			`);`
287			`BU2_U0_gen_output_regs_output_regs_fd_output_17 : FDR`
288			`generic map(`
289			`INIT => '0'`
290			`)`
291			`port map (`
292			`C => clk,`
293			`D => d_2(16),`
294			`R => sclr,`
295			`Q => q_3(16)`
296			`);`
297			`BU2_U0_gen_output_regs_output_regs_fd_output_16 : FDR`
298			`generic map(`
299			`INIT => '0'`
300			`)`
301			`port map (`
302			`C => clk,`
303			`D => d_2(15),`
304			`R => sclr,`
305			`Q => q_3(15)`
306			`);`
307			`BU2_U0_gen_output_regs_output_regs_fd_output_15 : FDR`
308			`generic map(`
309			`INIT => '0'`
310			`)`
311			`port map (`
312			`C => clk,`
313			`D => d_2(14),`
314			`R => sclr,`
315			`Q => q_3(14)`
316			`);`
317			`BU2_U0_gen_output_regs_output_regs_fd_output_14 : FDR`
318			`generic map(`
319			`INIT => '0'`
320			`)`
321			`port map (`
322			`C => clk,`
323			`D => d_2(13),`
324			`R => sclr,`
325			`Q => q_3(13)`
326			`);`
327			`BU2_U0_gen_output_regs_output_regs_fd_output_13 : FDR`
328			`generic map(`
329			`INIT => '0'`
330			`)`
331			`port map (`
332			`C => clk,`
333			`D => d_2(12),`
334			`R => sclr,`
335			`Q => q_3(12)`
336			`);`
337			`BU2_U0_gen_output_regs_output_regs_fd_output_12 : FDR`
338			`generic map(`
339			`INIT => '0'`
340			`)`
341			`port map (`
342			`C => clk,`
343			`D => d_2(11),`
344			`R => sclr,`
345			`Q => q_3(11)`
346			`);`
347			`BU2_U0_gen_output_regs_output_regs_fd_output_11 : FDR`
348			`generic map(`
349			`INIT => '0'`
350			`)`
351			`port map (`
352			`C => clk,`
353			`D => d_2(10),`
354			`R => sclr,`
355			`Q => q_3(10)`
356			`);`
357			`BU2_U0_gen_output_regs_output_regs_fd_output_10 : FDR`
358			`generic map(`
359			`INIT => '0'`
360			`)`
361			`port map (`
362			`C => clk,`
363			`D => d_2(9),`
364			`R => sclr,`
365			`Q => q_3(9)`
366			`);`
367			`BU2_U0_gen_output_regs_output_regs_fd_output_9 : FDR`
368			`generic map(`
369			`INIT => '0'`
370			`)`
371			`port map (`
372			`C => clk,`
373			`D => d_2(8),`
374			`R => sclr,`
375			`Q => q_3(8)`
376			`);`
377			`BU2_U0_gen_output_regs_output_regs_fd_output_8 : FDR`
378			`generic map(`
379			`INIT => '0'`
380			`)`
381			`port map (`
382			`C => clk,`
383			`D => d_2(7),`
384			`R => sclr,`
385			`Q => q_3(7)`
386			`);`
387			`BU2_U0_gen_output_regs_output_regs_fd_output_7 : FDR`
388			`generic map(`
389			`INIT => '0'`
390			`)`
391			`port map (`
392			`C => clk,`
393			`D => d_2(6),`
394			`R => sclr,`
395			`Q => q_3(6)`
396			`);`
397			`BU2_U0_gen_output_regs_output_regs_fd_output_6 : FDR`
398			`generic map(`
399			`INIT => '0'`
400			`)`
401			`port map (`
402			`C => clk,`
403			`D => d_2(5),`
404			`R => sclr,`
405			`Q => q_3(5)`
406			`);`
407			`BU2_U0_gen_output_regs_output_regs_fd_output_5 : FDR`
408			`generic map(`
409			`INIT => '0'`
410			`)`
411			`port map (`
412			`C => clk,`
413			`D => d_2(4),`
414			`R => sclr,`
415			`Q => q_3(4)`
416			`);`
417			`BU2_U0_gen_output_regs_output_regs_fd_output_4 : FDR`
418			`generic map(`
419			`INIT => '0'`
420			`)`
421			`port map (`
422			`C => clk,`
423			`D => d_2(3),`
424			`R => sclr,`
425			`Q => q_3(3)`
426			`);`
427			`BU2_U0_gen_output_regs_output_regs_fd_output_3 : FDR`
428			`generic map(`
429			`INIT => '0'`
430			`)`
431			`port map (`
432			`C => clk,`
433			`D => d_2(2),`
434			`R => sclr,`
435			`Q => q_3(2)`
436			`);`
437			`BU2_U0_gen_output_regs_output_regs_fd_output_2 : FDR`
438			`generic map(`
439			`INIT => '0'`
440			`)`
441			`port map (`
442			`C => clk,`
443			`D => d_2(1),`
444			`R => sclr,`
445			`Q => q_3(1)`
446			`);`
447			`BU2_U0_gen_output_regs_output_regs_fd_output_1 : FDR`
448			`generic map(`
449			`INIT => '0'`
450			`)`
451			`port map (`
452			`C => clk,`
453			`D => d_2(0),`
454			`R => sclr,`
455			`Q => q_3(0)`
456			`);`
457
458			`end STRUCTURE;`
459
460			`-- synthesis translate_on`