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#

# Xilinx Core Generator version K.39

# Date: Tue Jun 23 11:23:32 2009

#

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#

#  This file contains the customisation parameters for a

#  Xilinx CORE Generator IP GUI. It is strongly recommended

#  that you do not manually alter this file as it may cause

#  unexpected and unsupported behavior.

#

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#

# BEGIN Project Options

SET addpads = False

SET asysymbol = False

SET busformat = BusFormatAngleBracketNotRipped

SET createndf = False

SET designentry = VHDL

SET device = xc5vsx95t

SET devicefamily = virtex5

SET flowvendor = Other

SET formalverification = False

SET foundationsym = False

SET implementationfiletype = Ngc

SET package = ff1136

SET removerpms = False

SET simulationfiles = Structural

SET speedgrade = -2

SET verilogsim = False

SET vhdlsim = True

# END Project Options

# BEGIN Select

SELECT RAM-based_Shift_Register family Xilinx,_Inc. 9.0

# END Select

# BEGIN Parameters

CSET aclr=false

CSET ainit=false

CSET aset=false

CSET asyncinitradix=2

CSET asyncinitval=00000000000000000000000000000000

CSET ce=false

CSET cepriority=Sync_Overrides_CE

CSET component_name=reg_32b_1c

CSET defaultdata=00000000000000000000000000000000

CSET defaultdataradix=2

CSET depth=1

CSET meminitfile=no_coe_file_loaded

CSET optgoal=Resources

CSET readmiffile=false

CSET reglastbit=true

CSET sclr=true

CSET shiftregtype=Fixed_Length

CSET sinit=false

CSET sset=false

CSET syncctrlpriority=Reset_Overrides_Set

CSET syncinitradix=2

CSET syncinitval=00000000000000000000000000000000

CSET width=32

# END Parameters

GENERATE

# CRC: afea3c0a