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-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
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--------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ / Vendor: Xilinx
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-- \ \ \/ Version: K.39
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-- \ \ Application: netgen
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-- / / Filename: sp_fp_add.vhd
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-- /___/ /\ Timestamp: Tue Jun 23 11:26:56 2009
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-- \ \ / \
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-- \___\/\___\
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--
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-- Command : -intstyle ise -w -sim -ofmt vhdl "C:\Documents and Settings\Administrator\Desktop\Felsenstein Coprocessor\Logarithm LUT based\HW Implementation\Coregen\tmp\_cg\sp_fp_add.ngc" "C:\Documents and Settings\Administrator\Desktop\Felsenstein Coprocessor\Logarithm LUT based\HW Implementation\Coregen\tmp\_cg\sp_fp_add.vhd"
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-- Device : 5vsx95tff1136-1
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-- Input file : C:/Documents and Settings/Administrator/Desktop/Felsenstein Coprocessor/Logarithm LUT based/HW Implementation/Coregen/tmp/_cg/sp_fp_add.ngc
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-- Output file : C:/Documents and Settings/Administrator/Desktop/Felsenstein Coprocessor/Logarithm LUT based/HW Implementation/Coregen/tmp/_cg/sp_fp_add.vhd
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-- # of Entities : 1
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-- Design Name : sp_fp_add
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-- Xilinx : C:\Xilinx\10.1\ISE
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--
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-- Purpose:
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-- This VHDL netlist is a verification model and uses simulation
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-- primitives which may not represent the true implementation of the
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-- device, however the netlist is functionally correct and should not
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-- be modified. This file cannot be synthesized and should only be used
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-- with supported simulation tools.
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--
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-- Reference:
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-- Development System Reference Guide, Chapter 23
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-- Synthesis and Simulation Design Guide, Chapter 6
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--
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--------------------------------------------------------------------------------
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-- synthesis translate_off
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library UNISIM;
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use UNISIM.VCOMPONENTS.ALL;
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use UNISIM.VPKG.ALL;
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entity sp_fp_add is
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port (
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sclr : in STD_LOGIC := 'X';
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rdy : out STD_LOGIC;
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operation_nd : in STD_LOGIC := 'X';
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clk : in STD_LOGIC := 'X';
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a : in STD_LOGIC_VECTOR ( 31 downto 0 );
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b : in STD_LOGIC_VECTOR ( 31 downto 0 );
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result : out STD_LOGIC_VECTOR ( 31 downto 0 )
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);
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end sp_fp_add;
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architecture STRUCTURE of sp_fp_add is
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signal sig00000001 : STD_LOGIC;
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signal sig00000002 : STD_LOGIC;
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signal sig00000003 : STD_LOGIC;
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signal sig00000004 : STD_LOGIC;
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signal sig00000005 : STD_LOGIC;
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signal sig00000006 : STD_LOGIC;
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signal sig00000007 : STD_LOGIC;
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signal sig00000008 : STD_LOGIC;
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signal sig00000009 : STD_LOGIC;
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signal sig0000000a : STD_LOGIC;
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signal sig0000000b : STD_LOGIC;
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signal sig0000000c : STD_LOGIC;
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signal sig0000000d : STD_LOGIC;
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signal sig0000000e : STD_LOGIC;
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signal sig0000000f : STD_LOGIC;
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signal sig00000010 : STD_LOGIC;
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signal sig00000011 : STD_LOGIC;
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signal sig00000012 : STD_LOGIC;
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signal sig00000013 : STD_LOGIC;
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signal sig00000014 : STD_LOGIC;
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signal sig00000015 : STD_LOGIC;
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signal sig00000016 : STD_LOGIC;
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signal sig00000017 : STD_LOGIC;
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signal sig00000018 : STD_LOGIC;
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signal sig00000019 : STD_LOGIC;
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signal sig0000001a : STD_LOGIC;
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signal sig0000001b : STD_LOGIC;
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signal sig0000001c : STD_LOGIC;
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signal sig0000001d : STD_LOGIC;
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signal sig0000001e : STD_LOGIC;
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signal sig0000001f : STD_LOGIC;
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signal sig00000020 : STD_LOGIC;
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signal sig00000021 : STD_LOGIC;
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signal sig00000022 : STD_LOGIC;
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signal sig00000023 : STD_LOGIC;
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signal sig00000024 : STD_LOGIC;
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signal sig00000025 : STD_LOGIC;
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signal sig00000026 : STD_LOGIC;
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signal sig00000027 : STD_LOGIC;
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signal sig00000028 : STD_LOGIC;
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signal sig00000029 : STD_LOGIC;
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signal sig0000002a : STD_LOGIC;
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signal sig0000002b : STD_LOGIC;
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signal sig0000002c : STD_LOGIC;
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signal sig0000002d : STD_LOGIC;
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signal sig0000002e : STD_LOGIC;
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signal sig0000002f : STD_LOGIC;
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signal sig00000030 : STD_LOGIC;
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signal sig00000031 : STD_LOGIC;
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signal sig00000032 : STD_LOGIC;
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signal sig00000033 : STD_LOGIC;
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signal sig00000034 : STD_LOGIC;
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signal sig00000035 : STD_LOGIC;
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signal sig00000036 : STD_LOGIC;
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signal sig00000037 : STD_LOGIC;
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signal sig00000038 : STD_LOGIC;
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signal sig00000039 : STD_LOGIC;
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signal sig0000003a : STD_LOGIC;
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signal sig0000003b : STD_LOGIC;
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signal sig0000003c : STD_LOGIC;
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signal sig0000003d : STD_LOGIC;
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signal sig0000003e : STD_LOGIC;
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signal sig0000003f : STD_LOGIC;
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signal sig00000040 : STD_LOGIC;
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signal sig00000041 : STD_LOGIC;
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signal sig00000042 : STD_LOGIC;
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signal sig00000043 : STD_LOGIC;
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signal sig00000044 : STD_LOGIC;
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signal sig00000045 : STD_LOGIC;
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signal sig00000046 : STD_LOGIC;
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signal sig00000047 : STD_LOGIC;
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signal sig00000048 : STD_LOGIC;
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signal sig00000049 : STD_LOGIC;
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signal sig0000004a : STD_LOGIC;
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signal sig0000004b : STD_LOGIC;
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signal sig0000004c : STD_LOGIC;
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signal sig0000004d : STD_LOGIC;
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signal sig0000004e : STD_LOGIC;
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signal sig0000004f : STD_LOGIC;
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signal sig00000050 : STD_LOGIC;
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signal sig00000051 : STD_LOGIC;
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signal sig00000052 : STD_LOGIC;
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signal sig00000053 : STD_LOGIC;
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signal sig00000054 : STD_LOGIC;
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signal sig00000055 : STD_LOGIC;
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signal sig00000056 : STD_LOGIC;
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signal sig00000057 : STD_LOGIC;
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signal sig00000058 : STD_LOGIC;
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signal sig00000059 : STD_LOGIC;
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signal sig0000005a : STD_LOGIC;
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signal sig0000005b : STD_LOGIC;
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signal sig0000005c : STD_LOGIC;
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signal sig0000005d : STD_LOGIC;
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signal sig0000005e : STD_LOGIC;
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signal sig0000005f : STD_LOGIC;
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signal sig00000060 : STD_LOGIC;
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signal sig00000061 : STD_LOGIC;
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signal sig00000062 : STD_LOGIC;
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signal sig00000063 : STD_LOGIC;
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signal sig00000064 : STD_LOGIC;
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signal blk00000003_sig000003ac : STD_LOGIC;
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signal blk00000003_sig000003ab : STD_LOGIC;
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signal blk00000003_sig000003aa : STD_LOGIC;
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signal blk00000003_sig000003a9 : STD_LOGIC;
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signal blk00000003_sig000003a8 : STD_LOGIC;
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signal blk00000003_sig000003a7 : STD_LOGIC;
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signal blk00000003_sig000003a6 : STD_LOGIC;
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signal blk00000003_sig000003a5 : STD_LOGIC;
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signal blk00000003_sig000003a4 : STD_LOGIC;
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signal blk00000003_sig000003a3 : STD_LOGIC;
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signal blk00000003_sig000003a2 : STD_LOGIC;
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signal blk00000003_sig000003a1 : STD_LOGIC;
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signal blk00000003_sig000003a0 : STD_LOGIC;
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signal blk00000003_sig0000039f : STD_LOGIC;
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signal blk00000003_sig0000039e : STD_LOGIC;
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signal blk00000003_sig0000039d : STD_LOGIC;
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signal blk00000003_sig0000039c : STD_LOGIC;
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signal blk00000003_sig0000039b : STD_LOGIC;
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signal blk00000003_sig0000039a : STD_LOGIC;
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signal blk00000003_sig00000399 : STD_LOGIC;
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signal blk00000003_sig00000398 : STD_LOGIC;
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signal blk00000003_sig00000397 : STD_LOGIC;
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signal blk00000003_sig00000396 : STD_LOGIC;
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signal blk00000003_sig00000395 : STD_LOGIC;
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signal blk00000003_sig00000394 : STD_LOGIC;
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signal blk00000003_sig00000393 : STD_LOGIC;
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signal blk00000003_sig00000392 : STD_LOGIC;
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signal blk00000003_sig00000391 : STD_LOGIC;
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signal blk00000003_sig00000390 : STD_LOGIC;
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signal blk00000003_sig0000038f : STD_LOGIC;
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signal blk00000003_sig0000038e : STD_LOGIC;
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signal blk00000003_sig0000038d : STD_LOGIC;
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signal blk00000003_sig0000038c : STD_LOGIC;
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signal blk00000003_sig0000038b : STD_LOGIC;
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signal blk00000003_sig0000038a : STD_LOGIC;
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signal blk00000003_sig00000389 : STD_LOGIC;
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signal blk00000003_sig00000388 : STD_LOGIC;
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signal blk00000003_sig00000387 : STD_LOGIC;
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signal blk00000003_sig00000386 : STD_LOGIC;
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signal blk00000003_sig00000385 : STD_LOGIC;
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signal blk00000003_sig00000384 : STD_LOGIC;
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signal blk00000003_sig00000383 : STD_LOGIC;
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signal blk00000003_sig00000382 : STD_LOGIC;
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signal blk00000003_sig00000381 : STD_LOGIC;
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signal blk00000003_sig00000380 : STD_LOGIC;
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signal blk00000003_sig0000037f : STD_LOGIC;
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signal blk00000003_sig0000037e : STD_LOGIC;
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signal blk00000003_sig0000037d : STD_LOGIC;
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signal blk00000003_sig0000037c : STD_LOGIC;
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signal blk00000003_sig0000037b : STD_LOGIC;
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signal blk00000003_sig0000037a : STD_LOGIC;
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signal blk00000003_sig00000379 : STD_LOGIC;
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signal blk00000003_sig00000378 : STD_LOGIC;
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signal blk00000003_sig00000377 : STD_LOGIC;
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signal blk00000003_sig00000376 : STD_LOGIC;
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signal blk00000003_sig00000375 : STD_LOGIC;
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signal blk00000003_sig00000374 : STD_LOGIC;
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signal blk00000003_sig00000373 : STD_LOGIC;
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signal blk00000003_sig00000372 : STD_LOGIC;
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signal blk00000003_sig00000371 : STD_LOGIC;
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signal blk00000003_sig00000370 : STD_LOGIC;
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signal blk00000003_sig0000036f : STD_LOGIC;
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signal blk00000003_sig0000036e : STD_LOGIC;
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signal blk00000003_sig0000036d : STD_LOGIC;
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signal blk00000003_sig0000036c : STD_LOGIC;
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signal blk00000003_sig0000036b : STD_LOGIC;
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signal blk00000003_sig0000036a : STD_LOGIC;
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signal blk00000003_sig00000369 : STD_LOGIC;
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signal blk00000003_sig00000368 : STD_LOGIC;
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signal blk00000003_sig00000367 : STD_LOGIC;
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signal blk00000003_sig00000366 : STD_LOGIC;
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signal blk00000003_sig00000365 : STD_LOGIC;
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signal blk00000003_sig00000364 : STD_LOGIC;
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signal blk00000003_sig00000363 : STD_LOGIC;
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signal blk00000003_sig00000362 : STD_LOGIC;
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signal blk00000003_sig00000361 : STD_LOGIC;
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signal blk00000003_sig00000360 : STD_LOGIC;
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signal blk00000003_sig0000035f : STD_LOGIC;
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signal blk00000003_sig0000035e : STD_LOGIC;
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signal blk00000003_sig0000035d : STD_LOGIC;
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signal blk00000003_sig0000035c : STD_LOGIC;
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signal blk00000003_sig0000035b : STD_LOGIC;
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signal blk00000003_sig0000035a : STD_LOGIC;
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signal blk00000003_sig00000359 : STD_LOGIC;
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signal blk00000003_sig00000358 : STD_LOGIC;
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signal blk00000003_sig00000357 : STD_LOGIC;
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signal blk00000003_sig00000356 : STD_LOGIC;
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signal blk00000003_sig00000355 : STD_LOGIC;
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signal blk00000003_sig00000354 : STD_LOGIC;
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signal blk00000003_sig00000353 : STD_LOGIC;
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signal blk00000003_sig00000352 : STD_LOGIC;
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signal blk00000003_sig00000351 : STD_LOGIC;
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signal blk00000003_sig00000350 : STD_LOGIC;
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signal blk00000003_sig0000034f : STD_LOGIC;
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signal blk00000003_sig0000034e : STD_LOGIC;
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signal blk00000003_sig0000034d : STD_LOGIC;
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signal blk00000003_sig0000034c : STD_LOGIC;
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signal blk00000003_sig0000034b : STD_LOGIC;
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signal blk00000003_sig0000034a : STD_LOGIC;
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signal blk00000003_sig00000349 : STD_LOGIC;
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signal blk00000003_sig00000348 : STD_LOGIC;
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signal blk00000003_sig00000347 : STD_LOGIC;
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signal blk00000003_sig00000346 : STD_LOGIC;
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signal blk00000003_sig00000345 : STD_LOGIC;
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signal blk00000003_sig00000344 : STD_LOGIC;
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signal blk00000003_sig00000343 : STD_LOGIC;
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signal blk00000003_sig00000342 : STD_LOGIC;
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signal blk00000003_sig00000341 : STD_LOGIC;
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signal blk00000003_sig00000340 : STD_LOGIC;
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signal blk00000003_sig0000033f : STD_LOGIC;
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signal blk00000003_sig0000033e : STD_LOGIC;
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signal blk00000003_sig0000033d : STD_LOGIC;
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signal blk00000003_sig0000033c : STD_LOGIC;
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signal blk00000003_sig0000033b : STD_LOGIC;
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signal blk00000003_sig0000033a : STD_LOGIC;
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signal blk00000003_sig00000339 : STD_LOGIC;
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signal blk00000003_sig00000338 : STD_LOGIC;
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signal blk00000003_sig00000337 : STD_LOGIC;
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signal blk00000003_sig00000336 : STD_LOGIC;
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signal blk00000003_sig00000335 : STD_LOGIC;
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signal blk00000003_sig00000334 : STD_LOGIC;
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signal blk00000003_sig00000333 : STD_LOGIC;
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signal blk00000003_sig00000332 : STD_LOGIC;
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signal blk00000003_sig00000331 : STD_LOGIC;
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signal blk00000003_sig00000330 : STD_LOGIC;
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signal blk00000003_sig0000032f : STD_LOGIC;
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signal blk00000003_sig0000032e : STD_LOGIC;
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signal blk00000003_sig0000032d : STD_LOGIC;
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signal blk00000003_sig0000032c : STD_LOGIC;
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285 |
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signal blk00000003_sig0000032b : STD_LOGIC;
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286 |
|
|
signal blk00000003_sig0000032a : STD_LOGIC;
|
287 |
|
|
signal blk00000003_sig00000329 : STD_LOGIC;
|
288 |
|
|
signal blk00000003_sig00000328 : STD_LOGIC;
|
289 |
|
|
signal blk00000003_sig00000327 : STD_LOGIC;
|
290 |
|
|
signal blk00000003_sig00000326 : STD_LOGIC;
|
291 |
|
|
signal blk00000003_sig00000325 : STD_LOGIC;
|
292 |
|
|
signal blk00000003_sig00000324 : STD_LOGIC;
|
293 |
|
|
signal blk00000003_sig00000323 : STD_LOGIC;
|
294 |
|
|
signal blk00000003_sig00000322 : STD_LOGIC;
|
295 |
|
|
signal blk00000003_sig00000321 : STD_LOGIC;
|
296 |
|
|
signal blk00000003_sig00000320 : STD_LOGIC;
|
297 |
|
|
signal blk00000003_sig0000031f : STD_LOGIC;
|
298 |
|
|
signal blk00000003_sig0000031e : STD_LOGIC;
|
299 |
|
|
signal blk00000003_sig0000031d : STD_LOGIC;
|
300 |
|
|
signal blk00000003_sig0000031c : STD_LOGIC;
|
301 |
|
|
signal blk00000003_sig0000031b : STD_LOGIC;
|
302 |
|
|
signal blk00000003_sig0000031a : STD_LOGIC;
|
303 |
|
|
signal blk00000003_sig00000319 : STD_LOGIC;
|
304 |
|
|
signal blk00000003_sig00000318 : STD_LOGIC;
|
305 |
|
|
signal blk00000003_sig00000317 : STD_LOGIC;
|
306 |
|
|
signal blk00000003_sig00000316 : STD_LOGIC;
|
307 |
|
|
signal blk00000003_sig00000315 : STD_LOGIC;
|
308 |
|
|
signal blk00000003_sig00000314 : STD_LOGIC;
|
309 |
|
|
signal blk00000003_sig00000313 : STD_LOGIC;
|
310 |
|
|
signal blk00000003_sig00000312 : STD_LOGIC;
|
311 |
|
|
signal blk00000003_sig00000311 : STD_LOGIC;
|
312 |
|
|
signal blk00000003_sig00000310 : STD_LOGIC;
|
313 |
|
|
signal blk00000003_sig0000030f : STD_LOGIC;
|
314 |
|
|
signal blk00000003_sig0000030e : STD_LOGIC;
|
315 |
|
|
signal blk00000003_sig0000030d : STD_LOGIC;
|
316 |
|
|
signal blk00000003_sig0000030c : STD_LOGIC;
|
317 |
|
|
signal blk00000003_sig0000030b : STD_LOGIC;
|
318 |
|
|
signal blk00000003_sig0000030a : STD_LOGIC;
|
319 |
|
|
signal blk00000003_sig00000309 : STD_LOGIC;
|
320 |
|
|
signal blk00000003_sig00000308 : STD_LOGIC;
|
321 |
|
|
signal blk00000003_sig00000307 : STD_LOGIC;
|
322 |
|
|
signal blk00000003_sig00000306 : STD_LOGIC;
|
323 |
|
|
signal blk00000003_sig00000305 : STD_LOGIC;
|
324 |
|
|
signal blk00000003_sig00000304 : STD_LOGIC;
|
325 |
|
|
signal blk00000003_sig00000303 : STD_LOGIC;
|
326 |
|
|
signal blk00000003_sig00000302 : STD_LOGIC;
|
327 |
|
|
signal blk00000003_sig00000301 : STD_LOGIC;
|
328 |
|
|
signal blk00000003_sig00000300 : STD_LOGIC;
|
329 |
|
|
signal blk00000003_sig000002ff : STD_LOGIC;
|
330 |
|
|
signal blk00000003_sig000002fe : STD_LOGIC;
|
331 |
|
|
signal blk00000003_sig000002fd : STD_LOGIC;
|
332 |
|
|
signal blk00000003_sig000002fc : STD_LOGIC;
|
333 |
|
|
signal blk00000003_sig000002fb : STD_LOGIC;
|
334 |
|
|
signal blk00000003_sig000002fa : STD_LOGIC;
|
335 |
|
|
signal blk00000003_sig000002f9 : STD_LOGIC;
|
336 |
|
|
signal blk00000003_sig000002f8 : STD_LOGIC;
|
337 |
|
|
signal blk00000003_sig000002f7 : STD_LOGIC;
|
338 |
|
|
signal blk00000003_sig000002f6 : STD_LOGIC;
|
339 |
|
|
signal blk00000003_sig000002f5 : STD_LOGIC;
|
340 |
|
|
signal blk00000003_sig000002f4 : STD_LOGIC;
|
341 |
|
|
signal blk00000003_sig000002f3 : STD_LOGIC;
|
342 |
|
|
signal blk00000003_sig000002f2 : STD_LOGIC;
|
343 |
|
|
signal blk00000003_sig000002f1 : STD_LOGIC;
|
344 |
|
|
signal blk00000003_sig000002f0 : STD_LOGIC;
|
345 |
|
|
signal blk00000003_sig000002ef : STD_LOGIC;
|
346 |
|
|
signal blk00000003_sig000002ee : STD_LOGIC;
|
347 |
|
|
signal blk00000003_sig000002ed : STD_LOGIC;
|
348 |
|
|
signal blk00000003_sig000002ec : STD_LOGIC;
|
349 |
|
|
signal blk00000003_sig000002eb : STD_LOGIC;
|
350 |
|
|
signal blk00000003_sig000002ea : STD_LOGIC;
|
351 |
|
|
signal blk00000003_sig000002e9 : STD_LOGIC;
|
352 |
|
|
signal blk00000003_sig000002e8 : STD_LOGIC;
|
353 |
|
|
signal blk00000003_sig000002e7 : STD_LOGIC;
|
354 |
|
|
signal blk00000003_sig000002e6 : STD_LOGIC;
|
355 |
|
|
signal blk00000003_sig000002e5 : STD_LOGIC;
|
356 |
|
|
signal blk00000003_sig000002e4 : STD_LOGIC;
|
357 |
|
|
signal blk00000003_sig000002e3 : STD_LOGIC;
|
358 |
|
|
signal blk00000003_sig000002e2 : STD_LOGIC;
|
359 |
|
|
signal blk00000003_sig000002e1 : STD_LOGIC;
|
360 |
|
|
signal blk00000003_sig000002e0 : STD_LOGIC;
|
361 |
|
|
signal blk00000003_sig000002df : STD_LOGIC;
|
362 |
|
|
signal blk00000003_sig000002de : STD_LOGIC;
|
363 |
|
|
signal blk00000003_sig000002dd : STD_LOGIC;
|
364 |
|
|
signal blk00000003_sig000002dc : STD_LOGIC;
|
365 |
|
|
signal blk00000003_sig000002db : STD_LOGIC;
|
366 |
|
|
signal blk00000003_sig000002da : STD_LOGIC;
|
367 |
|
|
signal blk00000003_sig000002d9 : STD_LOGIC;
|
368 |
|
|
signal blk00000003_sig000002d8 : STD_LOGIC;
|
369 |
|
|
signal blk00000003_sig000002d7 : STD_LOGIC;
|
370 |
|
|
signal blk00000003_sig000002d6 : STD_LOGIC;
|
371 |
|
|
signal blk00000003_sig000002d5 : STD_LOGIC;
|
372 |
|
|
signal blk00000003_sig000002d4 : STD_LOGIC;
|
373 |
|
|
signal blk00000003_sig000002d3 : STD_LOGIC;
|
374 |
|
|
signal blk00000003_sig000002d2 : STD_LOGIC;
|
375 |
|
|
signal blk00000003_sig000002d1 : STD_LOGIC;
|
376 |
|
|
signal blk00000003_sig000002d0 : STD_LOGIC;
|
377 |
|
|
signal blk00000003_sig000002cf : STD_LOGIC;
|
378 |
|
|
signal blk00000003_sig000002ce : STD_LOGIC;
|
379 |
|
|
signal blk00000003_sig000002cd : STD_LOGIC;
|
380 |
|
|
signal blk00000003_sig000002cc : STD_LOGIC;
|
381 |
|
|
signal blk00000003_sig000002cb : STD_LOGIC;
|
382 |
|
|
signal blk00000003_sig000002ca : STD_LOGIC;
|
383 |
|
|
signal blk00000003_sig000002c9 : STD_LOGIC;
|
384 |
|
|
signal blk00000003_sig000002c8 : STD_LOGIC;
|
385 |
|
|
signal blk00000003_sig000002c7 : STD_LOGIC;
|
386 |
|
|
signal blk00000003_sig000002c6 : STD_LOGIC;
|
387 |
|
|
signal blk00000003_sig000002c5 : STD_LOGIC;
|
388 |
|
|
signal blk00000003_sig000002c4 : STD_LOGIC;
|
389 |
|
|
signal blk00000003_sig000002c3 : STD_LOGIC;
|
390 |
|
|
signal blk00000003_sig000002c2 : STD_LOGIC;
|
391 |
|
|
signal blk00000003_sig000002c1 : STD_LOGIC;
|
392 |
|
|
signal blk00000003_sig000002c0 : STD_LOGIC;
|
393 |
|
|
signal blk00000003_sig000002bf : STD_LOGIC;
|
394 |
|
|
signal blk00000003_sig000002be : STD_LOGIC;
|
395 |
|
|
signal blk00000003_sig000002bd : STD_LOGIC;
|
396 |
|
|
signal blk00000003_sig000002bc : STD_LOGIC;
|
397 |
|
|
signal blk00000003_sig000002bb : STD_LOGIC;
|
398 |
|
|
signal blk00000003_sig000002ba : STD_LOGIC;
|
399 |
|
|
signal blk00000003_sig000002b9 : STD_LOGIC;
|
400 |
|
|
signal blk00000003_sig000002b8 : STD_LOGIC;
|
401 |
|
|
signal blk00000003_sig000002b7 : STD_LOGIC;
|
402 |
|
|
signal blk00000003_sig000002b6 : STD_LOGIC;
|
403 |
|
|
signal blk00000003_sig000002b5 : STD_LOGIC;
|
404 |
|
|
signal blk00000003_sig000002b4 : STD_LOGIC;
|
405 |
|
|
signal blk00000003_sig000002b3 : STD_LOGIC;
|
406 |
|
|
signal blk00000003_sig000002b2 : STD_LOGIC;
|
407 |
|
|
signal blk00000003_sig000002b1 : STD_LOGIC;
|
408 |
|
|
signal blk00000003_sig000002b0 : STD_LOGIC;
|
409 |
|
|
signal blk00000003_sig000002af : STD_LOGIC;
|
410 |
|
|
signal blk00000003_sig000002ae : STD_LOGIC;
|
411 |
|
|
signal blk00000003_sig000002ad : STD_LOGIC;
|
412 |
|
|
signal blk00000003_sig000002ac : STD_LOGIC;
|
413 |
|
|
signal blk00000003_sig000002ab : STD_LOGIC;
|
414 |
|
|
signal blk00000003_sig000002aa : STD_LOGIC;
|
415 |
|
|
signal blk00000003_sig000002a9 : STD_LOGIC;
|
416 |
|
|
signal blk00000003_sig000002a8 : STD_LOGIC;
|
417 |
|
|
signal blk00000003_sig000002a7 : STD_LOGIC;
|
418 |
|
|
signal blk00000003_sig000002a6 : STD_LOGIC;
|
419 |
|
|
signal blk00000003_sig000002a5 : STD_LOGIC;
|
420 |
|
|
signal blk00000003_sig000002a4 : STD_LOGIC;
|
421 |
|
|
signal blk00000003_sig000002a3 : STD_LOGIC;
|
422 |
|
|
signal blk00000003_sig000002a2 : STD_LOGIC;
|
423 |
|
|
signal blk00000003_sig000002a1 : STD_LOGIC;
|
424 |
|
|
signal blk00000003_sig000002a0 : STD_LOGIC;
|
425 |
|
|
signal blk00000003_sig0000029f : STD_LOGIC;
|
426 |
|
|
signal blk00000003_sig0000029e : STD_LOGIC;
|
427 |
|
|
signal blk00000003_sig0000029d : STD_LOGIC;
|
428 |
|
|
signal blk00000003_sig0000029c : STD_LOGIC;
|
429 |
|
|
signal blk00000003_sig0000029b : STD_LOGIC;
|
430 |
|
|
signal blk00000003_sig0000029a : STD_LOGIC;
|
431 |
|
|
signal blk00000003_sig00000299 : STD_LOGIC;
|
432 |
|
|
signal blk00000003_sig00000298 : STD_LOGIC;
|
433 |
|
|
signal blk00000003_sig00000297 : STD_LOGIC;
|
434 |
|
|
signal blk00000003_sig00000296 : STD_LOGIC;
|
435 |
|
|
signal blk00000003_sig00000295 : STD_LOGIC;
|
436 |
|
|
signal blk00000003_sig00000294 : STD_LOGIC;
|
437 |
|
|
signal blk00000003_sig00000293 : STD_LOGIC;
|
438 |
|
|
signal blk00000003_sig00000292 : STD_LOGIC;
|
439 |
|
|
signal blk00000003_sig00000291 : STD_LOGIC;
|
440 |
|
|
signal blk00000003_sig00000290 : STD_LOGIC;
|
441 |
|
|
signal blk00000003_sig0000028f : STD_LOGIC;
|
442 |
|
|
signal blk00000003_sig0000028e : STD_LOGIC;
|
443 |
|
|
signal blk00000003_sig0000028d : STD_LOGIC;
|
444 |
|
|
signal blk00000003_sig0000028c : STD_LOGIC;
|
445 |
|
|
signal blk00000003_sig0000028b : STD_LOGIC;
|
446 |
|
|
signal blk00000003_sig0000028a : STD_LOGIC;
|
447 |
|
|
signal blk00000003_sig00000289 : STD_LOGIC;
|
448 |
|
|
signal blk00000003_sig00000288 : STD_LOGIC;
|
449 |
|
|
signal blk00000003_sig00000287 : STD_LOGIC;
|
450 |
|
|
signal blk00000003_sig00000286 : STD_LOGIC;
|
451 |
|
|
signal blk00000003_sig00000285 : STD_LOGIC;
|
452 |
|
|
signal blk00000003_sig00000284 : STD_LOGIC;
|
453 |
|
|
signal blk00000003_sig00000283 : STD_LOGIC;
|
454 |
|
|
signal blk00000003_sig00000282 : STD_LOGIC;
|
455 |
|
|
signal blk00000003_sig00000281 : STD_LOGIC;
|
456 |
|
|
signal blk00000003_sig00000280 : STD_LOGIC;
|
457 |
|
|
signal blk00000003_sig0000027f : STD_LOGIC;
|
458 |
|
|
signal blk00000003_sig0000027e : STD_LOGIC;
|
459 |
|
|
signal blk00000003_sig0000027d : STD_LOGIC;
|
460 |
|
|
signal blk00000003_sig0000027c : STD_LOGIC;
|
461 |
|
|
signal blk00000003_sig0000027b : STD_LOGIC;
|
462 |
|
|
signal blk00000003_sig0000027a : STD_LOGIC;
|
463 |
|
|
signal blk00000003_sig00000279 : STD_LOGIC;
|
464 |
|
|
signal blk00000003_sig00000278 : STD_LOGIC;
|
465 |
|
|
signal blk00000003_sig00000277 : STD_LOGIC;
|
466 |
|
|
signal blk00000003_sig00000276 : STD_LOGIC;
|
467 |
|
|
signal blk00000003_sig00000275 : STD_LOGIC;
|
468 |
|
|
signal blk00000003_sig00000274 : STD_LOGIC;
|
469 |
|
|
signal blk00000003_sig00000273 : STD_LOGIC;
|
470 |
|
|
signal blk00000003_sig00000272 : STD_LOGIC;
|
471 |
|
|
signal blk00000003_sig00000271 : STD_LOGIC;
|
472 |
|
|
signal blk00000003_sig00000270 : STD_LOGIC;
|
473 |
|
|
signal blk00000003_sig0000026f : STD_LOGIC;
|
474 |
|
|
signal blk00000003_sig0000026e : STD_LOGIC;
|
475 |
|
|
signal blk00000003_sig0000026d : STD_LOGIC;
|
476 |
|
|
signal blk00000003_sig0000026c : STD_LOGIC;
|
477 |
|
|
signal blk00000003_sig0000026b : STD_LOGIC;
|
478 |
|
|
signal blk00000003_sig0000026a : STD_LOGIC;
|
479 |
|
|
signal blk00000003_sig00000269 : STD_LOGIC;
|
480 |
|
|
signal blk00000003_sig00000268 : STD_LOGIC;
|
481 |
|
|
signal blk00000003_sig00000267 : STD_LOGIC;
|
482 |
|
|
signal blk00000003_sig00000266 : STD_LOGIC;
|
483 |
|
|
signal blk00000003_sig00000265 : STD_LOGIC;
|
484 |
|
|
signal blk00000003_sig00000264 : STD_LOGIC;
|
485 |
|
|
signal blk00000003_sig00000263 : STD_LOGIC;
|
486 |
|
|
signal blk00000003_sig00000262 : STD_LOGIC;
|
487 |
|
|
signal blk00000003_sig00000261 : STD_LOGIC;
|
488 |
|
|
signal blk00000003_sig00000260 : STD_LOGIC;
|
489 |
|
|
signal blk00000003_sig0000025f : STD_LOGIC;
|
490 |
|
|
signal blk00000003_sig0000025e : STD_LOGIC;
|
491 |
|
|
signal blk00000003_sig0000025d : STD_LOGIC;
|
492 |
|
|
signal blk00000003_sig0000025c : STD_LOGIC;
|
493 |
|
|
signal blk00000003_sig0000025b : STD_LOGIC;
|
494 |
|
|
signal blk00000003_sig0000025a : STD_LOGIC;
|
495 |
|
|
signal blk00000003_sig00000259 : STD_LOGIC;
|
496 |
|
|
signal blk00000003_sig00000258 : STD_LOGIC;
|
497 |
|
|
signal blk00000003_sig00000257 : STD_LOGIC;
|
498 |
|
|
signal blk00000003_sig00000256 : STD_LOGIC;
|
499 |
|
|
signal blk00000003_sig00000255 : STD_LOGIC;
|
500 |
|
|
signal blk00000003_sig00000254 : STD_LOGIC;
|
501 |
|
|
signal blk00000003_sig00000253 : STD_LOGIC;
|
502 |
|
|
signal blk00000003_sig00000252 : STD_LOGIC;
|
503 |
|
|
signal blk00000003_sig00000251 : STD_LOGIC;
|
504 |
|
|
signal blk00000003_sig00000250 : STD_LOGIC;
|
505 |
|
|
signal blk00000003_sig0000024f : STD_LOGIC;
|
506 |
|
|
signal blk00000003_sig0000024e : STD_LOGIC;
|
507 |
|
|
signal blk00000003_sig0000024d : STD_LOGIC;
|
508 |
|
|
signal blk00000003_sig0000024c : STD_LOGIC;
|
509 |
|
|
signal blk00000003_sig0000024b : STD_LOGIC;
|
510 |
|
|
signal blk00000003_sig0000024a : STD_LOGIC;
|
511 |
|
|
signal blk00000003_sig00000249 : STD_LOGIC;
|
512 |
|
|
signal blk00000003_sig00000248 : STD_LOGIC;
|
513 |
|
|
signal blk00000003_sig00000247 : STD_LOGIC;
|
514 |
|
|
signal blk00000003_sig00000246 : STD_LOGIC;
|
515 |
|
|
signal blk00000003_sig00000245 : STD_LOGIC;
|
516 |
|
|
signal blk00000003_sig00000244 : STD_LOGIC;
|
517 |
|
|
signal blk00000003_sig00000243 : STD_LOGIC;
|
518 |
|
|
signal blk00000003_sig00000242 : STD_LOGIC;
|
519 |
|
|
signal blk00000003_sig00000241 : STD_LOGIC;
|
520 |
|
|
signal blk00000003_sig00000240 : STD_LOGIC;
|
521 |
|
|
signal blk00000003_sig0000023f : STD_LOGIC;
|
522 |
|
|
signal blk00000003_sig0000023e : STD_LOGIC;
|
523 |
|
|
signal blk00000003_sig0000023d : STD_LOGIC;
|
524 |
|
|
signal blk00000003_sig0000023c : STD_LOGIC;
|
525 |
|
|
signal blk00000003_sig0000023b : STD_LOGIC;
|
526 |
|
|
signal blk00000003_sig0000023a : STD_LOGIC;
|
527 |
|
|
signal blk00000003_sig00000239 : STD_LOGIC;
|
528 |
|
|
signal blk00000003_sig00000238 : STD_LOGIC;
|
529 |
|
|
signal blk00000003_sig00000237 : STD_LOGIC;
|
530 |
|
|
signal blk00000003_sig00000236 : STD_LOGIC;
|
531 |
|
|
signal blk00000003_sig00000235 : STD_LOGIC;
|
532 |
|
|
signal blk00000003_sig00000234 : STD_LOGIC;
|
533 |
|
|
signal blk00000003_sig00000233 : STD_LOGIC;
|
534 |
|
|
signal blk00000003_sig00000232 : STD_LOGIC;
|
535 |
|
|
signal blk00000003_sig00000231 : STD_LOGIC;
|
536 |
|
|
signal blk00000003_sig00000230 : STD_LOGIC;
|
537 |
|
|
signal blk00000003_sig0000022f : STD_LOGIC;
|
538 |
|
|
signal blk00000003_sig0000022e : STD_LOGIC;
|
539 |
|
|
signal blk00000003_sig0000022d : STD_LOGIC;
|
540 |
|
|
signal blk00000003_sig0000022c : STD_LOGIC;
|
541 |
|
|
signal blk00000003_sig0000022b : STD_LOGIC;
|
542 |
|
|
signal blk00000003_sig0000022a : STD_LOGIC;
|
543 |
|
|
signal blk00000003_sig00000229 : STD_LOGIC;
|
544 |
|
|
signal blk00000003_sig00000228 : STD_LOGIC;
|
545 |
|
|
signal blk00000003_sig00000227 : STD_LOGIC;
|
546 |
|
|
signal blk00000003_sig00000226 : STD_LOGIC;
|
547 |
|
|
signal blk00000003_sig00000225 : STD_LOGIC;
|
548 |
|
|
signal blk00000003_sig00000224 : STD_LOGIC;
|
549 |
|
|
signal blk00000003_sig00000223 : STD_LOGIC;
|
550 |
|
|
signal blk00000003_sig00000222 : STD_LOGIC;
|
551 |
|
|
signal blk00000003_sig00000221 : STD_LOGIC;
|
552 |
|
|
signal blk00000003_sig00000220 : STD_LOGIC;
|
553 |
|
|
signal blk00000003_sig0000021f : STD_LOGIC;
|
554 |
|
|
signal blk00000003_sig0000021e : STD_LOGIC;
|
555 |
|
|
signal blk00000003_sig0000021d : STD_LOGIC;
|
556 |
|
|
signal blk00000003_sig0000021c : STD_LOGIC;
|
557 |
|
|
signal blk00000003_sig0000021b : STD_LOGIC;
|
558 |
|
|
signal blk00000003_sig0000021a : STD_LOGIC;
|
559 |
|
|
signal blk00000003_sig00000219 : STD_LOGIC;
|
560 |
|
|
signal blk00000003_sig00000218 : STD_LOGIC;
|
561 |
|
|
signal blk00000003_sig00000217 : STD_LOGIC;
|
562 |
|
|
signal blk00000003_sig00000216 : STD_LOGIC;
|
563 |
|
|
signal blk00000003_sig00000215 : STD_LOGIC;
|
564 |
|
|
signal blk00000003_sig00000214 : STD_LOGIC;
|
565 |
|
|
signal blk00000003_sig00000213 : STD_LOGIC;
|
566 |
|
|
signal blk00000003_sig00000212 : STD_LOGIC;
|
567 |
|
|
signal blk00000003_sig00000211 : STD_LOGIC;
|
568 |
|
|
signal blk00000003_sig00000210 : STD_LOGIC;
|
569 |
|
|
signal blk00000003_sig0000020f : STD_LOGIC;
|
570 |
|
|
signal blk00000003_sig0000020e : STD_LOGIC;
|
571 |
|
|
signal blk00000003_sig0000020d : STD_LOGIC;
|
572 |
|
|
signal blk00000003_sig0000020c : STD_LOGIC;
|
573 |
|
|
signal blk00000003_sig0000020b : STD_LOGIC;
|
574 |
|
|
signal blk00000003_sig0000020a : STD_LOGIC;
|
575 |
|
|
signal blk00000003_sig00000209 : STD_LOGIC;
|
576 |
|
|
signal blk00000003_sig00000208 : STD_LOGIC;
|
577 |
|
|
signal blk00000003_sig00000207 : STD_LOGIC;
|
578 |
|
|
signal blk00000003_sig00000206 : STD_LOGIC;
|
579 |
|
|
signal blk00000003_sig00000205 : STD_LOGIC;
|
580 |
|
|
signal blk00000003_sig00000204 : STD_LOGIC;
|
581 |
|
|
signal blk00000003_sig00000203 : STD_LOGIC;
|
582 |
|
|
signal blk00000003_sig00000202 : STD_LOGIC;
|
583 |
|
|
signal blk00000003_sig00000201 : STD_LOGIC;
|
584 |
|
|
signal blk00000003_sig00000200 : STD_LOGIC;
|
585 |
|
|
signal blk00000003_sig000001ff : STD_LOGIC;
|
586 |
|
|
signal blk00000003_sig000001fe : STD_LOGIC;
|
587 |
|
|
signal blk00000003_sig000001fd : STD_LOGIC;
|
588 |
|
|
signal blk00000003_sig000001fc : STD_LOGIC;
|
589 |
|
|
signal blk00000003_sig000001fb : STD_LOGIC;
|
590 |
|
|
signal blk00000003_sig000001fa : STD_LOGIC;
|
591 |
|
|
signal blk00000003_sig000001f9 : STD_LOGIC;
|
592 |
|
|
signal blk00000003_sig000001f8 : STD_LOGIC;
|
593 |
|
|
signal blk00000003_sig000001f7 : STD_LOGIC;
|
594 |
|
|
signal blk00000003_sig000001f6 : STD_LOGIC;
|
595 |
|
|
signal blk00000003_sig000001f5 : STD_LOGIC;
|
596 |
|
|
signal blk00000003_sig000001f4 : STD_LOGIC;
|
597 |
|
|
signal blk00000003_sig000001f3 : STD_LOGIC;
|
598 |
|
|
signal blk00000003_sig000001f2 : STD_LOGIC;
|
599 |
|
|
signal blk00000003_sig000001f1 : STD_LOGIC;
|
600 |
|
|
signal blk00000003_sig000001f0 : STD_LOGIC;
|
601 |
|
|
signal blk00000003_sig000001ef : STD_LOGIC;
|
602 |
|
|
signal blk00000003_sig000001ee : STD_LOGIC;
|
603 |
|
|
signal blk00000003_sig000001ed : STD_LOGIC;
|
604 |
|
|
signal blk00000003_sig000001ec : STD_LOGIC;
|
605 |
|
|
signal blk00000003_sig000001eb : STD_LOGIC;
|
606 |
|
|
signal blk00000003_sig000001ea : STD_LOGIC;
|
607 |
|
|
signal blk00000003_sig000001e9 : STD_LOGIC;
|
608 |
|
|
signal blk00000003_sig000001e8 : STD_LOGIC;
|
609 |
|
|
signal blk00000003_sig000001e7 : STD_LOGIC;
|
610 |
|
|
signal blk00000003_sig000001e6 : STD_LOGIC;
|
611 |
|
|
signal blk00000003_sig000001e5 : STD_LOGIC;
|
612 |
|
|
signal blk00000003_sig000001e4 : STD_LOGIC;
|
613 |
|
|
signal blk00000003_sig000001e3 : STD_LOGIC;
|
614 |
|
|
signal blk00000003_sig000001e2 : STD_LOGIC;
|
615 |
|
|
signal blk00000003_sig000001e1 : STD_LOGIC;
|
616 |
|
|
signal blk00000003_sig000001e0 : STD_LOGIC;
|
617 |
|
|
signal blk00000003_sig000001df : STD_LOGIC;
|
618 |
|
|
signal blk00000003_sig000001de : STD_LOGIC;
|
619 |
|
|
signal blk00000003_sig000001dd : STD_LOGIC;
|
620 |
|
|
signal blk00000003_sig000001dc : STD_LOGIC;
|
621 |
|
|
signal blk00000003_sig000001db : STD_LOGIC;
|
622 |
|
|
signal blk00000003_sig000001da : STD_LOGIC;
|
623 |
|
|
signal blk00000003_sig000001d9 : STD_LOGIC;
|
624 |
|
|
signal blk00000003_sig000001d8 : STD_LOGIC;
|
625 |
|
|
signal blk00000003_sig000001d7 : STD_LOGIC;
|
626 |
|
|
signal blk00000003_sig000001d6 : STD_LOGIC;
|
627 |
|
|
signal blk00000003_sig000001d5 : STD_LOGIC;
|
628 |
|
|
signal blk00000003_sig000001d4 : STD_LOGIC;
|
629 |
|
|
signal blk00000003_sig000001d3 : STD_LOGIC;
|
630 |
|
|
signal blk00000003_sig000001d2 : STD_LOGIC;
|
631 |
|
|
signal blk00000003_sig000001d1 : STD_LOGIC;
|
632 |
|
|
signal blk00000003_sig000001d0 : STD_LOGIC;
|
633 |
|
|
signal blk00000003_sig000001cf : STD_LOGIC;
|
634 |
|
|
signal blk00000003_sig000001ce : STD_LOGIC;
|
635 |
|
|
signal blk00000003_sig000001cd : STD_LOGIC;
|
636 |
|
|
signal blk00000003_sig000001cc : STD_LOGIC;
|
637 |
|
|
signal blk00000003_sig000001cb : STD_LOGIC;
|
638 |
|
|
signal blk00000003_sig000001ca : STD_LOGIC;
|
639 |
|
|
signal blk00000003_sig000001c9 : STD_LOGIC;
|
640 |
|
|
signal blk00000003_sig000001c8 : STD_LOGIC;
|
641 |
|
|
signal blk00000003_sig000001c7 : STD_LOGIC;
|
642 |
|
|
signal blk00000003_sig000001c6 : STD_LOGIC;
|
643 |
|
|
signal blk00000003_sig000001c5 : STD_LOGIC;
|
644 |
|
|
signal blk00000003_sig000001c4 : STD_LOGIC;
|
645 |
|
|
signal blk00000003_sig000001c3 : STD_LOGIC;
|
646 |
|
|
signal blk00000003_sig000001c2 : STD_LOGIC;
|
647 |
|
|
signal blk00000003_sig000001c1 : STD_LOGIC;
|
648 |
|
|
signal blk00000003_sig000001c0 : STD_LOGIC;
|
649 |
|
|
signal blk00000003_sig000001bf : STD_LOGIC;
|
650 |
|
|
signal blk00000003_sig000001be : STD_LOGIC;
|
651 |
|
|
signal blk00000003_sig000001bd : STD_LOGIC;
|
652 |
|
|
signal blk00000003_sig000001bc : STD_LOGIC;
|
653 |
|
|
signal blk00000003_sig000001bb : STD_LOGIC;
|
654 |
|
|
signal blk00000003_sig000001ba : STD_LOGIC;
|
655 |
|
|
signal blk00000003_sig000001b9 : STD_LOGIC;
|
656 |
|
|
signal blk00000003_sig000001b8 : STD_LOGIC;
|
657 |
|
|
signal blk00000003_sig000001b7 : STD_LOGIC;
|
658 |
|
|
signal blk00000003_sig000001b6 : STD_LOGIC;
|
659 |
|
|
signal blk00000003_sig000001b5 : STD_LOGIC;
|
660 |
|
|
signal blk00000003_sig000001b4 : STD_LOGIC;
|
661 |
|
|
signal blk00000003_sig000001b3 : STD_LOGIC;
|
662 |
|
|
signal blk00000003_sig000001b2 : STD_LOGIC;
|
663 |
|
|
signal blk00000003_sig000001b1 : STD_LOGIC;
|
664 |
|
|
signal blk00000003_sig000001b0 : STD_LOGIC;
|
665 |
|
|
signal blk00000003_sig000001af : STD_LOGIC;
|
666 |
|
|
signal blk00000003_sig000001ae : STD_LOGIC;
|
667 |
|
|
signal blk00000003_sig000001ad : STD_LOGIC;
|
668 |
|
|
signal blk00000003_sig000001ac : STD_LOGIC;
|
669 |
|
|
signal blk00000003_sig000001ab : STD_LOGIC;
|
670 |
|
|
signal blk00000003_sig000001aa : STD_LOGIC;
|
671 |
|
|
signal blk00000003_sig000001a9 : STD_LOGIC;
|
672 |
|
|
signal blk00000003_sig000001a8 : STD_LOGIC;
|
673 |
|
|
signal blk00000003_sig000001a7 : STD_LOGIC;
|
674 |
|
|
signal blk00000003_sig000001a6 : STD_LOGIC;
|
675 |
|
|
signal blk00000003_sig000001a5 : STD_LOGIC;
|
676 |
|
|
signal blk00000003_sig000001a4 : STD_LOGIC;
|
677 |
|
|
signal blk00000003_sig000001a3 : STD_LOGIC;
|
678 |
|
|
signal blk00000003_sig000001a2 : STD_LOGIC;
|
679 |
|
|
signal blk00000003_sig000001a1 : STD_LOGIC;
|
680 |
|
|
signal blk00000003_sig000001a0 : STD_LOGIC;
|
681 |
|
|
signal blk00000003_sig0000019f : STD_LOGIC;
|
682 |
|
|
signal blk00000003_sig0000019e : STD_LOGIC;
|
683 |
|
|
signal blk00000003_sig0000019d : STD_LOGIC;
|
684 |
|
|
signal blk00000003_sig0000019c : STD_LOGIC;
|
685 |
|
|
signal blk00000003_sig0000019b : STD_LOGIC;
|
686 |
|
|
signal blk00000003_sig0000019a : STD_LOGIC;
|
687 |
|
|
signal blk00000003_sig00000199 : STD_LOGIC;
|
688 |
|
|
signal blk00000003_sig00000198 : STD_LOGIC;
|
689 |
|
|
signal blk00000003_sig00000197 : STD_LOGIC;
|
690 |
|
|
signal blk00000003_sig00000196 : STD_LOGIC;
|
691 |
|
|
signal blk00000003_sig00000195 : STD_LOGIC;
|
692 |
|
|
signal blk00000003_sig00000194 : STD_LOGIC;
|
693 |
|
|
signal blk00000003_sig00000193 : STD_LOGIC;
|
694 |
|
|
signal blk00000003_sig00000192 : STD_LOGIC;
|
695 |
|
|
signal blk00000003_sig00000191 : STD_LOGIC;
|
696 |
|
|
signal blk00000003_sig00000190 : STD_LOGIC;
|
697 |
|
|
signal blk00000003_sig0000018f : STD_LOGIC;
|
698 |
|
|
signal blk00000003_sig0000018e : STD_LOGIC;
|
699 |
|
|
signal blk00000003_sig0000018d : STD_LOGIC;
|
700 |
|
|
signal blk00000003_sig0000018c : STD_LOGIC;
|
701 |
|
|
signal blk00000003_sig0000018b : STD_LOGIC;
|
702 |
|
|
signal blk00000003_sig0000018a : STD_LOGIC;
|
703 |
|
|
signal blk00000003_sig00000189 : STD_LOGIC;
|
704 |
|
|
signal blk00000003_sig00000188 : STD_LOGIC;
|
705 |
|
|
signal blk00000003_sig00000187 : STD_LOGIC;
|
706 |
|
|
signal blk00000003_sig00000186 : STD_LOGIC;
|
707 |
|
|
signal blk00000003_sig00000185 : STD_LOGIC;
|
708 |
|
|
signal blk00000003_sig00000184 : STD_LOGIC;
|
709 |
|
|
signal blk00000003_sig00000183 : STD_LOGIC;
|
710 |
|
|
signal blk00000003_sig00000182 : STD_LOGIC;
|
711 |
|
|
signal blk00000003_sig00000181 : STD_LOGIC;
|
712 |
|
|
signal blk00000003_sig00000180 : STD_LOGIC;
|
713 |
|
|
signal blk00000003_sig0000017f : STD_LOGIC;
|
714 |
|
|
signal blk00000003_sig0000017e : STD_LOGIC;
|
715 |
|
|
signal blk00000003_sig0000017d : STD_LOGIC;
|
716 |
|
|
signal blk00000003_sig0000017c : STD_LOGIC;
|
717 |
|
|
signal blk00000003_sig0000017b : STD_LOGIC;
|
718 |
|
|
signal blk00000003_sig0000017a : STD_LOGIC;
|
719 |
|
|
signal blk00000003_sig00000179 : STD_LOGIC;
|
720 |
|
|
signal blk00000003_sig00000178 : STD_LOGIC;
|
721 |
|
|
signal blk00000003_sig00000177 : STD_LOGIC;
|
722 |
|
|
signal blk00000003_sig00000176 : STD_LOGIC;
|
723 |
|
|
signal blk00000003_sig00000175 : STD_LOGIC;
|
724 |
|
|
signal blk00000003_sig00000174 : STD_LOGIC;
|
725 |
|
|
signal blk00000003_sig00000173 : STD_LOGIC;
|
726 |
|
|
signal blk00000003_sig00000172 : STD_LOGIC;
|
727 |
|
|
signal blk00000003_sig00000171 : STD_LOGIC;
|
728 |
|
|
signal blk00000003_sig00000170 : STD_LOGIC;
|
729 |
|
|
signal blk00000003_sig0000016f : STD_LOGIC;
|
730 |
|
|
signal blk00000003_sig0000016e : STD_LOGIC;
|
731 |
|
|
signal blk00000003_sig0000016d : STD_LOGIC;
|
732 |
|
|
signal blk00000003_sig0000016c : STD_LOGIC;
|
733 |
|
|
signal blk00000003_sig0000016b : STD_LOGIC;
|
734 |
|
|
signal blk00000003_sig0000016a : STD_LOGIC;
|
735 |
|
|
signal blk00000003_sig00000169 : STD_LOGIC;
|
736 |
|
|
signal blk00000003_sig00000168 : STD_LOGIC;
|
737 |
|
|
signal blk00000003_sig00000167 : STD_LOGIC;
|
738 |
|
|
signal blk00000003_sig00000166 : STD_LOGIC;
|
739 |
|
|
signal blk00000003_sig00000165 : STD_LOGIC;
|
740 |
|
|
signal blk00000003_sig00000164 : STD_LOGIC;
|
741 |
|
|
signal blk00000003_sig00000163 : STD_LOGIC;
|
742 |
|
|
signal blk00000003_sig00000162 : STD_LOGIC;
|
743 |
|
|
signal blk00000003_sig00000161 : STD_LOGIC;
|
744 |
|
|
signal blk00000003_sig00000160 : STD_LOGIC;
|
745 |
|
|
signal blk00000003_sig0000015f : STD_LOGIC;
|
746 |
|
|
signal blk00000003_sig0000015e : STD_LOGIC;
|
747 |
|
|
signal blk00000003_sig0000015d : STD_LOGIC;
|
748 |
|
|
signal blk00000003_sig0000015c : STD_LOGIC;
|
749 |
|
|
signal blk00000003_sig0000015b : STD_LOGIC;
|
750 |
|
|
signal blk00000003_sig0000015a : STD_LOGIC;
|
751 |
|
|
signal blk00000003_sig00000159 : STD_LOGIC;
|
752 |
|
|
signal blk00000003_sig00000158 : STD_LOGIC;
|
753 |
|
|
signal blk00000003_sig00000157 : STD_LOGIC;
|
754 |
|
|
signal blk00000003_sig00000156 : STD_LOGIC;
|
755 |
|
|
signal blk00000003_sig00000155 : STD_LOGIC;
|
756 |
|
|
signal blk00000003_sig00000154 : STD_LOGIC;
|
757 |
|
|
signal blk00000003_sig00000153 : STD_LOGIC;
|
758 |
|
|
signal blk00000003_sig00000152 : STD_LOGIC;
|
759 |
|
|
signal blk00000003_sig00000151 : STD_LOGIC;
|
760 |
|
|
signal blk00000003_sig00000150 : STD_LOGIC;
|
761 |
|
|
signal blk00000003_sig0000014f : STD_LOGIC;
|
762 |
|
|
signal blk00000003_sig0000014e : STD_LOGIC;
|
763 |
|
|
signal blk00000003_sig0000014d : STD_LOGIC;
|
764 |
|
|
signal blk00000003_sig0000014c : STD_LOGIC;
|
765 |
|
|
signal blk00000003_sig0000014b : STD_LOGIC;
|
766 |
|
|
signal blk00000003_sig0000014a : STD_LOGIC;
|
767 |
|
|
signal blk00000003_sig00000149 : STD_LOGIC;
|
768 |
|
|
signal blk00000003_sig00000148 : STD_LOGIC;
|
769 |
|
|
signal blk00000003_sig00000147 : STD_LOGIC;
|
770 |
|
|
signal blk00000003_sig00000146 : STD_LOGIC;
|
771 |
|
|
signal blk00000003_sig00000145 : STD_LOGIC;
|
772 |
|
|
signal blk00000003_sig00000144 : STD_LOGIC;
|
773 |
|
|
signal blk00000003_sig00000143 : STD_LOGIC;
|
774 |
|
|
signal blk00000003_sig00000142 : STD_LOGIC;
|
775 |
|
|
signal blk00000003_sig00000141 : STD_LOGIC;
|
776 |
|
|
signal blk00000003_sig00000140 : STD_LOGIC;
|
777 |
|
|
signal blk00000003_sig0000013f : STD_LOGIC;
|
778 |
|
|
signal blk00000003_sig0000013e : STD_LOGIC;
|
779 |
|
|
signal blk00000003_sig0000013d : STD_LOGIC;
|
780 |
|
|
signal blk00000003_sig0000013c : STD_LOGIC;
|
781 |
|
|
signal blk00000003_sig0000013b : STD_LOGIC;
|
782 |
|
|
signal blk00000003_sig0000013a : STD_LOGIC;
|
783 |
|
|
signal blk00000003_sig00000139 : STD_LOGIC;
|
784 |
|
|
signal blk00000003_sig00000138 : STD_LOGIC;
|
785 |
|
|
signal blk00000003_sig00000137 : STD_LOGIC;
|
786 |
|
|
signal blk00000003_sig00000136 : STD_LOGIC;
|
787 |
|
|
signal blk00000003_sig00000135 : STD_LOGIC;
|
788 |
|
|
signal blk00000003_sig00000134 : STD_LOGIC;
|
789 |
|
|
signal blk00000003_sig00000133 : STD_LOGIC;
|
790 |
|
|
signal blk00000003_sig00000132 : STD_LOGIC;
|
791 |
|
|
signal blk00000003_sig00000131 : STD_LOGIC;
|
792 |
|
|
signal blk00000003_sig00000130 : STD_LOGIC;
|
793 |
|
|
signal blk00000003_sig0000012f : STD_LOGIC;
|
794 |
|
|
signal blk00000003_sig0000012e : STD_LOGIC;
|
795 |
|
|
signal blk00000003_sig0000012d : STD_LOGIC;
|
796 |
|
|
signal blk00000003_sig0000012c : STD_LOGIC;
|
797 |
|
|
signal blk00000003_sig0000012b : STD_LOGIC;
|
798 |
|
|
signal blk00000003_sig0000012a : STD_LOGIC;
|
799 |
|
|
signal blk00000003_sig00000129 : STD_LOGIC;
|
800 |
|
|
signal blk00000003_sig00000128 : STD_LOGIC;
|
801 |
|
|
signal blk00000003_sig00000127 : STD_LOGIC;
|
802 |
|
|
signal blk00000003_sig00000126 : STD_LOGIC;
|
803 |
|
|
signal blk00000003_sig00000125 : STD_LOGIC;
|
804 |
|
|
signal blk00000003_sig00000124 : STD_LOGIC;
|
805 |
|
|
signal blk00000003_sig00000123 : STD_LOGIC;
|
806 |
|
|
signal blk00000003_sig00000122 : STD_LOGIC;
|
807 |
|
|
signal blk00000003_sig00000121 : STD_LOGIC;
|
808 |
|
|
signal blk00000003_sig00000120 : STD_LOGIC;
|
809 |
|
|
signal blk00000003_sig0000011f : STD_LOGIC;
|
810 |
|
|
signal blk00000003_sig0000011e : STD_LOGIC;
|
811 |
|
|
signal blk00000003_sig0000011d : STD_LOGIC;
|
812 |
|
|
signal blk00000003_sig0000011c : STD_LOGIC;
|
813 |
|
|
signal blk00000003_sig0000011b : STD_LOGIC;
|
814 |
|
|
signal blk00000003_sig0000011a : STD_LOGIC;
|
815 |
|
|
signal blk00000003_sig00000119 : STD_LOGIC;
|
816 |
|
|
signal blk00000003_sig00000118 : STD_LOGIC;
|
817 |
|
|
signal blk00000003_sig00000117 : STD_LOGIC;
|
818 |
|
|
signal blk00000003_sig00000116 : STD_LOGIC;
|
819 |
|
|
signal blk00000003_sig00000115 : STD_LOGIC;
|
820 |
|
|
signal blk00000003_sig00000114 : STD_LOGIC;
|
821 |
|
|
signal blk00000003_sig00000113 : STD_LOGIC;
|
822 |
|
|
signal blk00000003_sig00000112 : STD_LOGIC;
|
823 |
|
|
signal blk00000003_sig00000111 : STD_LOGIC;
|
824 |
|
|
signal blk00000003_sig00000110 : STD_LOGIC;
|
825 |
|
|
signal blk00000003_sig0000010f : STD_LOGIC;
|
826 |
|
|
signal blk00000003_sig0000010e : STD_LOGIC;
|
827 |
|
|
signal blk00000003_sig0000010d : STD_LOGIC;
|
828 |
|
|
signal blk00000003_sig0000010c : STD_LOGIC;
|
829 |
|
|
signal blk00000003_sig0000010b : STD_LOGIC;
|
830 |
|
|
signal blk00000003_sig0000010a : STD_LOGIC;
|
831 |
|
|
signal blk00000003_sig00000109 : STD_LOGIC;
|
832 |
|
|
signal blk00000003_sig00000108 : STD_LOGIC;
|
833 |
|
|
signal blk00000003_sig00000107 : STD_LOGIC;
|
834 |
|
|
signal blk00000003_sig00000106 : STD_LOGIC;
|
835 |
|
|
signal blk00000003_sig00000105 : STD_LOGIC;
|
836 |
|
|
signal blk00000003_sig00000104 : STD_LOGIC;
|
837 |
|
|
signal blk00000003_sig00000103 : STD_LOGIC;
|
838 |
|
|
signal blk00000003_sig00000102 : STD_LOGIC;
|
839 |
|
|
signal blk00000003_sig00000101 : STD_LOGIC;
|
840 |
|
|
signal blk00000003_sig00000100 : STD_LOGIC;
|
841 |
|
|
signal blk00000003_sig000000ff : STD_LOGIC;
|
842 |
|
|
signal blk00000003_sig000000fe : STD_LOGIC;
|
843 |
|
|
signal blk00000003_sig000000fd : STD_LOGIC;
|
844 |
|
|
signal blk00000003_sig000000fc : STD_LOGIC;
|
845 |
|
|
signal blk00000003_sig000000fb : STD_LOGIC;
|
846 |
|
|
signal blk00000003_sig000000fa : STD_LOGIC;
|
847 |
|
|
signal blk00000003_sig000000f9 : STD_LOGIC;
|
848 |
|
|
signal blk00000003_sig000000f8 : STD_LOGIC;
|
849 |
|
|
signal blk00000003_sig000000f7 : STD_LOGIC;
|
850 |
|
|
signal blk00000003_sig000000f6 : STD_LOGIC;
|
851 |
|
|
signal blk00000003_sig000000f5 : STD_LOGIC;
|
852 |
|
|
signal blk00000003_sig000000f4 : STD_LOGIC;
|
853 |
|
|
signal blk00000003_sig000000f3 : STD_LOGIC;
|
854 |
|
|
signal blk00000003_sig000000f2 : STD_LOGIC;
|
855 |
|
|
signal blk00000003_sig000000f1 : STD_LOGIC;
|
856 |
|
|
signal blk00000003_sig000000f0 : STD_LOGIC;
|
857 |
|
|
signal blk00000003_sig000000ef : STD_LOGIC;
|
858 |
|
|
signal blk00000003_sig000000ee : STD_LOGIC;
|
859 |
|
|
signal blk00000003_sig000000ed : STD_LOGIC;
|
860 |
|
|
signal blk00000003_sig000000ec : STD_LOGIC;
|
861 |
|
|
signal blk00000003_sig000000eb : STD_LOGIC;
|
862 |
|
|
signal blk00000003_sig000000ea : STD_LOGIC;
|
863 |
|
|
signal blk00000003_sig000000e9 : STD_LOGIC;
|
864 |
|
|
signal blk00000003_sig000000e8 : STD_LOGIC;
|
865 |
|
|
signal blk00000003_sig000000e7 : STD_LOGIC;
|
866 |
|
|
signal blk00000003_sig000000e6 : STD_LOGIC;
|
867 |
|
|
signal blk00000003_sig000000e5 : STD_LOGIC;
|
868 |
|
|
signal blk00000003_sig000000e4 : STD_LOGIC;
|
869 |
|
|
signal blk00000003_sig000000e3 : STD_LOGIC;
|
870 |
|
|
signal blk00000003_sig000000e2 : STD_LOGIC;
|
871 |
|
|
signal blk00000003_sig000000e1 : STD_LOGIC;
|
872 |
|
|
signal blk00000003_sig000000e0 : STD_LOGIC;
|
873 |
|
|
signal blk00000003_sig000000df : STD_LOGIC;
|
874 |
|
|
signal blk00000003_sig000000de : STD_LOGIC;
|
875 |
|
|
signal blk00000003_sig000000dd : STD_LOGIC;
|
876 |
|
|
signal blk00000003_sig000000dc : STD_LOGIC;
|
877 |
|
|
signal blk00000003_sig000000db : STD_LOGIC;
|
878 |
|
|
signal blk00000003_sig000000da : STD_LOGIC;
|
879 |
|
|
signal blk00000003_sig000000d9 : STD_LOGIC;
|
880 |
|
|
signal blk00000003_sig000000d8 : STD_LOGIC;
|
881 |
|
|
signal blk00000003_sig000000d7 : STD_LOGIC;
|
882 |
|
|
signal blk00000003_sig000000d6 : STD_LOGIC;
|
883 |
|
|
signal blk00000003_sig000000d5 : STD_LOGIC;
|
884 |
|
|
signal blk00000003_sig000000d4 : STD_LOGIC;
|
885 |
|
|
signal blk00000003_sig000000d3 : STD_LOGIC;
|
886 |
|
|
signal blk00000003_sig000000d2 : STD_LOGIC;
|
887 |
|
|
signal blk00000003_sig000000d1 : STD_LOGIC;
|
888 |
|
|
signal blk00000003_sig000000d0 : STD_LOGIC;
|
889 |
|
|
signal blk00000003_sig000000cf : STD_LOGIC;
|
890 |
|
|
signal blk00000003_sig000000ce : STD_LOGIC;
|
891 |
|
|
signal blk00000003_sig000000cd : STD_LOGIC;
|
892 |
|
|
signal blk00000003_sig000000cc : STD_LOGIC;
|
893 |
|
|
signal blk00000003_sig000000cb : STD_LOGIC;
|
894 |
|
|
signal blk00000003_sig00000067 : STD_LOGIC;
|
895 |
|
|
signal blk00000003_sig00000066 : STD_LOGIC;
|
896 |
|
|
signal NLW_blk00000001_P_UNCONNECTED : STD_LOGIC;
|
897 |
|
|
signal NLW_blk00000002_G_UNCONNECTED : STD_LOGIC;
|
898 |
|
|
signal NLW_blk00000003_blk000002c3_Q15_UNCONNECTED : STD_LOGIC;
|
899 |
|
|
signal NLW_blk00000003_blk000002c1_Q15_UNCONNECTED : STD_LOGIC;
|
900 |
|
|
signal NLW_blk00000003_blk000002bf_Q15_UNCONNECTED : STD_LOGIC;
|
901 |
|
|
signal NLW_blk00000003_blk000002bd_Q15_UNCONNECTED : STD_LOGIC;
|
902 |
|
|
signal NLW_blk00000003_blk000002bb_Q15_UNCONNECTED : STD_LOGIC;
|
903 |
|
|
signal NLW_blk00000003_blk000002b9_Q15_UNCONNECTED : STD_LOGIC;
|
904 |
|
|
signal NLW_blk00000003_blk000002b7_Q15_UNCONNECTED : STD_LOGIC;
|
905 |
|
|
signal NLW_blk00000003_blk000002b5_Q15_UNCONNECTED : STD_LOGIC;
|
906 |
|
|
signal NLW_blk00000003_blk000002b3_Q15_UNCONNECTED : STD_LOGIC;
|
907 |
|
|
signal NLW_blk00000003_blk000002b1_Q15_UNCONNECTED : STD_LOGIC;
|
908 |
|
|
signal NLW_blk00000003_blk000002af_Q15_UNCONNECTED : STD_LOGIC;
|
909 |
|
|
signal NLW_blk00000003_blk000002ad_Q15_UNCONNECTED : STD_LOGIC;
|
910 |
|
|
signal NLW_blk00000003_blk000002ab_Q15_UNCONNECTED : STD_LOGIC;
|
911 |
|
|
signal NLW_blk00000003_blk000002a9_Q15_UNCONNECTED : STD_LOGIC;
|
912 |
|
|
signal NLW_blk00000003_blk000002a7_Q15_UNCONNECTED : STD_LOGIC;
|
913 |
|
|
signal NLW_blk00000003_blk0000011d_O_UNCONNECTED : STD_LOGIC;
|
914 |
|
|
signal NLW_blk00000003_blk000000e2_O_UNCONNECTED : STD_LOGIC;
|
915 |
|
|
signal NLW_blk00000003_blk000000e0_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
|
916 |
|
|
signal NLW_blk00000003_blk000000e0_OVERFLOW_UNCONNECTED : STD_LOGIC;
|
917 |
|
|
signal NLW_blk00000003_blk000000e0_UNDERFLOW_UNCONNECTED : STD_LOGIC;
|
918 |
|
|
signal NLW_blk00000003_blk000000e0_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
|
919 |
|
|
signal NLW_blk00000003_blk000000e0_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
|
920 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_47_UNCONNECTED : STD_LOGIC;
|
921 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_46_UNCONNECTED : STD_LOGIC;
|
922 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_45_UNCONNECTED : STD_LOGIC;
|
923 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_44_UNCONNECTED : STD_LOGIC;
|
924 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_43_UNCONNECTED : STD_LOGIC;
|
925 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_42_UNCONNECTED : STD_LOGIC;
|
926 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_41_UNCONNECTED : STD_LOGIC;
|
927 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_40_UNCONNECTED : STD_LOGIC;
|
928 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_39_UNCONNECTED : STD_LOGIC;
|
929 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_38_UNCONNECTED : STD_LOGIC;
|
930 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_37_UNCONNECTED : STD_LOGIC;
|
931 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_36_UNCONNECTED : STD_LOGIC;
|
932 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_35_UNCONNECTED : STD_LOGIC;
|
933 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_34_UNCONNECTED : STD_LOGIC;
|
934 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_33_UNCONNECTED : STD_LOGIC;
|
935 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_32_UNCONNECTED : STD_LOGIC;
|
936 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_31_UNCONNECTED : STD_LOGIC;
|
937 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_30_UNCONNECTED : STD_LOGIC;
|
938 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_29_UNCONNECTED : STD_LOGIC;
|
939 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_28_UNCONNECTED : STD_LOGIC;
|
940 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_27_UNCONNECTED : STD_LOGIC;
|
941 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_26_UNCONNECTED : STD_LOGIC;
|
942 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_25_UNCONNECTED : STD_LOGIC;
|
943 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_24_UNCONNECTED : STD_LOGIC;
|
944 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_23_UNCONNECTED : STD_LOGIC;
|
945 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_22_UNCONNECTED : STD_LOGIC;
|
946 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_21_UNCONNECTED : STD_LOGIC;
|
947 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_20_UNCONNECTED : STD_LOGIC;
|
948 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_19_UNCONNECTED : STD_LOGIC;
|
949 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_18_UNCONNECTED : STD_LOGIC;
|
950 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_17_UNCONNECTED : STD_LOGIC;
|
951 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_16_UNCONNECTED : STD_LOGIC;
|
952 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_15_UNCONNECTED : STD_LOGIC;
|
953 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_14_UNCONNECTED : STD_LOGIC;
|
954 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_13_UNCONNECTED : STD_LOGIC;
|
955 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_12_UNCONNECTED : STD_LOGIC;
|
956 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_11_UNCONNECTED : STD_LOGIC;
|
957 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_10_UNCONNECTED : STD_LOGIC;
|
958 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_9_UNCONNECTED : STD_LOGIC;
|
959 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_8_UNCONNECTED : STD_LOGIC;
|
960 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_7_UNCONNECTED : STD_LOGIC;
|
961 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_6_UNCONNECTED : STD_LOGIC;
|
962 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_5_UNCONNECTED : STD_LOGIC;
|
963 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_4_UNCONNECTED : STD_LOGIC;
|
964 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_3_UNCONNECTED : STD_LOGIC;
|
965 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_2_UNCONNECTED : STD_LOGIC;
|
966 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_1_UNCONNECTED : STD_LOGIC;
|
967 |
|
|
signal NLW_blk00000003_blk000000e0_PCOUT_0_UNCONNECTED : STD_LOGIC;
|
968 |
|
|
signal NLW_blk00000003_blk000000e0_P_47_UNCONNECTED : STD_LOGIC;
|
969 |
|
|
signal NLW_blk00000003_blk000000e0_P_46_UNCONNECTED : STD_LOGIC;
|
970 |
|
|
signal NLW_blk00000003_blk000000e0_P_45_UNCONNECTED : STD_LOGIC;
|
971 |
|
|
signal NLW_blk00000003_blk000000e0_P_44_UNCONNECTED : STD_LOGIC;
|
972 |
|
|
signal NLW_blk00000003_blk000000e0_P_43_UNCONNECTED : STD_LOGIC;
|
973 |
|
|
signal NLW_blk00000003_blk000000e0_P_42_UNCONNECTED : STD_LOGIC;
|
974 |
|
|
signal NLW_blk00000003_blk000000e0_P_41_UNCONNECTED : STD_LOGIC;
|
975 |
|
|
signal NLW_blk00000003_blk000000e0_P_40_UNCONNECTED : STD_LOGIC;
|
976 |
|
|
signal NLW_blk00000003_blk000000e0_BCOUT_17_UNCONNECTED : STD_LOGIC;
|
977 |
|
|
signal NLW_blk00000003_blk000000e0_BCOUT_16_UNCONNECTED : STD_LOGIC;
|
978 |
|
|
signal NLW_blk00000003_blk000000e0_BCOUT_15_UNCONNECTED : STD_LOGIC;
|
979 |
|
|
signal NLW_blk00000003_blk000000e0_BCOUT_14_UNCONNECTED : STD_LOGIC;
|
980 |
|
|
signal NLW_blk00000003_blk000000e0_BCOUT_13_UNCONNECTED : STD_LOGIC;
|
981 |
|
|
signal NLW_blk00000003_blk000000e0_BCOUT_12_UNCONNECTED : STD_LOGIC;
|
982 |
|
|
signal NLW_blk00000003_blk000000e0_BCOUT_11_UNCONNECTED : STD_LOGIC;
|
983 |
|
|
signal NLW_blk00000003_blk000000e0_BCOUT_10_UNCONNECTED : STD_LOGIC;
|
984 |
|
|
signal NLW_blk00000003_blk000000e0_BCOUT_9_UNCONNECTED : STD_LOGIC;
|
985 |
|
|
signal NLW_blk00000003_blk000000e0_BCOUT_8_UNCONNECTED : STD_LOGIC;
|
986 |
|
|
signal NLW_blk00000003_blk000000e0_BCOUT_7_UNCONNECTED : STD_LOGIC;
|
987 |
|
|
signal NLW_blk00000003_blk000000e0_BCOUT_6_UNCONNECTED : STD_LOGIC;
|
988 |
|
|
signal NLW_blk00000003_blk000000e0_BCOUT_5_UNCONNECTED : STD_LOGIC;
|
989 |
|
|
signal NLW_blk00000003_blk000000e0_BCOUT_4_UNCONNECTED : STD_LOGIC;
|
990 |
|
|
signal NLW_blk00000003_blk000000e0_BCOUT_3_UNCONNECTED : STD_LOGIC;
|
991 |
|
|
signal NLW_blk00000003_blk000000e0_BCOUT_2_UNCONNECTED : STD_LOGIC;
|
992 |
|
|
signal NLW_blk00000003_blk000000e0_BCOUT_1_UNCONNECTED : STD_LOGIC;
|
993 |
|
|
signal NLW_blk00000003_blk000000e0_BCOUT_0_UNCONNECTED : STD_LOGIC;
|
994 |
|
|
signal NLW_blk00000003_blk000000e0_ACOUT_29_UNCONNECTED : STD_LOGIC;
|
995 |
|
|
signal NLW_blk00000003_blk000000e0_ACOUT_28_UNCONNECTED : STD_LOGIC;
|
996 |
|
|
signal NLW_blk00000003_blk000000e0_ACOUT_27_UNCONNECTED : STD_LOGIC;
|
997 |
|
|
signal NLW_blk00000003_blk000000e0_ACOUT_26_UNCONNECTED : STD_LOGIC;
|
998 |
|
|
signal NLW_blk00000003_blk000000e0_ACOUT_25_UNCONNECTED : STD_LOGIC;
|
999 |
|
|
signal NLW_blk00000003_blk000000e0_ACOUT_24_UNCONNECTED : STD_LOGIC;
|
1000 |
|
|
signal NLW_blk00000003_blk000000e0_ACOUT_23_UNCONNECTED : STD_LOGIC;
|
1001 |
|
|
signal NLW_blk00000003_blk000000e0_ACOUT_22_UNCONNECTED : STD_LOGIC;
|
1002 |
|
|
signal NLW_blk00000003_blk000000e0_ACOUT_21_UNCONNECTED : STD_LOGIC;
|
1003 |
|
|
signal NLW_blk00000003_blk000000e0_ACOUT_20_UNCONNECTED : STD_LOGIC;
|
1004 |
|
|
signal NLW_blk00000003_blk000000e0_ACOUT_19_UNCONNECTED : STD_LOGIC;
|
1005 |
|
|
signal NLW_blk00000003_blk000000e0_ACOUT_18_UNCONNECTED : STD_LOGIC;
|
1006 |
|
|
signal NLW_blk00000003_blk000000e0_ACOUT_17_UNCONNECTED : STD_LOGIC;
|
1007 |
|
|
signal NLW_blk00000003_blk000000e0_ACOUT_16_UNCONNECTED : STD_LOGIC;
|
1008 |
|
|
signal NLW_blk00000003_blk000000e0_ACOUT_15_UNCONNECTED : STD_LOGIC;
|
1009 |
|
|
signal NLW_blk00000003_blk000000e0_ACOUT_14_UNCONNECTED : STD_LOGIC;
|
1010 |
|
|
signal NLW_blk00000003_blk000000e0_ACOUT_13_UNCONNECTED : STD_LOGIC;
|
1011 |
|
|
signal NLW_blk00000003_blk000000e0_ACOUT_12_UNCONNECTED : STD_LOGIC;
|
1012 |
|
|
signal NLW_blk00000003_blk000000e0_ACOUT_11_UNCONNECTED : STD_LOGIC;
|
1013 |
|
|
signal NLW_blk00000003_blk000000e0_ACOUT_10_UNCONNECTED : STD_LOGIC;
|
1014 |
|
|
signal NLW_blk00000003_blk000000e0_ACOUT_9_UNCONNECTED : STD_LOGIC;
|
1015 |
|
|
signal NLW_blk00000003_blk000000e0_ACOUT_8_UNCONNECTED : STD_LOGIC;
|
1016 |
|
|
signal NLW_blk00000003_blk000000e0_ACOUT_7_UNCONNECTED : STD_LOGIC;
|
1017 |
|
|
signal NLW_blk00000003_blk000000e0_ACOUT_6_UNCONNECTED : STD_LOGIC;
|
1018 |
|
|
signal NLW_blk00000003_blk000000e0_ACOUT_5_UNCONNECTED : STD_LOGIC;
|
1019 |
|
|
signal NLW_blk00000003_blk000000e0_ACOUT_4_UNCONNECTED : STD_LOGIC;
|
1020 |
|
|
signal NLW_blk00000003_blk000000e0_ACOUT_3_UNCONNECTED : STD_LOGIC;
|
1021 |
|
|
signal NLW_blk00000003_blk000000e0_ACOUT_2_UNCONNECTED : STD_LOGIC;
|
1022 |
|
|
signal NLW_blk00000003_blk000000e0_ACOUT_1_UNCONNECTED : STD_LOGIC;
|
1023 |
|
|
signal NLW_blk00000003_blk000000e0_ACOUT_0_UNCONNECTED : STD_LOGIC;
|
1024 |
|
|
signal NLW_blk00000003_blk000000e0_CARRYOUT_3_UNCONNECTED : STD_LOGIC;
|
1025 |
|
|
signal NLW_blk00000003_blk000000e0_CARRYOUT_2_UNCONNECTED : STD_LOGIC;
|
1026 |
|
|
signal NLW_blk00000003_blk000000e0_CARRYOUT_1_UNCONNECTED : STD_LOGIC;
|
1027 |
|
|
signal NLW_blk00000003_blk000000e0_CARRYOUT_0_UNCONNECTED : STD_LOGIC;
|
1028 |
|
|
signal NLW_blk00000003_blk00000096_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
|
1029 |
|
|
signal NLW_blk00000003_blk00000096_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
|
1030 |
|
|
signal NLW_blk00000003_blk00000096_OVERFLOW_UNCONNECTED : STD_LOGIC;
|
1031 |
|
|
signal NLW_blk00000003_blk00000096_UNDERFLOW_UNCONNECTED : STD_LOGIC;
|
1032 |
|
|
signal NLW_blk00000003_blk00000096_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
|
1033 |
|
|
signal NLW_blk00000003_blk00000096_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
|
1034 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_47_UNCONNECTED : STD_LOGIC;
|
1035 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_46_UNCONNECTED : STD_LOGIC;
|
1036 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_45_UNCONNECTED : STD_LOGIC;
|
1037 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_44_UNCONNECTED : STD_LOGIC;
|
1038 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_43_UNCONNECTED : STD_LOGIC;
|
1039 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_42_UNCONNECTED : STD_LOGIC;
|
1040 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_41_UNCONNECTED : STD_LOGIC;
|
1041 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_40_UNCONNECTED : STD_LOGIC;
|
1042 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_39_UNCONNECTED : STD_LOGIC;
|
1043 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_38_UNCONNECTED : STD_LOGIC;
|
1044 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_37_UNCONNECTED : STD_LOGIC;
|
1045 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_36_UNCONNECTED : STD_LOGIC;
|
1046 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_35_UNCONNECTED : STD_LOGIC;
|
1047 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_34_UNCONNECTED : STD_LOGIC;
|
1048 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_33_UNCONNECTED : STD_LOGIC;
|
1049 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_32_UNCONNECTED : STD_LOGIC;
|
1050 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_31_UNCONNECTED : STD_LOGIC;
|
1051 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_30_UNCONNECTED : STD_LOGIC;
|
1052 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_29_UNCONNECTED : STD_LOGIC;
|
1053 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_28_UNCONNECTED : STD_LOGIC;
|
1054 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_27_UNCONNECTED : STD_LOGIC;
|
1055 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_26_UNCONNECTED : STD_LOGIC;
|
1056 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_25_UNCONNECTED : STD_LOGIC;
|
1057 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_24_UNCONNECTED : STD_LOGIC;
|
1058 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_23_UNCONNECTED : STD_LOGIC;
|
1059 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_22_UNCONNECTED : STD_LOGIC;
|
1060 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_21_UNCONNECTED : STD_LOGIC;
|
1061 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_20_UNCONNECTED : STD_LOGIC;
|
1062 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_19_UNCONNECTED : STD_LOGIC;
|
1063 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_18_UNCONNECTED : STD_LOGIC;
|
1064 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_17_UNCONNECTED : STD_LOGIC;
|
1065 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_16_UNCONNECTED : STD_LOGIC;
|
1066 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_15_UNCONNECTED : STD_LOGIC;
|
1067 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_14_UNCONNECTED : STD_LOGIC;
|
1068 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_13_UNCONNECTED : STD_LOGIC;
|
1069 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_12_UNCONNECTED : STD_LOGIC;
|
1070 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_11_UNCONNECTED : STD_LOGIC;
|
1071 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_10_UNCONNECTED : STD_LOGIC;
|
1072 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_9_UNCONNECTED : STD_LOGIC;
|
1073 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_8_UNCONNECTED : STD_LOGIC;
|
1074 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_7_UNCONNECTED : STD_LOGIC;
|
1075 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_6_UNCONNECTED : STD_LOGIC;
|
1076 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_5_UNCONNECTED : STD_LOGIC;
|
1077 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_4_UNCONNECTED : STD_LOGIC;
|
1078 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_3_UNCONNECTED : STD_LOGIC;
|
1079 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_2_UNCONNECTED : STD_LOGIC;
|
1080 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_1_UNCONNECTED : STD_LOGIC;
|
1081 |
|
|
signal NLW_blk00000003_blk00000096_PCOUT_0_UNCONNECTED : STD_LOGIC;
|
1082 |
|
|
signal NLW_blk00000003_blk00000096_P_47_UNCONNECTED : STD_LOGIC;
|
1083 |
|
|
signal NLW_blk00000003_blk00000096_P_46_UNCONNECTED : STD_LOGIC;
|
1084 |
|
|
signal NLW_blk00000003_blk00000096_P_45_UNCONNECTED : STD_LOGIC;
|
1085 |
|
|
signal NLW_blk00000003_blk00000096_P_44_UNCONNECTED : STD_LOGIC;
|
1086 |
|
|
signal NLW_blk00000003_blk00000096_P_43_UNCONNECTED : STD_LOGIC;
|
1087 |
|
|
signal NLW_blk00000003_blk00000096_P_42_UNCONNECTED : STD_LOGIC;
|
1088 |
|
|
signal NLW_blk00000003_blk00000096_P_41_UNCONNECTED : STD_LOGIC;
|
1089 |
|
|
signal NLW_blk00000003_blk00000096_P_40_UNCONNECTED : STD_LOGIC;
|
1090 |
|
|
signal NLW_blk00000003_blk00000096_P_39_UNCONNECTED : STD_LOGIC;
|
1091 |
|
|
signal NLW_blk00000003_blk00000096_P_38_UNCONNECTED : STD_LOGIC;
|
1092 |
|
|
signal NLW_blk00000003_blk00000096_P_37_UNCONNECTED : STD_LOGIC;
|
1093 |
|
|
signal NLW_blk00000003_blk00000096_P_36_UNCONNECTED : STD_LOGIC;
|
1094 |
|
|
signal NLW_blk00000003_blk00000096_P_35_UNCONNECTED : STD_LOGIC;
|
1095 |
|
|
signal NLW_blk00000003_blk00000096_P_26_UNCONNECTED : STD_LOGIC;
|
1096 |
|
|
signal NLW_blk00000003_blk00000096_P_25_UNCONNECTED : STD_LOGIC;
|
1097 |
|
|
signal NLW_blk00000003_blk00000096_P_1_UNCONNECTED : STD_LOGIC;
|
1098 |
|
|
signal NLW_blk00000003_blk00000096_P_0_UNCONNECTED : STD_LOGIC;
|
1099 |
|
|
signal NLW_blk00000003_blk00000096_BCOUT_17_UNCONNECTED : STD_LOGIC;
|
1100 |
|
|
signal NLW_blk00000003_blk00000096_BCOUT_16_UNCONNECTED : STD_LOGIC;
|
1101 |
|
|
signal NLW_blk00000003_blk00000096_BCOUT_15_UNCONNECTED : STD_LOGIC;
|
1102 |
|
|
signal NLW_blk00000003_blk00000096_BCOUT_14_UNCONNECTED : STD_LOGIC;
|
1103 |
|
|
signal NLW_blk00000003_blk00000096_BCOUT_13_UNCONNECTED : STD_LOGIC;
|
1104 |
|
|
signal NLW_blk00000003_blk00000096_BCOUT_12_UNCONNECTED : STD_LOGIC;
|
1105 |
|
|
signal NLW_blk00000003_blk00000096_BCOUT_11_UNCONNECTED : STD_LOGIC;
|
1106 |
|
|
signal NLW_blk00000003_blk00000096_BCOUT_10_UNCONNECTED : STD_LOGIC;
|
1107 |
|
|
signal NLW_blk00000003_blk00000096_BCOUT_9_UNCONNECTED : STD_LOGIC;
|
1108 |
|
|
signal NLW_blk00000003_blk00000096_BCOUT_8_UNCONNECTED : STD_LOGIC;
|
1109 |
|
|
signal NLW_blk00000003_blk00000096_BCOUT_7_UNCONNECTED : STD_LOGIC;
|
1110 |
|
|
signal NLW_blk00000003_blk00000096_BCOUT_6_UNCONNECTED : STD_LOGIC;
|
1111 |
|
|
signal NLW_blk00000003_blk00000096_BCOUT_5_UNCONNECTED : STD_LOGIC;
|
1112 |
|
|
signal NLW_blk00000003_blk00000096_BCOUT_4_UNCONNECTED : STD_LOGIC;
|
1113 |
|
|
signal NLW_blk00000003_blk00000096_BCOUT_3_UNCONNECTED : STD_LOGIC;
|
1114 |
|
|
signal NLW_blk00000003_blk00000096_BCOUT_2_UNCONNECTED : STD_LOGIC;
|
1115 |
|
|
signal NLW_blk00000003_blk00000096_BCOUT_1_UNCONNECTED : STD_LOGIC;
|
1116 |
|
|
signal NLW_blk00000003_blk00000096_BCOUT_0_UNCONNECTED : STD_LOGIC;
|
1117 |
|
|
signal NLW_blk00000003_blk00000096_ACOUT_29_UNCONNECTED : STD_LOGIC;
|
1118 |
|
|
signal NLW_blk00000003_blk00000096_ACOUT_28_UNCONNECTED : STD_LOGIC;
|
1119 |
|
|
signal NLW_blk00000003_blk00000096_ACOUT_27_UNCONNECTED : STD_LOGIC;
|
1120 |
|
|
signal NLW_blk00000003_blk00000096_ACOUT_26_UNCONNECTED : STD_LOGIC;
|
1121 |
|
|
signal NLW_blk00000003_blk00000096_ACOUT_25_UNCONNECTED : STD_LOGIC;
|
1122 |
|
|
signal NLW_blk00000003_blk00000096_ACOUT_24_UNCONNECTED : STD_LOGIC;
|
1123 |
|
|
signal NLW_blk00000003_blk00000096_ACOUT_23_UNCONNECTED : STD_LOGIC;
|
1124 |
|
|
signal NLW_blk00000003_blk00000096_ACOUT_22_UNCONNECTED : STD_LOGIC;
|
1125 |
|
|
signal NLW_blk00000003_blk00000096_ACOUT_21_UNCONNECTED : STD_LOGIC;
|
1126 |
|
|
signal NLW_blk00000003_blk00000096_ACOUT_20_UNCONNECTED : STD_LOGIC;
|
1127 |
|
|
signal NLW_blk00000003_blk00000096_ACOUT_19_UNCONNECTED : STD_LOGIC;
|
1128 |
|
|
signal NLW_blk00000003_blk00000096_ACOUT_18_UNCONNECTED : STD_LOGIC;
|
1129 |
|
|
signal NLW_blk00000003_blk00000096_ACOUT_17_UNCONNECTED : STD_LOGIC;
|
1130 |
|
|
signal NLW_blk00000003_blk00000096_ACOUT_16_UNCONNECTED : STD_LOGIC;
|
1131 |
|
|
signal NLW_blk00000003_blk00000096_ACOUT_15_UNCONNECTED : STD_LOGIC;
|
1132 |
|
|
signal NLW_blk00000003_blk00000096_ACOUT_14_UNCONNECTED : STD_LOGIC;
|
1133 |
|
|
signal NLW_blk00000003_blk00000096_ACOUT_13_UNCONNECTED : STD_LOGIC;
|
1134 |
|
|
signal NLW_blk00000003_blk00000096_ACOUT_12_UNCONNECTED : STD_LOGIC;
|
1135 |
|
|
signal NLW_blk00000003_blk00000096_ACOUT_11_UNCONNECTED : STD_LOGIC;
|
1136 |
|
|
signal NLW_blk00000003_blk00000096_ACOUT_10_UNCONNECTED : STD_LOGIC;
|
1137 |
|
|
signal NLW_blk00000003_blk00000096_ACOUT_9_UNCONNECTED : STD_LOGIC;
|
1138 |
|
|
signal NLW_blk00000003_blk00000096_ACOUT_8_UNCONNECTED : STD_LOGIC;
|
1139 |
|
|
signal NLW_blk00000003_blk00000096_ACOUT_7_UNCONNECTED : STD_LOGIC;
|
1140 |
|
|
signal NLW_blk00000003_blk00000096_ACOUT_6_UNCONNECTED : STD_LOGIC;
|
1141 |
|
|
signal NLW_blk00000003_blk00000096_ACOUT_5_UNCONNECTED : STD_LOGIC;
|
1142 |
|
|
signal NLW_blk00000003_blk00000096_ACOUT_4_UNCONNECTED : STD_LOGIC;
|
1143 |
|
|
signal NLW_blk00000003_blk00000096_ACOUT_3_UNCONNECTED : STD_LOGIC;
|
1144 |
|
|
signal NLW_blk00000003_blk00000096_ACOUT_2_UNCONNECTED : STD_LOGIC;
|
1145 |
|
|
signal NLW_blk00000003_blk00000096_ACOUT_1_UNCONNECTED : STD_LOGIC;
|
1146 |
|
|
signal NLW_blk00000003_blk00000096_ACOUT_0_UNCONNECTED : STD_LOGIC;
|
1147 |
|
|
signal NLW_blk00000003_blk00000096_CARRYOUT_3_UNCONNECTED : STD_LOGIC;
|
1148 |
|
|
signal NLW_blk00000003_blk00000096_CARRYOUT_2_UNCONNECTED : STD_LOGIC;
|
1149 |
|
|
signal NLW_blk00000003_blk00000096_CARRYOUT_1_UNCONNECTED : STD_LOGIC;
|
1150 |
|
|
signal NLW_blk00000003_blk00000096_CARRYOUT_0_UNCONNECTED : STD_LOGIC;
|
1151 |
|
|
begin
|
1152 |
|
|
sig00000043 <= sclr;
|
1153 |
|
|
rdy <= sig00000064;
|
1154 |
|
|
sig00000001 <= a(31);
|
1155 |
|
|
sig00000002 <= a(30);
|
1156 |
|
|
sig00000003 <= a(29);
|
1157 |
|
|
sig00000004 <= a(28);
|
1158 |
|
|
sig00000005 <= a(27);
|
1159 |
|
|
sig00000006 <= a(26);
|
1160 |
|
|
sig00000007 <= a(25);
|
1161 |
|
|
sig00000008 <= a(24);
|
1162 |
|
|
sig00000009 <= a(23);
|
1163 |
|
|
sig0000000a <= a(22);
|
1164 |
|
|
sig0000000b <= a(21);
|
1165 |
|
|
sig0000000c <= a(20);
|
1166 |
|
|
sig0000000d <= a(19);
|
1167 |
|
|
sig0000000e <= a(18);
|
1168 |
|
|
sig0000000f <= a(17);
|
1169 |
|
|
sig00000010 <= a(16);
|
1170 |
|
|
sig00000011 <= a(15);
|
1171 |
|
|
sig00000012 <= a(14);
|
1172 |
|
|
sig00000013 <= a(13);
|
1173 |
|
|
sig00000014 <= a(12);
|
1174 |
|
|
sig00000015 <= a(11);
|
1175 |
|
|
sig00000016 <= a(10);
|
1176 |
|
|
sig00000017 <= a(9);
|
1177 |
|
|
sig00000018 <= a(8);
|
1178 |
|
|
sig00000019 <= a(7);
|
1179 |
|
|
sig0000001a <= a(6);
|
1180 |
|
|
sig0000001b <= a(5);
|
1181 |
|
|
sig0000001c <= a(4);
|
1182 |
|
|
sig0000001d <= a(3);
|
1183 |
|
|
sig0000001e <= a(2);
|
1184 |
|
|
sig0000001f <= a(1);
|
1185 |
|
|
sig00000020 <= a(0);
|
1186 |
|
|
sig00000021 <= b(31);
|
1187 |
|
|
sig00000022 <= b(30);
|
1188 |
|
|
sig00000023 <= b(29);
|
1189 |
|
|
sig00000024 <= b(28);
|
1190 |
|
|
sig00000025 <= b(27);
|
1191 |
|
|
sig00000026 <= b(26);
|
1192 |
|
|
sig00000027 <= b(25);
|
1193 |
|
|
sig00000028 <= b(24);
|
1194 |
|
|
sig00000029 <= b(23);
|
1195 |
|
|
sig0000002a <= b(22);
|
1196 |
|
|
sig0000002b <= b(21);
|
1197 |
|
|
sig0000002c <= b(20);
|
1198 |
|
|
sig0000002d <= b(19);
|
1199 |
|
|
sig0000002e <= b(18);
|
1200 |
|
|
sig0000002f <= b(17);
|
1201 |
|
|
sig00000030 <= b(16);
|
1202 |
|
|
sig00000031 <= b(15);
|
1203 |
|
|
sig00000032 <= b(14);
|
1204 |
|
|
sig00000033 <= b(13);
|
1205 |
|
|
sig00000034 <= b(12);
|
1206 |
|
|
sig00000035 <= b(11);
|
1207 |
|
|
sig00000036 <= b(10);
|
1208 |
|
|
sig00000037 <= b(9);
|
1209 |
|
|
sig00000038 <= b(8);
|
1210 |
|
|
sig00000039 <= b(7);
|
1211 |
|
|
sig0000003a <= b(6);
|
1212 |
|
|
sig0000003b <= b(5);
|
1213 |
|
|
sig0000003c <= b(4);
|
1214 |
|
|
sig0000003d <= b(3);
|
1215 |
|
|
sig0000003e <= b(2);
|
1216 |
|
|
sig0000003f <= b(1);
|
1217 |
|
|
sig00000040 <= b(0);
|
1218 |
|
|
result(31) <= sig00000044;
|
1219 |
|
|
result(30) <= sig00000045;
|
1220 |
|
|
result(29) <= sig00000046;
|
1221 |
|
|
result(28) <= sig00000047;
|
1222 |
|
|
result(27) <= sig00000048;
|
1223 |
|
|
result(26) <= sig00000049;
|
1224 |
|
|
result(25) <= sig0000004a;
|
1225 |
|
|
result(24) <= sig0000004b;
|
1226 |
|
|
result(23) <= sig0000004c;
|
1227 |
|
|
result(22) <= sig0000004d;
|
1228 |
|
|
result(21) <= sig0000004e;
|
1229 |
|
|
result(20) <= sig0000004f;
|
1230 |
|
|
result(19) <= sig00000050;
|
1231 |
|
|
result(18) <= sig00000051;
|
1232 |
|
|
result(17) <= sig00000052;
|
1233 |
|
|
result(16) <= sig00000053;
|
1234 |
|
|
result(15) <= sig00000054;
|
1235 |
|
|
result(14) <= sig00000055;
|
1236 |
|
|
result(13) <= sig00000056;
|
1237 |
|
|
result(12) <= sig00000057;
|
1238 |
|
|
result(11) <= sig00000058;
|
1239 |
|
|
result(10) <= sig00000059;
|
1240 |
|
|
result(9) <= sig0000005a;
|
1241 |
|
|
result(8) <= sig0000005b;
|
1242 |
|
|
result(7) <= sig0000005c;
|
1243 |
|
|
result(6) <= sig0000005d;
|
1244 |
|
|
result(5) <= sig0000005e;
|
1245 |
|
|
result(4) <= sig0000005f;
|
1246 |
|
|
result(3) <= sig00000060;
|
1247 |
|
|
result(2) <= sig00000061;
|
1248 |
|
|
result(1) <= sig00000062;
|
1249 |
|
|
result(0) <= sig00000063;
|
1250 |
|
|
sig00000041 <= operation_nd;
|
1251 |
|
|
sig00000042 <= clk;
|
1252 |
|
|
blk00000001 : VCC
|
1253 |
|
|
port map (
|
1254 |
|
|
P => NLW_blk00000001_P_UNCONNECTED
|
1255 |
|
|
);
|
1256 |
|
|
blk00000002 : GND
|
1257 |
|
|
port map (
|
1258 |
|
|
G => NLW_blk00000002_G_UNCONNECTED
|
1259 |
|
|
);
|
1260 |
|
|
blk00000003_blk000002c4 : FDE
|
1261 |
|
|
generic map(
|
1262 |
|
|
INIT => '0'
|
1263 |
|
|
)
|
1264 |
|
|
port map (
|
1265 |
|
|
C => sig00000042,
|
1266 |
|
|
CE => blk00000003_sig00000067,
|
1267 |
|
|
D => blk00000003_sig000003ac,
|
1268 |
|
|
Q => blk00000003_sig00000369
|
1269 |
|
|
);
|
1270 |
|
|
blk00000003_blk000002c3 : SRLC16E
|
1271 |
|
|
generic map(
|
1272 |
|
|
INIT => X"0000"
|
1273 |
|
|
)
|
1274 |
|
|
port map (
|
1275 |
|
|
A0 => blk00000003_sig00000066,
|
1276 |
|
|
A1 => blk00000003_sig00000066,
|
1277 |
|
|
A2 => blk00000003_sig00000067,
|
1278 |
|
|
A3 => blk00000003_sig00000066,
|
1279 |
|
|
CE => blk00000003_sig00000067,
|
1280 |
|
|
CLK => sig00000042,
|
1281 |
|
|
D => blk00000003_sig0000038a,
|
1282 |
|
|
Q => blk00000003_sig000003ac,
|
1283 |
|
|
Q15 => NLW_blk00000003_blk000002c3_Q15_UNCONNECTED
|
1284 |
|
|
);
|
1285 |
|
|
blk00000003_blk000002c2 : FDE
|
1286 |
|
|
generic map(
|
1287 |
|
|
INIT => '0'
|
1288 |
|
|
)
|
1289 |
|
|
port map (
|
1290 |
|
|
C => sig00000042,
|
1291 |
|
|
CE => blk00000003_sig00000067,
|
1292 |
|
|
D => blk00000003_sig000003ab,
|
1293 |
|
|
Q => blk00000003_sig0000036b
|
1294 |
|
|
);
|
1295 |
|
|
blk00000003_blk000002c1 : SRLC16E
|
1296 |
|
|
generic map(
|
1297 |
|
|
INIT => X"0000"
|
1298 |
|
|
)
|
1299 |
|
|
port map (
|
1300 |
|
|
A0 => blk00000003_sig00000066,
|
1301 |
|
|
A1 => blk00000003_sig00000066,
|
1302 |
|
|
A2 => blk00000003_sig00000067,
|
1303 |
|
|
A3 => blk00000003_sig00000066,
|
1304 |
|
|
CE => blk00000003_sig00000067,
|
1305 |
|
|
CLK => sig00000042,
|
1306 |
|
|
D => blk00000003_sig0000033a,
|
1307 |
|
|
Q => blk00000003_sig000003ab,
|
1308 |
|
|
Q15 => NLW_blk00000003_blk000002c1_Q15_UNCONNECTED
|
1309 |
|
|
);
|
1310 |
|
|
blk00000003_blk000002c0 : FDE
|
1311 |
|
|
generic map(
|
1312 |
|
|
INIT => '0'
|
1313 |
|
|
)
|
1314 |
|
|
port map (
|
1315 |
|
|
C => sig00000042,
|
1316 |
|
|
CE => blk00000003_sig00000067,
|
1317 |
|
|
D => blk00000003_sig000003aa,
|
1318 |
|
|
Q => blk00000003_sig0000036a
|
1319 |
|
|
);
|
1320 |
|
|
blk00000003_blk000002bf : SRLC16E
|
1321 |
|
|
generic map(
|
1322 |
|
|
INIT => X"0000"
|
1323 |
|
|
)
|
1324 |
|
|
port map (
|
1325 |
|
|
A0 => blk00000003_sig00000066,
|
1326 |
|
|
A1 => blk00000003_sig00000066,
|
1327 |
|
|
A2 => blk00000003_sig00000067,
|
1328 |
|
|
A3 => blk00000003_sig00000066,
|
1329 |
|
|
CE => blk00000003_sig00000067,
|
1330 |
|
|
CLK => sig00000042,
|
1331 |
|
|
D => blk00000003_sig00000388,
|
1332 |
|
|
Q => blk00000003_sig000003aa,
|
1333 |
|
|
Q15 => NLW_blk00000003_blk000002bf_Q15_UNCONNECTED
|
1334 |
|
|
);
|
1335 |
|
|
blk00000003_blk000002be : FDE
|
1336 |
|
|
generic map(
|
1337 |
|
|
INIT => '0'
|
1338 |
|
|
)
|
1339 |
|
|
port map (
|
1340 |
|
|
C => sig00000042,
|
1341 |
|
|
CE => blk00000003_sig00000067,
|
1342 |
|
|
D => blk00000003_sig000003a9,
|
1343 |
|
|
Q => blk00000003_sig0000036c
|
1344 |
|
|
);
|
1345 |
|
|
blk00000003_blk000002bd : SRLC16E
|
1346 |
|
|
generic map(
|
1347 |
|
|
INIT => X"0000"
|
1348 |
|
|
)
|
1349 |
|
|
port map (
|
1350 |
|
|
A0 => blk00000003_sig00000066,
|
1351 |
|
|
A1 => blk00000003_sig00000066,
|
1352 |
|
|
A2 => blk00000003_sig00000066,
|
1353 |
|
|
A3 => blk00000003_sig00000066,
|
1354 |
|
|
CE => blk00000003_sig00000067,
|
1355 |
|
|
CLK => sig00000042,
|
1356 |
|
|
D => blk00000003_sig00000329,
|
1357 |
|
|
Q => blk00000003_sig000003a9,
|
1358 |
|
|
Q15 => NLW_blk00000003_blk000002bd_Q15_UNCONNECTED
|
1359 |
|
|
);
|
1360 |
|
|
blk00000003_blk000002bc : FDE
|
1361 |
|
|
generic map(
|
1362 |
|
|
INIT => '0'
|
1363 |
|
|
)
|
1364 |
|
|
port map (
|
1365 |
|
|
C => sig00000042,
|
1366 |
|
|
CE => blk00000003_sig00000067,
|
1367 |
|
|
D => blk00000003_sig000003a8,
|
1368 |
|
|
Q => blk00000003_sig000002e4
|
1369 |
|
|
);
|
1370 |
|
|
blk00000003_blk000002bb : SRLC16E
|
1371 |
|
|
generic map(
|
1372 |
|
|
INIT => X"0000"
|
1373 |
|
|
)
|
1374 |
|
|
port map (
|
1375 |
|
|
A0 => blk00000003_sig00000067,
|
1376 |
|
|
A1 => blk00000003_sig00000067,
|
1377 |
|
|
A2 => blk00000003_sig00000066,
|
1378 |
|
|
A3 => blk00000003_sig00000066,
|
1379 |
|
|
CE => blk00000003_sig00000067,
|
1380 |
|
|
CLK => sig00000042,
|
1381 |
|
|
D => blk00000003_sig00000338,
|
1382 |
|
|
Q => blk00000003_sig000003a8,
|
1383 |
|
|
Q15 => NLW_blk00000003_blk000002bb_Q15_UNCONNECTED
|
1384 |
|
|
);
|
1385 |
|
|
blk00000003_blk000002ba : FDE
|
1386 |
|
|
generic map(
|
1387 |
|
|
INIT => '0'
|
1388 |
|
|
)
|
1389 |
|
|
port map (
|
1390 |
|
|
C => sig00000042,
|
1391 |
|
|
CE => blk00000003_sig00000067,
|
1392 |
|
|
D => blk00000003_sig000003a7,
|
1393 |
|
|
Q => blk00000003_sig000002e8
|
1394 |
|
|
);
|
1395 |
|
|
blk00000003_blk000002b9 : SRLC16E
|
1396 |
|
|
generic map(
|
1397 |
|
|
INIT => X"0000"
|
1398 |
|
|
)
|
1399 |
|
|
port map (
|
1400 |
|
|
A0 => blk00000003_sig00000067,
|
1401 |
|
|
A1 => blk00000003_sig00000067,
|
1402 |
|
|
A2 => blk00000003_sig00000066,
|
1403 |
|
|
A3 => blk00000003_sig00000066,
|
1404 |
|
|
CE => blk00000003_sig00000067,
|
1405 |
|
|
CLK => sig00000042,
|
1406 |
|
|
D => blk00000003_sig00000337,
|
1407 |
|
|
Q => blk00000003_sig000003a7,
|
1408 |
|
|
Q15 => NLW_blk00000003_blk000002b9_Q15_UNCONNECTED
|
1409 |
|
|
);
|
1410 |
|
|
blk00000003_blk000002b8 : FDE
|
1411 |
|
|
generic map(
|
1412 |
|
|
INIT => '0'
|
1413 |
|
|
)
|
1414 |
|
|
port map (
|
1415 |
|
|
C => sig00000042,
|
1416 |
|
|
CE => blk00000003_sig00000067,
|
1417 |
|
|
D => blk00000003_sig000003a6,
|
1418 |
|
|
Q => blk00000003_sig000002ec
|
1419 |
|
|
);
|
1420 |
|
|
blk00000003_blk000002b7 : SRLC16E
|
1421 |
|
|
generic map(
|
1422 |
|
|
INIT => X"0000"
|
1423 |
|
|
)
|
1424 |
|
|
port map (
|
1425 |
|
|
A0 => blk00000003_sig00000067,
|
1426 |
|
|
A1 => blk00000003_sig00000067,
|
1427 |
|
|
A2 => blk00000003_sig00000066,
|
1428 |
|
|
A3 => blk00000003_sig00000066,
|
1429 |
|
|
CE => blk00000003_sig00000067,
|
1430 |
|
|
CLK => sig00000042,
|
1431 |
|
|
D => blk00000003_sig00000336,
|
1432 |
|
|
Q => blk00000003_sig000003a6,
|
1433 |
|
|
Q15 => NLW_blk00000003_blk000002b7_Q15_UNCONNECTED
|
1434 |
|
|
);
|
1435 |
|
|
blk00000003_blk000002b6 : FDE
|
1436 |
|
|
generic map(
|
1437 |
|
|
INIT => '0'
|
1438 |
|
|
)
|
1439 |
|
|
port map (
|
1440 |
|
|
C => sig00000042,
|
1441 |
|
|
CE => blk00000003_sig00000067,
|
1442 |
|
|
D => blk00000003_sig000003a5,
|
1443 |
|
|
Q => blk00000003_sig000002f0
|
1444 |
|
|
);
|
1445 |
|
|
blk00000003_blk000002b5 : SRLC16E
|
1446 |
|
|
generic map(
|
1447 |
|
|
INIT => X"0000"
|
1448 |
|
|
)
|
1449 |
|
|
port map (
|
1450 |
|
|
A0 => blk00000003_sig00000067,
|
1451 |
|
|
A1 => blk00000003_sig00000067,
|
1452 |
|
|
A2 => blk00000003_sig00000066,
|
1453 |
|
|
A3 => blk00000003_sig00000066,
|
1454 |
|
|
CE => blk00000003_sig00000067,
|
1455 |
|
|
CLK => sig00000042,
|
1456 |
|
|
D => blk00000003_sig00000335,
|
1457 |
|
|
Q => blk00000003_sig000003a5,
|
1458 |
|
|
Q15 => NLW_blk00000003_blk000002b5_Q15_UNCONNECTED
|
1459 |
|
|
);
|
1460 |
|
|
blk00000003_blk000002b4 : FDE
|
1461 |
|
|
generic map(
|
1462 |
|
|
INIT => '0'
|
1463 |
|
|
)
|
1464 |
|
|
port map (
|
1465 |
|
|
C => sig00000042,
|
1466 |
|
|
CE => blk00000003_sig00000067,
|
1467 |
|
|
D => blk00000003_sig000003a4,
|
1468 |
|
|
Q => blk00000003_sig000002f4
|
1469 |
|
|
);
|
1470 |
|
|
blk00000003_blk000002b3 : SRLC16E
|
1471 |
|
|
generic map(
|
1472 |
|
|
INIT => X"0000"
|
1473 |
|
|
)
|
1474 |
|
|
port map (
|
1475 |
|
|
A0 => blk00000003_sig00000067,
|
1476 |
|
|
A1 => blk00000003_sig00000067,
|
1477 |
|
|
A2 => blk00000003_sig00000066,
|
1478 |
|
|
A3 => blk00000003_sig00000066,
|
1479 |
|
|
CE => blk00000003_sig00000067,
|
1480 |
|
|
CLK => sig00000042,
|
1481 |
|
|
D => blk00000003_sig00000334,
|
1482 |
|
|
Q => blk00000003_sig000003a4,
|
1483 |
|
|
Q15 => NLW_blk00000003_blk000002b3_Q15_UNCONNECTED
|
1484 |
|
|
);
|
1485 |
|
|
blk00000003_blk000002b2 : FDE
|
1486 |
|
|
generic map(
|
1487 |
|
|
INIT => '0'
|
1488 |
|
|
)
|
1489 |
|
|
port map (
|
1490 |
|
|
C => sig00000042,
|
1491 |
|
|
CE => blk00000003_sig00000067,
|
1492 |
|
|
D => blk00000003_sig000003a3,
|
1493 |
|
|
Q => blk00000003_sig000002f8
|
1494 |
|
|
);
|
1495 |
|
|
blk00000003_blk000002b1 : SRLC16E
|
1496 |
|
|
generic map(
|
1497 |
|
|
INIT => X"0000"
|
1498 |
|
|
)
|
1499 |
|
|
port map (
|
1500 |
|
|
A0 => blk00000003_sig00000067,
|
1501 |
|
|
A1 => blk00000003_sig00000067,
|
1502 |
|
|
A2 => blk00000003_sig00000066,
|
1503 |
|
|
A3 => blk00000003_sig00000066,
|
1504 |
|
|
CE => blk00000003_sig00000067,
|
1505 |
|
|
CLK => sig00000042,
|
1506 |
|
|
D => blk00000003_sig00000333,
|
1507 |
|
|
Q => blk00000003_sig000003a3,
|
1508 |
|
|
Q15 => NLW_blk00000003_blk000002b1_Q15_UNCONNECTED
|
1509 |
|
|
);
|
1510 |
|
|
blk00000003_blk000002b0 : FDE
|
1511 |
|
|
generic map(
|
1512 |
|
|
INIT => '0'
|
1513 |
|
|
)
|
1514 |
|
|
port map (
|
1515 |
|
|
C => sig00000042,
|
1516 |
|
|
CE => blk00000003_sig00000067,
|
1517 |
|
|
D => blk00000003_sig000003a2,
|
1518 |
|
|
Q => blk00000003_sig000002fc
|
1519 |
|
|
);
|
1520 |
|
|
blk00000003_blk000002af : SRLC16E
|
1521 |
|
|
generic map(
|
1522 |
|
|
INIT => X"0000"
|
1523 |
|
|
)
|
1524 |
|
|
port map (
|
1525 |
|
|
A0 => blk00000003_sig00000067,
|
1526 |
|
|
A1 => blk00000003_sig00000067,
|
1527 |
|
|
A2 => blk00000003_sig00000066,
|
1528 |
|
|
A3 => blk00000003_sig00000066,
|
1529 |
|
|
CE => blk00000003_sig00000067,
|
1530 |
|
|
CLK => sig00000042,
|
1531 |
|
|
D => blk00000003_sig00000332,
|
1532 |
|
|
Q => blk00000003_sig000003a2,
|
1533 |
|
|
Q15 => NLW_blk00000003_blk000002af_Q15_UNCONNECTED
|
1534 |
|
|
);
|
1535 |
|
|
blk00000003_blk000002ae : FDE
|
1536 |
|
|
generic map(
|
1537 |
|
|
INIT => '0'
|
1538 |
|
|
)
|
1539 |
|
|
port map (
|
1540 |
|
|
C => sig00000042,
|
1541 |
|
|
CE => blk00000003_sig00000067,
|
1542 |
|
|
D => blk00000003_sig000003a1,
|
1543 |
|
|
Q => blk00000003_sig000002ff
|
1544 |
|
|
);
|
1545 |
|
|
blk00000003_blk000002ad : SRLC16E
|
1546 |
|
|
generic map(
|
1547 |
|
|
INIT => X"0000"
|
1548 |
|
|
)
|
1549 |
|
|
port map (
|
1550 |
|
|
A0 => blk00000003_sig00000067,
|
1551 |
|
|
A1 => blk00000003_sig00000067,
|
1552 |
|
|
A2 => blk00000003_sig00000066,
|
1553 |
|
|
A3 => blk00000003_sig00000066,
|
1554 |
|
|
CE => blk00000003_sig00000067,
|
1555 |
|
|
CLK => sig00000042,
|
1556 |
|
|
D => blk00000003_sig00000331,
|
1557 |
|
|
Q => blk00000003_sig000003a1,
|
1558 |
|
|
Q15 => NLW_blk00000003_blk000002ad_Q15_UNCONNECTED
|
1559 |
|
|
);
|
1560 |
|
|
blk00000003_blk000002ac : FDE
|
1561 |
|
|
generic map(
|
1562 |
|
|
INIT => '0'
|
1563 |
|
|
)
|
1564 |
|
|
port map (
|
1565 |
|
|
C => sig00000042,
|
1566 |
|
|
CE => blk00000003_sig00000067,
|
1567 |
|
|
D => blk00000003_sig000003a0,
|
1568 |
|
|
Q => blk00000003_sig0000038b
|
1569 |
|
|
);
|
1570 |
|
|
blk00000003_blk000002ab : SRLC16E
|
1571 |
|
|
generic map(
|
1572 |
|
|
INIT => X"0000"
|
1573 |
|
|
)
|
1574 |
|
|
port map (
|
1575 |
|
|
A0 => blk00000003_sig00000067,
|
1576 |
|
|
A1 => blk00000003_sig00000066,
|
1577 |
|
|
A2 => blk00000003_sig00000066,
|
1578 |
|
|
A3 => blk00000003_sig00000066,
|
1579 |
|
|
CE => blk00000003_sig00000067,
|
1580 |
|
|
CLK => sig00000042,
|
1581 |
|
|
D => blk00000003_sig0000026a,
|
1582 |
|
|
Q => blk00000003_sig000003a0,
|
1583 |
|
|
Q15 => NLW_blk00000003_blk000002ab_Q15_UNCONNECTED
|
1584 |
|
|
);
|
1585 |
|
|
blk00000003_blk000002aa : FDE
|
1586 |
|
|
generic map(
|
1587 |
|
|
INIT => '0'
|
1588 |
|
|
)
|
1589 |
|
|
port map (
|
1590 |
|
|
C => sig00000042,
|
1591 |
|
|
CE => blk00000003_sig00000067,
|
1592 |
|
|
D => blk00000003_sig0000039f,
|
1593 |
|
|
Q => blk00000003_sig000001a6
|
1594 |
|
|
);
|
1595 |
|
|
blk00000003_blk000002a9 : SRLC16E
|
1596 |
|
|
generic map(
|
1597 |
|
|
INIT => X"0000"
|
1598 |
|
|
)
|
1599 |
|
|
port map (
|
1600 |
|
|
A0 => blk00000003_sig00000066,
|
1601 |
|
|
A1 => blk00000003_sig00000066,
|
1602 |
|
|
A2 => blk00000003_sig00000066,
|
1603 |
|
|
A3 => blk00000003_sig00000066,
|
1604 |
|
|
CE => blk00000003_sig00000067,
|
1605 |
|
|
CLK => sig00000042,
|
1606 |
|
|
D => blk00000003_sig00000173,
|
1607 |
|
|
Q => blk00000003_sig0000039f,
|
1608 |
|
|
Q15 => NLW_blk00000003_blk000002a9_Q15_UNCONNECTED
|
1609 |
|
|
);
|
1610 |
|
|
blk00000003_blk000002a8 : FDE
|
1611 |
|
|
generic map(
|
1612 |
|
|
INIT => '0'
|
1613 |
|
|
)
|
1614 |
|
|
port map (
|
1615 |
|
|
C => sig00000042,
|
1616 |
|
|
CE => blk00000003_sig00000067,
|
1617 |
|
|
D => blk00000003_sig0000039e,
|
1618 |
|
|
Q => blk00000003_sig00000368
|
1619 |
|
|
);
|
1620 |
|
|
blk00000003_blk000002a7 : SRLC16E
|
1621 |
|
|
generic map(
|
1622 |
|
|
INIT => X"0000"
|
1623 |
|
|
)
|
1624 |
|
|
port map (
|
1625 |
|
|
A0 => blk00000003_sig00000067,
|
1626 |
|
|
A1 => blk00000003_sig00000067,
|
1627 |
|
|
A2 => blk00000003_sig00000067,
|
1628 |
|
|
A3 => blk00000003_sig00000066,
|
1629 |
|
|
CE => blk00000003_sig00000067,
|
1630 |
|
|
CLK => sig00000042,
|
1631 |
|
|
D => blk00000003_sig000000db,
|
1632 |
|
|
Q => blk00000003_sig0000039e,
|
1633 |
|
|
Q15 => NLW_blk00000003_blk000002a7_Q15_UNCONNECTED
|
1634 |
|
|
);
|
1635 |
|
|
blk00000003_blk000002a6 : MUXF7
|
1636 |
|
|
port map (
|
1637 |
|
|
I0 => blk00000003_sig0000039d,
|
1638 |
|
|
I1 => blk00000003_sig0000039c,
|
1639 |
|
|
S => blk00000003_sig0000034a,
|
1640 |
|
|
O => blk00000003_sig00000339
|
1641 |
|
|
);
|
1642 |
|
|
blk00000003_blk000002a5 : LUT6
|
1643 |
|
|
generic map(
|
1644 |
|
|
INIT => X"F5F4F4F401000000"
|
1645 |
|
|
)
|
1646 |
|
|
port map (
|
1647 |
|
|
I0 => blk00000003_sig0000033e,
|
1648 |
|
|
I1 => blk00000003_sig00000340,
|
1649 |
|
|
I2 => blk00000003_sig0000033c,
|
1650 |
|
|
I3 => blk00000003_sig00000346,
|
1651 |
|
|
I4 => blk00000003_sig00000342,
|
1652 |
|
|
I5 => blk00000003_sig00000348,
|
1653 |
|
|
O => blk00000003_sig0000039d
|
1654 |
|
|
);
|
1655 |
|
|
blk00000003_blk000002a4 : LUT6
|
1656 |
|
|
generic map(
|
1657 |
|
|
INIT => X"F5F4F5F501000101"
|
1658 |
|
|
)
|
1659 |
|
|
port map (
|
1660 |
|
|
I0 => blk00000003_sig0000033e,
|
1661 |
|
|
I1 => blk00000003_sig00000340,
|
1662 |
|
|
I2 => blk00000003_sig0000033c,
|
1663 |
|
|
I3 => blk00000003_sig00000346,
|
1664 |
|
|
I4 => blk00000003_sig00000342,
|
1665 |
|
|
I5 => blk00000003_sig00000348,
|
1666 |
|
|
O => blk00000003_sig0000039c
|
1667 |
|
|
);
|
1668 |
|
|
blk00000003_blk000002a3 : LUT5
|
1669 |
|
|
generic map(
|
1670 |
|
|
INIT => X"00000001"
|
1671 |
|
|
)
|
1672 |
|
|
port map (
|
1673 |
|
|
I0 => blk00000003_sig0000034c,
|
1674 |
|
|
I1 => blk00000003_sig0000034d,
|
1675 |
|
|
I2 => blk00000003_sig0000034e,
|
1676 |
|
|
I3 => blk00000003_sig0000034f,
|
1677 |
|
|
I4 => blk00000003_sig00000350,
|
1678 |
|
|
O => blk00000003_sig00000283
|
1679 |
|
|
);
|
1680 |
|
|
blk00000003_blk000002a2 : LUT5
|
1681 |
|
|
generic map(
|
1682 |
|
|
INIT => X"00800200"
|
1683 |
|
|
)
|
1684 |
|
|
port map (
|
1685 |
|
|
I0 => blk00000003_sig0000034c,
|
1686 |
|
|
I1 => blk00000003_sig0000034d,
|
1687 |
|
|
I2 => blk00000003_sig0000034e,
|
1688 |
|
|
I3 => blk00000003_sig0000034f,
|
1689 |
|
|
I4 => blk00000003_sig00000350,
|
1690 |
|
|
O => blk00000003_sig0000027a
|
1691 |
|
|
);
|
1692 |
|
|
blk00000003_blk000002a1 : LUT6
|
1693 |
|
|
generic map(
|
1694 |
|
|
INIT => X"8000000000000002"
|
1695 |
|
|
)
|
1696 |
|
|
port map (
|
1697 |
|
|
I0 => blk00000003_sig0000034c,
|
1698 |
|
|
I1 => blk00000003_sig0000034d,
|
1699 |
|
|
I2 => blk00000003_sig0000034e,
|
1700 |
|
|
I3 => blk00000003_sig0000034f,
|
1701 |
|
|
I4 => blk00000003_sig00000350,
|
1702 |
|
|
I5 => blk00000003_sig00000351,
|
1703 |
|
|
O => blk00000003_sig00000282
|
1704 |
|
|
);
|
1705 |
|
|
blk00000003_blk000002a0 : LUT6
|
1706 |
|
|
generic map(
|
1707 |
|
|
INIT => X"4001000000010004"
|
1708 |
|
|
)
|
1709 |
|
|
port map (
|
1710 |
|
|
I0 => blk00000003_sig0000034c,
|
1711 |
|
|
I1 => blk00000003_sig0000034d,
|
1712 |
|
|
I2 => blk00000003_sig0000034e,
|
1713 |
|
|
I3 => blk00000003_sig0000034f,
|
1714 |
|
|
I4 => blk00000003_sig00000350,
|
1715 |
|
|
I5 => blk00000003_sig00000351,
|
1716 |
|
|
O => blk00000003_sig00000281
|
1717 |
|
|
);
|
1718 |
|
|
blk00000003_blk0000029f : LUT6
|
1719 |
|
|
generic map(
|
1720 |
|
|
INIT => X"0400100000100040"
|
1721 |
|
|
)
|
1722 |
|
|
port map (
|
1723 |
|
|
I0 => blk00000003_sig0000034c,
|
1724 |
|
|
I1 => blk00000003_sig0000034d,
|
1725 |
|
|
I2 => blk00000003_sig0000034e,
|
1726 |
|
|
I3 => blk00000003_sig0000034f,
|
1727 |
|
|
I4 => blk00000003_sig00000350,
|
1728 |
|
|
I5 => blk00000003_sig00000351,
|
1729 |
|
|
O => blk00000003_sig0000027d
|
1730 |
|
|
);
|
1731 |
|
|
blk00000003_blk0000029e : LUT6
|
1732 |
|
|
generic map(
|
1733 |
|
|
INIT => X"0200080000200080"
|
1734 |
|
|
)
|
1735 |
|
|
port map (
|
1736 |
|
|
I0 => blk00000003_sig0000034c,
|
1737 |
|
|
I1 => blk00000003_sig0000034d,
|
1738 |
|
|
I2 => blk00000003_sig0000034e,
|
1739 |
|
|
I3 => blk00000003_sig0000034f,
|
1740 |
|
|
I4 => blk00000003_sig00000350,
|
1741 |
|
|
I5 => blk00000003_sig00000351,
|
1742 |
|
|
O => blk00000003_sig0000027c
|
1743 |
|
|
);
|
1744 |
|
|
blk00000003_blk0000029d : LUT6
|
1745 |
|
|
generic map(
|
1746 |
|
|
INIT => X"0100040000400100"
|
1747 |
|
|
)
|
1748 |
|
|
port map (
|
1749 |
|
|
I0 => blk00000003_sig0000034c,
|
1750 |
|
|
I1 => blk00000003_sig0000034d,
|
1751 |
|
|
I2 => blk00000003_sig0000034e,
|
1752 |
|
|
I3 => blk00000003_sig0000034f,
|
1753 |
|
|
I4 => blk00000003_sig00000350,
|
1754 |
|
|
I5 => blk00000003_sig00000351,
|
1755 |
|
|
O => blk00000003_sig0000027b
|
1756 |
|
|
);
|
1757 |
|
|
blk00000003_blk0000029c : LUT6
|
1758 |
|
|
generic map(
|
1759 |
|
|
INIT => X"0040010001000400"
|
1760 |
|
|
)
|
1761 |
|
|
port map (
|
1762 |
|
|
I0 => blk00000003_sig0000034c,
|
1763 |
|
|
I1 => blk00000003_sig0000034d,
|
1764 |
|
|
I2 => blk00000003_sig0000034e,
|
1765 |
|
|
I3 => blk00000003_sig0000034f,
|
1766 |
|
|
I4 => blk00000003_sig00000350,
|
1767 |
|
|
I5 => blk00000003_sig00000351,
|
1768 |
|
|
O => blk00000003_sig00000279
|
1769 |
|
|
);
|
1770 |
|
|
blk00000003_blk0000029b : LUT6
|
1771 |
|
|
generic map(
|
1772 |
|
|
INIT => X"0200080000200080"
|
1773 |
|
|
)
|
1774 |
|
|
port map (
|
1775 |
|
|
I0 => blk00000003_sig0000034c,
|
1776 |
|
|
I1 => blk00000003_sig0000034d,
|
1777 |
|
|
I2 => blk00000003_sig0000034f,
|
1778 |
|
|
I3 => blk00000003_sig0000034e,
|
1779 |
|
|
I4 => blk00000003_sig00000350,
|
1780 |
|
|
I5 => blk00000003_sig00000351,
|
1781 |
|
|
O => blk00000003_sig00000278
|
1782 |
|
|
);
|
1783 |
|
|
blk00000003_blk0000029a : LUT6
|
1784 |
|
|
generic map(
|
1785 |
|
|
INIT => X"0010004004001000"
|
1786 |
|
|
)
|
1787 |
|
|
port map (
|
1788 |
|
|
I0 => blk00000003_sig0000034c,
|
1789 |
|
|
I1 => blk00000003_sig0000034d,
|
1790 |
|
|
I2 => blk00000003_sig0000034e,
|
1791 |
|
|
I3 => blk00000003_sig0000034f,
|
1792 |
|
|
I4 => blk00000003_sig00000350,
|
1793 |
|
|
I5 => blk00000003_sig00000351,
|
1794 |
|
|
O => blk00000003_sig00000277
|
1795 |
|
|
);
|
1796 |
|
|
blk00000003_blk00000299 : LUT6
|
1797 |
|
|
generic map(
|
1798 |
|
|
INIT => X"0200080000200080"
|
1799 |
|
|
)
|
1800 |
|
|
port map (
|
1801 |
|
|
I0 => blk00000003_sig0000034c,
|
1802 |
|
|
I1 => blk00000003_sig0000034f,
|
1803 |
|
|
I2 => blk00000003_sig0000034e,
|
1804 |
|
|
I3 => blk00000003_sig0000034d,
|
1805 |
|
|
I4 => blk00000003_sig00000351,
|
1806 |
|
|
I5 => blk00000003_sig00000350,
|
1807 |
|
|
O => blk00000003_sig00000276
|
1808 |
|
|
);
|
1809 |
|
|
blk00000003_blk00000298 : LUT6
|
1810 |
|
|
generic map(
|
1811 |
|
|
INIT => X"2000800000020008"
|
1812 |
|
|
)
|
1813 |
|
|
port map (
|
1814 |
|
|
I0 => blk00000003_sig0000034c,
|
1815 |
|
|
I1 => blk00000003_sig0000034d,
|
1816 |
|
|
I2 => blk00000003_sig0000034e,
|
1817 |
|
|
I3 => blk00000003_sig0000034f,
|
1818 |
|
|
I4 => blk00000003_sig00000350,
|
1819 |
|
|
I5 => blk00000003_sig00000351,
|
1820 |
|
|
O => blk00000003_sig00000280
|
1821 |
|
|
);
|
1822 |
|
|
blk00000003_blk00000297 : LUT6
|
1823 |
|
|
generic map(
|
1824 |
|
|
INIT => X"1000400000040010"
|
1825 |
|
|
)
|
1826 |
|
|
port map (
|
1827 |
|
|
I0 => blk00000003_sig0000034c,
|
1828 |
|
|
I1 => blk00000003_sig0000034d,
|
1829 |
|
|
I2 => blk00000003_sig0000034e,
|
1830 |
|
|
I3 => blk00000003_sig0000034f,
|
1831 |
|
|
I4 => blk00000003_sig00000350,
|
1832 |
|
|
I5 => blk00000003_sig00000351,
|
1833 |
|
|
O => blk00000003_sig0000027f
|
1834 |
|
|
);
|
1835 |
|
|
blk00000003_blk00000296 : LUT6
|
1836 |
|
|
generic map(
|
1837 |
|
|
INIT => X"0010004004001000"
|
1838 |
|
|
)
|
1839 |
|
|
port map (
|
1840 |
|
|
I0 => blk00000003_sig0000034c,
|
1841 |
|
|
I1 => blk00000003_sig0000034d,
|
1842 |
|
|
I2 => blk00000003_sig0000034e,
|
1843 |
|
|
I3 => blk00000003_sig00000351,
|
1844 |
|
|
I4 => blk00000003_sig00000350,
|
1845 |
|
|
I5 => blk00000003_sig0000034f,
|
1846 |
|
|
O => blk00000003_sig00000275
|
1847 |
|
|
);
|
1848 |
|
|
blk00000003_blk00000295 : LUT6
|
1849 |
|
|
generic map(
|
1850 |
|
|
INIT => X"0800200000080020"
|
1851 |
|
|
)
|
1852 |
|
|
port map (
|
1853 |
|
|
I0 => blk00000003_sig0000034c,
|
1854 |
|
|
I1 => blk00000003_sig0000034d,
|
1855 |
|
|
I2 => blk00000003_sig0000034e,
|
1856 |
|
|
I3 => blk00000003_sig0000034f,
|
1857 |
|
|
I4 => blk00000003_sig00000350,
|
1858 |
|
|
I5 => blk00000003_sig00000351,
|
1859 |
|
|
O => blk00000003_sig0000027e
|
1860 |
|
|
);
|
1861 |
|
|
blk00000003_blk00000294 : LUT6
|
1862 |
|
|
generic map(
|
1863 |
|
|
INIT => X"0200080000200080"
|
1864 |
|
|
)
|
1865 |
|
|
port map (
|
1866 |
|
|
I0 => blk00000003_sig0000034c,
|
1867 |
|
|
I1 => blk00000003_sig0000034d,
|
1868 |
|
|
I2 => blk00000003_sig00000351,
|
1869 |
|
|
I3 => blk00000003_sig0000034e,
|
1870 |
|
|
I4 => blk00000003_sig00000350,
|
1871 |
|
|
I5 => blk00000003_sig0000034f,
|
1872 |
|
|
O => blk00000003_sig00000274
|
1873 |
|
|
);
|
1874 |
|
|
blk00000003_blk00000293 : LUT6
|
1875 |
|
|
generic map(
|
1876 |
|
|
INIT => X"0818181818181010"
|
1877 |
|
|
)
|
1878 |
|
|
port map (
|
1879 |
|
|
I0 => blk00000003_sig0000034f,
|
1880 |
|
|
I1 => blk00000003_sig00000350,
|
1881 |
|
|
I2 => blk00000003_sig00000351,
|
1882 |
|
|
I3 => blk00000003_sig0000034c,
|
1883 |
|
|
I4 => blk00000003_sig0000034d,
|
1884 |
|
|
I5 => blk00000003_sig0000034e,
|
1885 |
|
|
O => blk00000003_sig00000376
|
1886 |
|
|
);
|
1887 |
|
|
blk00000003_blk00000292 : LUT6
|
1888 |
|
|
generic map(
|
1889 |
|
|
INIT => X"666666666666666A"
|
1890 |
|
|
)
|
1891 |
|
|
port map (
|
1892 |
|
|
I0 => blk00000003_sig00000350,
|
1893 |
|
|
I1 => blk00000003_sig00000351,
|
1894 |
|
|
I2 => blk00000003_sig0000034e,
|
1895 |
|
|
I3 => blk00000003_sig0000034f,
|
1896 |
|
|
I4 => blk00000003_sig0000034d,
|
1897 |
|
|
I5 => blk00000003_sig0000034c,
|
1898 |
|
|
O => blk00000003_sig00000372
|
1899 |
|
|
);
|
1900 |
|
|
blk00000003_blk00000291 : INV
|
1901 |
|
|
port map (
|
1902 |
|
|
I => blk00000003_sig00000372,
|
1903 |
|
|
O => blk00000003_sig0000039b
|
1904 |
|
|
);
|
1905 |
|
|
blk00000003_blk00000290 : INV
|
1906 |
|
|
port map (
|
1907 |
|
|
I => blk00000003_sig000002e4,
|
1908 |
|
|
O => blk00000003_sig000002e2
|
1909 |
|
|
);
|
1910 |
|
|
blk00000003_blk0000028f : INV
|
1911 |
|
|
port map (
|
1912 |
|
|
I => blk00000003_sig000002e8,
|
1913 |
|
|
O => blk00000003_sig000002e6
|
1914 |
|
|
);
|
1915 |
|
|
blk00000003_blk0000028e : INV
|
1916 |
|
|
port map (
|
1917 |
|
|
I => blk00000003_sig000002ec,
|
1918 |
|
|
O => blk00000003_sig000002ea
|
1919 |
|
|
);
|
1920 |
|
|
blk00000003_blk0000028d : INV
|
1921 |
|
|
port map (
|
1922 |
|
|
I => blk00000003_sig000000d3,
|
1923 |
|
|
O => blk00000003_sig000000d2
|
1924 |
|
|
);
|
1925 |
|
|
blk00000003_blk0000028c : FD
|
1926 |
|
|
generic map(
|
1927 |
|
|
INIT => '0'
|
1928 |
|
|
)
|
1929 |
|
|
port map (
|
1930 |
|
|
C => sig00000042,
|
1931 |
|
|
D => blk00000003_sig0000039b,
|
1932 |
|
|
Q => blk00000003_sig0000021e
|
1933 |
|
|
);
|
1934 |
|
|
blk00000003_blk0000028b : FD
|
1935 |
|
|
generic map(
|
1936 |
|
|
INIT => '0'
|
1937 |
|
|
)
|
1938 |
|
|
port map (
|
1939 |
|
|
C => sig00000042,
|
1940 |
|
|
D => blk00000003_sig0000039a,
|
1941 |
|
|
Q => blk00000003_sig0000021f
|
1942 |
|
|
);
|
1943 |
|
|
blk00000003_blk0000028a : LUT2
|
1944 |
|
|
generic map(
|
1945 |
|
|
INIT => X"2"
|
1946 |
|
|
)
|
1947 |
|
|
port map (
|
1948 |
|
|
I0 => blk00000003_sig00000386,
|
1949 |
|
|
I1 => blk00000003_sig00000372,
|
1950 |
|
|
O => blk00000003_sig0000039a
|
1951 |
|
|
);
|
1952 |
|
|
blk00000003_blk00000289 : FD
|
1953 |
|
|
generic map(
|
1954 |
|
|
INIT => '0'
|
1955 |
|
|
)
|
1956 |
|
|
port map (
|
1957 |
|
|
C => sig00000042,
|
1958 |
|
|
D => blk00000003_sig00000399,
|
1959 |
|
|
Q => blk00000003_sig00000220
|
1960 |
|
|
);
|
1961 |
|
|
blk00000003_blk00000288 : LUT2
|
1962 |
|
|
generic map(
|
1963 |
|
|
INIT => X"2"
|
1964 |
|
|
)
|
1965 |
|
|
port map (
|
1966 |
|
|
I0 => blk00000003_sig00000385,
|
1967 |
|
|
I1 => blk00000003_sig00000372,
|
1968 |
|
|
O => blk00000003_sig00000399
|
1969 |
|
|
);
|
1970 |
|
|
blk00000003_blk00000287 : FD
|
1971 |
|
|
generic map(
|
1972 |
|
|
INIT => '0'
|
1973 |
|
|
)
|
1974 |
|
|
port map (
|
1975 |
|
|
C => sig00000042,
|
1976 |
|
|
D => blk00000003_sig00000398,
|
1977 |
|
|
Q => blk00000003_sig00000221
|
1978 |
|
|
);
|
1979 |
|
|
blk00000003_blk00000286 : LUT2
|
1980 |
|
|
generic map(
|
1981 |
|
|
INIT => X"2"
|
1982 |
|
|
)
|
1983 |
|
|
port map (
|
1984 |
|
|
I0 => blk00000003_sig00000384,
|
1985 |
|
|
I1 => blk00000003_sig00000372,
|
1986 |
|
|
O => blk00000003_sig00000398
|
1987 |
|
|
);
|
1988 |
|
|
blk00000003_blk00000285 : FD
|
1989 |
|
|
generic map(
|
1990 |
|
|
INIT => '0'
|
1991 |
|
|
)
|
1992 |
|
|
port map (
|
1993 |
|
|
C => sig00000042,
|
1994 |
|
|
D => blk00000003_sig00000397,
|
1995 |
|
|
Q => blk00000003_sig00000222
|
1996 |
|
|
);
|
1997 |
|
|
blk00000003_blk00000284 : LUT2
|
1998 |
|
|
generic map(
|
1999 |
|
|
INIT => X"2"
|
2000 |
|
|
)
|
2001 |
|
|
port map (
|
2002 |
|
|
I0 => blk00000003_sig00000383,
|
2003 |
|
|
I1 => blk00000003_sig00000372,
|
2004 |
|
|
O => blk00000003_sig00000397
|
2005 |
|
|
);
|
2006 |
|
|
blk00000003_blk00000283 : FD
|
2007 |
|
|
generic map(
|
2008 |
|
|
INIT => '0'
|
2009 |
|
|
)
|
2010 |
|
|
port map (
|
2011 |
|
|
C => sig00000042,
|
2012 |
|
|
D => blk00000003_sig00000396,
|
2013 |
|
|
Q => blk00000003_sig00000223
|
2014 |
|
|
);
|
2015 |
|
|
blk00000003_blk00000282 : LUT2
|
2016 |
|
|
generic map(
|
2017 |
|
|
INIT => X"2"
|
2018 |
|
|
)
|
2019 |
|
|
port map (
|
2020 |
|
|
I0 => blk00000003_sig00000382,
|
2021 |
|
|
I1 => blk00000003_sig00000372,
|
2022 |
|
|
O => blk00000003_sig00000396
|
2023 |
|
|
);
|
2024 |
|
|
blk00000003_blk00000281 : FD
|
2025 |
|
|
generic map(
|
2026 |
|
|
INIT => '0'
|
2027 |
|
|
)
|
2028 |
|
|
port map (
|
2029 |
|
|
C => sig00000042,
|
2030 |
|
|
D => blk00000003_sig00000395,
|
2031 |
|
|
Q => blk00000003_sig00000224
|
2032 |
|
|
);
|
2033 |
|
|
blk00000003_blk00000280 : LUT2
|
2034 |
|
|
generic map(
|
2035 |
|
|
INIT => X"2"
|
2036 |
|
|
)
|
2037 |
|
|
port map (
|
2038 |
|
|
I0 => blk00000003_sig00000381,
|
2039 |
|
|
I1 => blk00000003_sig00000372,
|
2040 |
|
|
O => blk00000003_sig00000395
|
2041 |
|
|
);
|
2042 |
|
|
blk00000003_blk0000027f : FD
|
2043 |
|
|
generic map(
|
2044 |
|
|
INIT => '0'
|
2045 |
|
|
)
|
2046 |
|
|
port map (
|
2047 |
|
|
C => sig00000042,
|
2048 |
|
|
D => blk00000003_sig00000394,
|
2049 |
|
|
Q => blk00000003_sig00000225
|
2050 |
|
|
);
|
2051 |
|
|
blk00000003_blk0000027e : LUT2
|
2052 |
|
|
generic map(
|
2053 |
|
|
INIT => X"2"
|
2054 |
|
|
)
|
2055 |
|
|
port map (
|
2056 |
|
|
I0 => blk00000003_sig00000380,
|
2057 |
|
|
I1 => blk00000003_sig00000372,
|
2058 |
|
|
O => blk00000003_sig00000394
|
2059 |
|
|
);
|
2060 |
|
|
blk00000003_blk0000027d : FD
|
2061 |
|
|
generic map(
|
2062 |
|
|
INIT => '0'
|
2063 |
|
|
)
|
2064 |
|
|
port map (
|
2065 |
|
|
C => sig00000042,
|
2066 |
|
|
D => blk00000003_sig00000393,
|
2067 |
|
|
Q => blk00000003_sig00000226
|
2068 |
|
|
);
|
2069 |
|
|
blk00000003_blk0000027c : LUT2
|
2070 |
|
|
generic map(
|
2071 |
|
|
INIT => X"2"
|
2072 |
|
|
)
|
2073 |
|
|
port map (
|
2074 |
|
|
I0 => blk00000003_sig0000037f,
|
2075 |
|
|
I1 => blk00000003_sig00000372,
|
2076 |
|
|
O => blk00000003_sig00000393
|
2077 |
|
|
);
|
2078 |
|
|
blk00000003_blk0000027b : FD
|
2079 |
|
|
generic map(
|
2080 |
|
|
INIT => '0'
|
2081 |
|
|
)
|
2082 |
|
|
port map (
|
2083 |
|
|
C => sig00000042,
|
2084 |
|
|
D => blk00000003_sig00000392,
|
2085 |
|
|
Q => blk00000003_sig00000227
|
2086 |
|
|
);
|
2087 |
|
|
blk00000003_blk0000027a : LUT2
|
2088 |
|
|
generic map(
|
2089 |
|
|
INIT => X"2"
|
2090 |
|
|
)
|
2091 |
|
|
port map (
|
2092 |
|
|
I0 => blk00000003_sig0000037e,
|
2093 |
|
|
I1 => blk00000003_sig00000372,
|
2094 |
|
|
O => blk00000003_sig00000392
|
2095 |
|
|
);
|
2096 |
|
|
blk00000003_blk00000279 : FD
|
2097 |
|
|
generic map(
|
2098 |
|
|
INIT => '0'
|
2099 |
|
|
)
|
2100 |
|
|
port map (
|
2101 |
|
|
C => sig00000042,
|
2102 |
|
|
D => blk00000003_sig00000391,
|
2103 |
|
|
Q => blk00000003_sig00000228
|
2104 |
|
|
);
|
2105 |
|
|
blk00000003_blk00000278 : LUT2
|
2106 |
|
|
generic map(
|
2107 |
|
|
INIT => X"2"
|
2108 |
|
|
)
|
2109 |
|
|
port map (
|
2110 |
|
|
I0 => blk00000003_sig0000037d,
|
2111 |
|
|
I1 => blk00000003_sig00000372,
|
2112 |
|
|
O => blk00000003_sig00000391
|
2113 |
|
|
);
|
2114 |
|
|
blk00000003_blk00000277 : FD
|
2115 |
|
|
generic map(
|
2116 |
|
|
INIT => '0'
|
2117 |
|
|
)
|
2118 |
|
|
port map (
|
2119 |
|
|
C => sig00000042,
|
2120 |
|
|
D => blk00000003_sig00000390,
|
2121 |
|
|
Q => blk00000003_sig00000229
|
2122 |
|
|
);
|
2123 |
|
|
blk00000003_blk00000276 : LUT2
|
2124 |
|
|
generic map(
|
2125 |
|
|
INIT => X"2"
|
2126 |
|
|
)
|
2127 |
|
|
port map (
|
2128 |
|
|
I0 => blk00000003_sig0000037c,
|
2129 |
|
|
I1 => blk00000003_sig00000372,
|
2130 |
|
|
O => blk00000003_sig00000390
|
2131 |
|
|
);
|
2132 |
|
|
blk00000003_blk00000275 : FD
|
2133 |
|
|
generic map(
|
2134 |
|
|
INIT => '0'
|
2135 |
|
|
)
|
2136 |
|
|
port map (
|
2137 |
|
|
C => sig00000042,
|
2138 |
|
|
D => blk00000003_sig0000038f,
|
2139 |
|
|
Q => blk00000003_sig0000022a
|
2140 |
|
|
);
|
2141 |
|
|
blk00000003_blk00000274 : LUT2
|
2142 |
|
|
generic map(
|
2143 |
|
|
INIT => X"2"
|
2144 |
|
|
)
|
2145 |
|
|
port map (
|
2146 |
|
|
I0 => blk00000003_sig0000037b,
|
2147 |
|
|
I1 => blk00000003_sig00000372,
|
2148 |
|
|
O => blk00000003_sig0000038f
|
2149 |
|
|
);
|
2150 |
|
|
blk00000003_blk00000273 : FD
|
2151 |
|
|
generic map(
|
2152 |
|
|
INIT => '0'
|
2153 |
|
|
)
|
2154 |
|
|
port map (
|
2155 |
|
|
C => sig00000042,
|
2156 |
|
|
D => blk00000003_sig0000038e,
|
2157 |
|
|
Q => blk00000003_sig0000022b
|
2158 |
|
|
);
|
2159 |
|
|
blk00000003_blk00000272 : LUT2
|
2160 |
|
|
generic map(
|
2161 |
|
|
INIT => X"2"
|
2162 |
|
|
)
|
2163 |
|
|
port map (
|
2164 |
|
|
I0 => blk00000003_sig0000037a,
|
2165 |
|
|
I1 => blk00000003_sig00000372,
|
2166 |
|
|
O => blk00000003_sig0000038e
|
2167 |
|
|
);
|
2168 |
|
|
blk00000003_blk00000271 : FD
|
2169 |
|
|
generic map(
|
2170 |
|
|
INIT => '0'
|
2171 |
|
|
)
|
2172 |
|
|
port map (
|
2173 |
|
|
C => sig00000042,
|
2174 |
|
|
D => blk00000003_sig0000038d,
|
2175 |
|
|
Q => blk00000003_sig0000022c
|
2176 |
|
|
);
|
2177 |
|
|
blk00000003_blk00000270 : LUT2
|
2178 |
|
|
generic map(
|
2179 |
|
|
INIT => X"E"
|
2180 |
|
|
)
|
2181 |
|
|
port map (
|
2182 |
|
|
I0 => blk00000003_sig00000379,
|
2183 |
|
|
I1 => blk00000003_sig00000372,
|
2184 |
|
|
O => blk00000003_sig0000038d
|
2185 |
|
|
);
|
2186 |
|
|
blk00000003_blk0000026f : LUT2
|
2187 |
|
|
generic map(
|
2188 |
|
|
INIT => X"7"
|
2189 |
|
|
)
|
2190 |
|
|
port map (
|
2191 |
|
|
I0 => blk00000003_sig00000321,
|
2192 |
|
|
I1 => blk00000003_sig0000031c,
|
2193 |
|
|
O => blk00000003_sig0000026e
|
2194 |
|
|
);
|
2195 |
|
|
blk00000003_blk0000026e : LUT6
|
2196 |
|
|
generic map(
|
2197 |
|
|
INIT => X"0000000100000000"
|
2198 |
|
|
)
|
2199 |
|
|
port map (
|
2200 |
|
|
I0 => blk00000003_sig00000263,
|
2201 |
|
|
I1 => blk00000003_sig00000262,
|
2202 |
|
|
I2 => blk00000003_sig00000261,
|
2203 |
|
|
I3 => blk00000003_sig00000260,
|
2204 |
|
|
I4 => blk00000003_sig0000038c,
|
2205 |
|
|
I5 => blk00000003_sig00000378,
|
2206 |
|
|
O => blk00000003_sig00000272
|
2207 |
|
|
);
|
2208 |
|
|
blk00000003_blk0000026d : LUT4
|
2209 |
|
|
generic map(
|
2210 |
|
|
INIT => X"FFEF"
|
2211 |
|
|
)
|
2212 |
|
|
port map (
|
2213 |
|
|
I0 => blk00000003_sig0000025c,
|
2214 |
|
|
I1 => blk00000003_sig0000025b,
|
2215 |
|
|
I2 => blk00000003_sig0000038b,
|
2216 |
|
|
I3 => blk00000003_sig00000264,
|
2217 |
|
|
O => blk00000003_sig0000038c
|
2218 |
|
|
);
|
2219 |
|
|
blk00000003_blk0000026c : LUT1
|
2220 |
|
|
generic map(
|
2221 |
|
|
INIT => X"2"
|
2222 |
|
|
)
|
2223 |
|
|
port map (
|
2224 |
|
|
I0 => blk00000003_sig00000372,
|
2225 |
|
|
O => blk00000003_sig00000268
|
2226 |
|
|
);
|
2227 |
|
|
blk00000003_blk0000026b : LUT2
|
2228 |
|
|
generic map(
|
2229 |
|
|
INIT => X"E"
|
2230 |
|
|
)
|
2231 |
|
|
port map (
|
2232 |
|
|
I0 => blk00000003_sig00000342,
|
2233 |
|
|
I1 => blk00000003_sig0000033e,
|
2234 |
|
|
O => blk00000003_sig00000389
|
2235 |
|
|
);
|
2236 |
|
|
blk00000003_blk0000026a : FDRS
|
2237 |
|
|
generic map(
|
2238 |
|
|
INIT => '0'
|
2239 |
|
|
)
|
2240 |
|
|
port map (
|
2241 |
|
|
C => sig00000042,
|
2242 |
|
|
D => blk00000003_sig00000389,
|
2243 |
|
|
R => blk00000003_sig0000033c,
|
2244 |
|
|
S => blk00000003_sig00000340,
|
2245 |
|
|
Q => blk00000003_sig0000038a
|
2246 |
|
|
);
|
2247 |
|
|
blk00000003_blk00000269 : LUT4
|
2248 |
|
|
generic map(
|
2249 |
|
|
INIT => X"1054"
|
2250 |
|
|
)
|
2251 |
|
|
port map (
|
2252 |
|
|
I0 => blk00000003_sig0000033e,
|
2253 |
|
|
I1 => blk00000003_sig00000340,
|
2254 |
|
|
I2 => blk00000003_sig00000342,
|
2255 |
|
|
I3 => blk00000003_sig00000344,
|
2256 |
|
|
O => blk00000003_sig00000387
|
2257 |
|
|
);
|
2258 |
|
|
blk00000003_blk00000268 : FDS
|
2259 |
|
|
generic map(
|
2260 |
|
|
INIT => '0'
|
2261 |
|
|
)
|
2262 |
|
|
port map (
|
2263 |
|
|
C => sig00000042,
|
2264 |
|
|
D => blk00000003_sig00000387,
|
2265 |
|
|
S => blk00000003_sig0000033c,
|
2266 |
|
|
Q => blk00000003_sig00000388
|
2267 |
|
|
);
|
2268 |
|
|
blk00000003_blk00000267 : LUT3
|
2269 |
|
|
generic map(
|
2270 |
|
|
INIT => X"E4"
|
2271 |
|
|
)
|
2272 |
|
|
port map (
|
2273 |
|
|
I0 => blk00000003_sig000002b4,
|
2274 |
|
|
I1 => blk00000003_sig000000dc,
|
2275 |
|
|
I2 => blk00000003_sig000000f3,
|
2276 |
|
|
O => blk00000003_sig00000386
|
2277 |
|
|
);
|
2278 |
|
|
blk00000003_blk00000266 : LUT3
|
2279 |
|
|
generic map(
|
2280 |
|
|
INIT => X"E4"
|
2281 |
|
|
)
|
2282 |
|
|
port map (
|
2283 |
|
|
I0 => blk00000003_sig000002b4,
|
2284 |
|
|
I1 => blk00000003_sig000000dd,
|
2285 |
|
|
I2 => blk00000003_sig000000f4,
|
2286 |
|
|
O => blk00000003_sig00000385
|
2287 |
|
|
);
|
2288 |
|
|
blk00000003_blk00000265 : LUT3
|
2289 |
|
|
generic map(
|
2290 |
|
|
INIT => X"E4"
|
2291 |
|
|
)
|
2292 |
|
|
port map (
|
2293 |
|
|
I0 => blk00000003_sig000002b4,
|
2294 |
|
|
I1 => blk00000003_sig000000de,
|
2295 |
|
|
I2 => blk00000003_sig000000f5,
|
2296 |
|
|
O => blk00000003_sig00000384
|
2297 |
|
|
);
|
2298 |
|
|
blk00000003_blk00000264 : LUT3
|
2299 |
|
|
generic map(
|
2300 |
|
|
INIT => X"E4"
|
2301 |
|
|
)
|
2302 |
|
|
port map (
|
2303 |
|
|
I0 => blk00000003_sig000002b4,
|
2304 |
|
|
I1 => blk00000003_sig000000df,
|
2305 |
|
|
I2 => blk00000003_sig000000f6,
|
2306 |
|
|
O => blk00000003_sig00000383
|
2307 |
|
|
);
|
2308 |
|
|
blk00000003_blk00000263 : LUT3
|
2309 |
|
|
generic map(
|
2310 |
|
|
INIT => X"E4"
|
2311 |
|
|
)
|
2312 |
|
|
port map (
|
2313 |
|
|
I0 => blk00000003_sig000002b4,
|
2314 |
|
|
I1 => blk00000003_sig000000e0,
|
2315 |
|
|
I2 => blk00000003_sig000000f7,
|
2316 |
|
|
O => blk00000003_sig00000382
|
2317 |
|
|
);
|
2318 |
|
|
blk00000003_blk00000262 : LUT3
|
2319 |
|
|
generic map(
|
2320 |
|
|
INIT => X"E4"
|
2321 |
|
|
)
|
2322 |
|
|
port map (
|
2323 |
|
|
I0 => blk00000003_sig000002b4,
|
2324 |
|
|
I1 => blk00000003_sig000000e1,
|
2325 |
|
|
I2 => blk00000003_sig000000f8,
|
2326 |
|
|
O => blk00000003_sig00000381
|
2327 |
|
|
);
|
2328 |
|
|
blk00000003_blk00000261 : LUT3
|
2329 |
|
|
generic map(
|
2330 |
|
|
INIT => X"E4"
|
2331 |
|
|
)
|
2332 |
|
|
port map (
|
2333 |
|
|
I0 => blk00000003_sig000002b4,
|
2334 |
|
|
I1 => blk00000003_sig000000e2,
|
2335 |
|
|
I2 => blk00000003_sig000000f9,
|
2336 |
|
|
O => blk00000003_sig00000380
|
2337 |
|
|
);
|
2338 |
|
|
blk00000003_blk00000260 : LUT3
|
2339 |
|
|
generic map(
|
2340 |
|
|
INIT => X"E4"
|
2341 |
|
|
)
|
2342 |
|
|
port map (
|
2343 |
|
|
I0 => blk00000003_sig000002b4,
|
2344 |
|
|
I1 => blk00000003_sig000000e3,
|
2345 |
|
|
I2 => blk00000003_sig000000fa,
|
2346 |
|
|
O => blk00000003_sig0000037f
|
2347 |
|
|
);
|
2348 |
|
|
blk00000003_blk0000025f : LUT3
|
2349 |
|
|
generic map(
|
2350 |
|
|
INIT => X"E4"
|
2351 |
|
|
)
|
2352 |
|
|
port map (
|
2353 |
|
|
I0 => blk00000003_sig000002b4,
|
2354 |
|
|
I1 => blk00000003_sig000000e4,
|
2355 |
|
|
I2 => blk00000003_sig000000fb,
|
2356 |
|
|
O => blk00000003_sig0000037e
|
2357 |
|
|
);
|
2358 |
|
|
blk00000003_blk0000025e : LUT3
|
2359 |
|
|
generic map(
|
2360 |
|
|
INIT => X"E4"
|
2361 |
|
|
)
|
2362 |
|
|
port map (
|
2363 |
|
|
I0 => blk00000003_sig000002b4,
|
2364 |
|
|
I1 => blk00000003_sig000000e5,
|
2365 |
|
|
I2 => blk00000003_sig000000fc,
|
2366 |
|
|
O => blk00000003_sig0000037d
|
2367 |
|
|
);
|
2368 |
|
|
blk00000003_blk0000025d : LUT3
|
2369 |
|
|
generic map(
|
2370 |
|
|
INIT => X"E4"
|
2371 |
|
|
)
|
2372 |
|
|
port map (
|
2373 |
|
|
I0 => blk00000003_sig000002b4,
|
2374 |
|
|
I1 => blk00000003_sig000000e6,
|
2375 |
|
|
I2 => blk00000003_sig000000fd,
|
2376 |
|
|
O => blk00000003_sig0000037c
|
2377 |
|
|
);
|
2378 |
|
|
blk00000003_blk0000025c : LUT3
|
2379 |
|
|
generic map(
|
2380 |
|
|
INIT => X"E4"
|
2381 |
|
|
)
|
2382 |
|
|
port map (
|
2383 |
|
|
I0 => blk00000003_sig000002b4,
|
2384 |
|
|
I1 => blk00000003_sig000000e7,
|
2385 |
|
|
I2 => blk00000003_sig000000fe,
|
2386 |
|
|
O => blk00000003_sig0000037b
|
2387 |
|
|
);
|
2388 |
|
|
blk00000003_blk0000025b : LUT3
|
2389 |
|
|
generic map(
|
2390 |
|
|
INIT => X"E4"
|
2391 |
|
|
)
|
2392 |
|
|
port map (
|
2393 |
|
|
I0 => blk00000003_sig000002b4,
|
2394 |
|
|
I1 => blk00000003_sig000000e8,
|
2395 |
|
|
I2 => blk00000003_sig000000ff,
|
2396 |
|
|
O => blk00000003_sig0000037a
|
2397 |
|
|
);
|
2398 |
|
|
blk00000003_blk0000025a : LUT3
|
2399 |
|
|
generic map(
|
2400 |
|
|
INIT => X"E4"
|
2401 |
|
|
)
|
2402 |
|
|
port map (
|
2403 |
|
|
I0 => blk00000003_sig000002b4,
|
2404 |
|
|
I1 => blk00000003_sig000000e9,
|
2405 |
|
|
I2 => blk00000003_sig00000100,
|
2406 |
|
|
O => blk00000003_sig00000379
|
2407 |
|
|
);
|
2408 |
|
|
blk00000003_blk00000259 : FDR
|
2409 |
|
|
generic map(
|
2410 |
|
|
INIT => '0'
|
2411 |
|
|
)
|
2412 |
|
|
port map (
|
2413 |
|
|
C => sig00000042,
|
2414 |
|
|
D => blk00000003_sig00000259,
|
2415 |
|
|
R => blk00000003_sig0000015f,
|
2416 |
|
|
Q => blk00000003_sig0000019d
|
2417 |
|
|
);
|
2418 |
|
|
blk00000003_blk00000258 : FDR
|
2419 |
|
|
generic map(
|
2420 |
|
|
INIT => '0'
|
2421 |
|
|
)
|
2422 |
|
|
port map (
|
2423 |
|
|
C => sig00000042,
|
2424 |
|
|
D => blk00000003_sig00000258,
|
2425 |
|
|
R => blk00000003_sig0000015f,
|
2426 |
|
|
Q => blk00000003_sig0000019c
|
2427 |
|
|
);
|
2428 |
|
|
blk00000003_blk00000257 : FDR
|
2429 |
|
|
generic map(
|
2430 |
|
|
INIT => '0'
|
2431 |
|
|
)
|
2432 |
|
|
port map (
|
2433 |
|
|
C => sig00000042,
|
2434 |
|
|
D => blk00000003_sig00000257,
|
2435 |
|
|
R => blk00000003_sig0000015f,
|
2436 |
|
|
Q => blk00000003_sig0000019b
|
2437 |
|
|
);
|
2438 |
|
|
blk00000003_blk00000256 : FDR
|
2439 |
|
|
generic map(
|
2440 |
|
|
INIT => '0'
|
2441 |
|
|
)
|
2442 |
|
|
port map (
|
2443 |
|
|
C => sig00000042,
|
2444 |
|
|
D => blk00000003_sig00000256,
|
2445 |
|
|
R => blk00000003_sig0000015f,
|
2446 |
|
|
Q => blk00000003_sig0000019a
|
2447 |
|
|
);
|
2448 |
|
|
blk00000003_blk00000255 : FDR
|
2449 |
|
|
generic map(
|
2450 |
|
|
INIT => '0'
|
2451 |
|
|
)
|
2452 |
|
|
port map (
|
2453 |
|
|
C => sig00000042,
|
2454 |
|
|
D => blk00000003_sig00000255,
|
2455 |
|
|
R => blk00000003_sig0000015f,
|
2456 |
|
|
Q => blk00000003_sig00000199
|
2457 |
|
|
);
|
2458 |
|
|
blk00000003_blk00000254 : FDR
|
2459 |
|
|
generic map(
|
2460 |
|
|
INIT => '0'
|
2461 |
|
|
)
|
2462 |
|
|
port map (
|
2463 |
|
|
C => sig00000042,
|
2464 |
|
|
D => blk00000003_sig00000254,
|
2465 |
|
|
R => blk00000003_sig0000015f,
|
2466 |
|
|
Q => blk00000003_sig00000198
|
2467 |
|
|
);
|
2468 |
|
|
blk00000003_blk00000253 : FDR
|
2469 |
|
|
generic map(
|
2470 |
|
|
INIT => '0'
|
2471 |
|
|
)
|
2472 |
|
|
port map (
|
2473 |
|
|
C => sig00000042,
|
2474 |
|
|
D => blk00000003_sig00000253,
|
2475 |
|
|
R => blk00000003_sig0000015f,
|
2476 |
|
|
Q => blk00000003_sig00000197
|
2477 |
|
|
);
|
2478 |
|
|
blk00000003_blk00000252 : FDR
|
2479 |
|
|
generic map(
|
2480 |
|
|
INIT => '0'
|
2481 |
|
|
)
|
2482 |
|
|
port map (
|
2483 |
|
|
C => sig00000042,
|
2484 |
|
|
D => blk00000003_sig00000252,
|
2485 |
|
|
R => blk00000003_sig0000015f,
|
2486 |
|
|
Q => blk00000003_sig00000196
|
2487 |
|
|
);
|
2488 |
|
|
blk00000003_blk00000251 : FDR
|
2489 |
|
|
generic map(
|
2490 |
|
|
INIT => '0'
|
2491 |
|
|
)
|
2492 |
|
|
port map (
|
2493 |
|
|
C => sig00000042,
|
2494 |
|
|
D => blk00000003_sig00000251,
|
2495 |
|
|
R => blk00000003_sig0000015f,
|
2496 |
|
|
Q => blk00000003_sig00000195
|
2497 |
|
|
);
|
2498 |
|
|
blk00000003_blk00000250 : FDR
|
2499 |
|
|
generic map(
|
2500 |
|
|
INIT => '0'
|
2501 |
|
|
)
|
2502 |
|
|
port map (
|
2503 |
|
|
C => sig00000042,
|
2504 |
|
|
D => blk00000003_sig00000250,
|
2505 |
|
|
R => blk00000003_sig0000015f,
|
2506 |
|
|
Q => blk00000003_sig00000194
|
2507 |
|
|
);
|
2508 |
|
|
blk00000003_blk0000024f : FDR
|
2509 |
|
|
generic map(
|
2510 |
|
|
INIT => '0'
|
2511 |
|
|
)
|
2512 |
|
|
port map (
|
2513 |
|
|
C => sig00000042,
|
2514 |
|
|
D => blk00000003_sig0000024f,
|
2515 |
|
|
R => blk00000003_sig0000015f,
|
2516 |
|
|
Q => blk00000003_sig00000183
|
2517 |
|
|
);
|
2518 |
|
|
blk00000003_blk0000024e : FDR
|
2519 |
|
|
generic map(
|
2520 |
|
|
INIT => '0'
|
2521 |
|
|
)
|
2522 |
|
|
port map (
|
2523 |
|
|
C => sig00000042,
|
2524 |
|
|
D => blk00000003_sig0000024e,
|
2525 |
|
|
R => blk00000003_sig0000015f,
|
2526 |
|
|
Q => blk00000003_sig00000184
|
2527 |
|
|
);
|
2528 |
|
|
blk00000003_blk0000024d : FDR
|
2529 |
|
|
generic map(
|
2530 |
|
|
INIT => '0'
|
2531 |
|
|
)
|
2532 |
|
|
port map (
|
2533 |
|
|
C => sig00000042,
|
2534 |
|
|
D => blk00000003_sig0000024d,
|
2535 |
|
|
R => blk00000003_sig0000015f,
|
2536 |
|
|
Q => blk00000003_sig00000185
|
2537 |
|
|
);
|
2538 |
|
|
blk00000003_blk0000024c : FDR
|
2539 |
|
|
generic map(
|
2540 |
|
|
INIT => '0'
|
2541 |
|
|
)
|
2542 |
|
|
port map (
|
2543 |
|
|
C => sig00000042,
|
2544 |
|
|
D => blk00000003_sig0000024c,
|
2545 |
|
|
R => blk00000003_sig0000015f,
|
2546 |
|
|
Q => blk00000003_sig00000186
|
2547 |
|
|
);
|
2548 |
|
|
blk00000003_blk0000024b : FDR
|
2549 |
|
|
generic map(
|
2550 |
|
|
INIT => '0'
|
2551 |
|
|
)
|
2552 |
|
|
port map (
|
2553 |
|
|
C => sig00000042,
|
2554 |
|
|
D => blk00000003_sig0000024b,
|
2555 |
|
|
R => blk00000003_sig0000015f,
|
2556 |
|
|
Q => blk00000003_sig0000017d
|
2557 |
|
|
);
|
2558 |
|
|
blk00000003_blk0000024a : LUT6
|
2559 |
|
|
generic map(
|
2560 |
|
|
INIT => X"0000000000000001"
|
2561 |
|
|
)
|
2562 |
|
|
port map (
|
2563 |
|
|
I0 => blk00000003_sig00000266,
|
2564 |
|
|
I1 => blk00000003_sig00000265,
|
2565 |
|
|
I2 => blk00000003_sig00000267,
|
2566 |
|
|
I3 => blk00000003_sig0000025d,
|
2567 |
|
|
I4 => blk00000003_sig0000025e,
|
2568 |
|
|
I5 => blk00000003_sig0000025f,
|
2569 |
|
|
O => blk00000003_sig00000378
|
2570 |
|
|
);
|
2571 |
|
|
blk00000003_blk00000249 : LUT6
|
2572 |
|
|
generic map(
|
2573 |
|
|
INIT => X"0000000000000001"
|
2574 |
|
|
)
|
2575 |
|
|
port map (
|
2576 |
|
|
I0 => blk00000003_sig000001a2,
|
2577 |
|
|
I1 => blk00000003_sig000001a3,
|
2578 |
|
|
I2 => blk00000003_sig000001a4,
|
2579 |
|
|
I3 => blk00000003_sig0000019e,
|
2580 |
|
|
I4 => blk00000003_sig0000019f,
|
2581 |
|
|
I5 => blk00000003_sig00000377,
|
2582 |
|
|
O => blk00000003_sig0000032e
|
2583 |
|
|
);
|
2584 |
|
|
blk00000003_blk00000248 : LUT5
|
2585 |
|
|
generic map(
|
2586 |
|
|
INIT => X"FFFFFFFE"
|
2587 |
|
|
)
|
2588 |
|
|
port map (
|
2589 |
|
|
I0 => blk00000003_sig000001a0,
|
2590 |
|
|
I1 => blk00000003_sig000001a1,
|
2591 |
|
|
I2 => blk00000003_sig000001a5,
|
2592 |
|
|
I3 => blk00000003_sig0000032c,
|
2593 |
|
|
I4 => blk00000003_sig00000330,
|
2594 |
|
|
O => blk00000003_sig00000377
|
2595 |
|
|
);
|
2596 |
|
|
blk00000003_blk00000247 : LUT5
|
2597 |
|
|
generic map(
|
2598 |
|
|
INIT => X"1111000F"
|
2599 |
|
|
)
|
2600 |
|
|
port map (
|
2601 |
|
|
I0 => blk00000003_sig00000250,
|
2602 |
|
|
I1 => blk00000003_sig00000251,
|
2603 |
|
|
I2 => blk00000003_sig00000240,
|
2604 |
|
|
I3 => blk00000003_sig00000241,
|
2605 |
|
|
I4 => blk00000003_sig0000015f,
|
2606 |
|
|
O => blk00000003_sig00000169
|
2607 |
|
|
);
|
2608 |
|
|
blk00000003_blk00000246 : LUT5
|
2609 |
|
|
generic map(
|
2610 |
|
|
INIT => X"03030055"
|
2611 |
|
|
)
|
2612 |
|
|
port map (
|
2613 |
|
|
I0 => blk00000003_sig00000243,
|
2614 |
|
|
I1 => blk00000003_sig00000252,
|
2615 |
|
|
I2 => blk00000003_sig00000253,
|
2616 |
|
|
I3 => blk00000003_sig00000242,
|
2617 |
|
|
I4 => blk00000003_sig0000015f,
|
2618 |
|
|
O => blk00000003_sig0000016a
|
2619 |
|
|
);
|
2620 |
|
|
blk00000003_blk00000245 : LUT3
|
2621 |
|
|
generic map(
|
2622 |
|
|
INIT => X"47"
|
2623 |
|
|
)
|
2624 |
|
|
port map (
|
2625 |
|
|
I0 => blk00000003_sig00000355,
|
2626 |
|
|
I1 => blk00000003_sig00000354,
|
2627 |
|
|
I2 => blk00000003_sig0000035d,
|
2628 |
|
|
O => blk00000003_sig000002b5
|
2629 |
|
|
);
|
2630 |
|
|
blk00000003_blk00000244 : LUT5
|
2631 |
|
|
generic map(
|
2632 |
|
|
INIT => X"000F1111"
|
2633 |
|
|
)
|
2634 |
|
|
port map (
|
2635 |
|
|
I0 => blk00000003_sig00000244,
|
2636 |
|
|
I1 => blk00000003_sig00000245,
|
2637 |
|
|
I2 => blk00000003_sig00000254,
|
2638 |
|
|
I3 => blk00000003_sig00000255,
|
2639 |
|
|
I4 => blk00000003_sig0000015f,
|
2640 |
|
|
O => blk00000003_sig0000016b
|
2641 |
|
|
);
|
2642 |
|
|
blk00000003_blk00000243 : LUT3
|
2643 |
|
|
generic map(
|
2644 |
|
|
INIT => X"E4"
|
2645 |
|
|
)
|
2646 |
|
|
port map (
|
2647 |
|
|
I0 => blk00000003_sig00000354,
|
2648 |
|
|
I1 => blk00000003_sig0000035e,
|
2649 |
|
|
I2 => blk00000003_sig00000356,
|
2650 |
|
|
O => blk00000003_sig000002b8
|
2651 |
|
|
);
|
2652 |
|
|
blk00000003_blk00000242 : LUT5
|
2653 |
|
|
generic map(
|
2654 |
|
|
INIT => X"000F1111"
|
2655 |
|
|
)
|
2656 |
|
|
port map (
|
2657 |
|
|
I0 => blk00000003_sig00000246,
|
2658 |
|
|
I1 => blk00000003_sig00000247,
|
2659 |
|
|
I2 => blk00000003_sig00000256,
|
2660 |
|
|
I3 => blk00000003_sig00000257,
|
2661 |
|
|
I4 => blk00000003_sig0000015f,
|
2662 |
|
|
O => blk00000003_sig0000016c
|
2663 |
|
|
);
|
2664 |
|
|
blk00000003_blk00000241 : LUT3
|
2665 |
|
|
generic map(
|
2666 |
|
|
INIT => X"E4"
|
2667 |
|
|
)
|
2668 |
|
|
port map (
|
2669 |
|
|
I0 => blk00000003_sig00000354,
|
2670 |
|
|
I1 => blk00000003_sig0000035f,
|
2671 |
|
|
I2 => blk00000003_sig00000357,
|
2672 |
|
|
O => blk00000003_sig000002bb
|
2673 |
|
|
);
|
2674 |
|
|
blk00000003_blk00000240 : LUT6
|
2675 |
|
|
generic map(
|
2676 |
|
|
INIT => X"0000000000008001"
|
2677 |
|
|
)
|
2678 |
|
|
port map (
|
2679 |
|
|
I0 => blk00000003_sig00000352,
|
2680 |
|
|
I1 => blk00000003_sig00000353,
|
2681 |
|
|
I2 => blk00000003_sig00000354,
|
2682 |
|
|
I3 => blk00000003_sig00000351,
|
2683 |
|
|
I4 => blk00000003_sig00000375,
|
2684 |
|
|
I5 => blk00000003_sig00000376,
|
2685 |
|
|
O => blk00000003_sig0000026c
|
2686 |
|
|
);
|
2687 |
|
|
blk00000003_blk0000023f : LUT2
|
2688 |
|
|
generic map(
|
2689 |
|
|
INIT => X"E"
|
2690 |
|
|
)
|
2691 |
|
|
port map (
|
2692 |
|
|
I0 => blk00000003_sig00000321,
|
2693 |
|
|
I1 => blk00000003_sig0000031c,
|
2694 |
|
|
O => blk00000003_sig00000375
|
2695 |
|
|
);
|
2696 |
|
|
blk00000003_blk0000023e : LUT5
|
2697 |
|
|
generic map(
|
2698 |
|
|
INIT => X"C840FB73"
|
2699 |
|
|
)
|
2700 |
|
|
port map (
|
2701 |
|
|
I0 => blk00000003_sig0000013a,
|
2702 |
|
|
I1 => blk00000003_sig00000136,
|
2703 |
|
|
I2 => blk00000003_sig00000181,
|
2704 |
|
|
I3 => blk00000003_sig00000187,
|
2705 |
|
|
I4 => blk00000003_sig00000374,
|
2706 |
|
|
O => blk00000003_sig00000167
|
2707 |
|
|
);
|
2708 |
|
|
blk00000003_blk0000023d : LUT3
|
2709 |
|
|
generic map(
|
2710 |
|
|
INIT => X"1B"
|
2711 |
|
|
)
|
2712 |
|
|
port map (
|
2713 |
|
|
I0 => blk00000003_sig00000132,
|
2714 |
|
|
I1 => blk00000003_sig00000175,
|
2715 |
|
|
I2 => blk00000003_sig0000017b,
|
2716 |
|
|
O => blk00000003_sig00000374
|
2717 |
|
|
);
|
2718 |
|
|
blk00000003_blk0000023c : LUT5
|
2719 |
|
|
generic map(
|
2720 |
|
|
INIT => X"C840FB73"
|
2721 |
|
|
)
|
2722 |
|
|
port map (
|
2723 |
|
|
I0 => blk00000003_sig0000013a,
|
2724 |
|
|
I1 => blk00000003_sig00000136,
|
2725 |
|
|
I2 => blk00000003_sig00000182,
|
2726 |
|
|
I3 => blk00000003_sig00000188,
|
2727 |
|
|
I4 => blk00000003_sig00000373,
|
2728 |
|
|
O => blk00000003_sig00000165
|
2729 |
|
|
);
|
2730 |
|
|
blk00000003_blk0000023b : LUT3
|
2731 |
|
|
generic map(
|
2732 |
|
|
INIT => X"1B"
|
2733 |
|
|
)
|
2734 |
|
|
port map (
|
2735 |
|
|
I0 => blk00000003_sig00000132,
|
2736 |
|
|
I1 => blk00000003_sig00000176,
|
2737 |
|
|
I2 => blk00000003_sig0000017c,
|
2738 |
|
|
O => blk00000003_sig00000373
|
2739 |
|
|
);
|
2740 |
|
|
blk00000003_blk0000023a : LUT5
|
2741 |
|
|
generic map(
|
2742 |
|
|
INIT => X"000F1111"
|
2743 |
|
|
)
|
2744 |
|
|
port map (
|
2745 |
|
|
I0 => blk00000003_sig00000248,
|
2746 |
|
|
I1 => blk00000003_sig00000249,
|
2747 |
|
|
I2 => blk00000003_sig00000258,
|
2748 |
|
|
I3 => blk00000003_sig00000259,
|
2749 |
|
|
I4 => blk00000003_sig0000015f,
|
2750 |
|
|
O => blk00000003_sig0000016d
|
2751 |
|
|
);
|
2752 |
|
|
blk00000003_blk00000239 : LUT3
|
2753 |
|
|
generic map(
|
2754 |
|
|
INIT => X"E4"
|
2755 |
|
|
)
|
2756 |
|
|
port map (
|
2757 |
|
|
I0 => blk00000003_sig00000354,
|
2758 |
|
|
I1 => blk00000003_sig00000360,
|
2759 |
|
|
I2 => blk00000003_sig00000358,
|
2760 |
|
|
O => blk00000003_sig000002be
|
2761 |
|
|
);
|
2762 |
|
|
blk00000003_blk00000238 : LUT4
|
2763 |
|
|
generic map(
|
2764 |
|
|
INIT => X"2227"
|
2765 |
|
|
)
|
2766 |
|
|
port map (
|
2767 |
|
|
I0 => blk00000003_sig0000015f,
|
2768 |
|
|
I1 => blk00000003_sig0000025a,
|
2769 |
|
|
I2 => blk00000003_sig0000024a,
|
2770 |
|
|
I3 => blk00000003_sig0000024b,
|
2771 |
|
|
O => blk00000003_sig0000016e
|
2772 |
|
|
);
|
2773 |
|
|
blk00000003_blk00000237 : LUT3
|
2774 |
|
|
generic map(
|
2775 |
|
|
INIT => X"E4"
|
2776 |
|
|
)
|
2777 |
|
|
port map (
|
2778 |
|
|
I0 => blk00000003_sig00000354,
|
2779 |
|
|
I1 => blk00000003_sig00000361,
|
2780 |
|
|
I2 => blk00000003_sig00000359,
|
2781 |
|
|
O => blk00000003_sig000002c1
|
2782 |
|
|
);
|
2783 |
|
|
blk00000003_blk00000236 : LUT3
|
2784 |
|
|
generic map(
|
2785 |
|
|
INIT => X"AB"
|
2786 |
|
|
)
|
2787 |
|
|
port map (
|
2788 |
|
|
I0 => blk00000003_sig0000015f,
|
2789 |
|
|
I1 => blk00000003_sig0000024c,
|
2790 |
|
|
I2 => blk00000003_sig0000024d,
|
2791 |
|
|
O => blk00000003_sig0000016f
|
2792 |
|
|
);
|
2793 |
|
|
blk00000003_blk00000235 : LUT3
|
2794 |
|
|
generic map(
|
2795 |
|
|
INIT => X"E4"
|
2796 |
|
|
)
|
2797 |
|
|
port map (
|
2798 |
|
|
I0 => blk00000003_sig00000354,
|
2799 |
|
|
I1 => blk00000003_sig00000362,
|
2800 |
|
|
I2 => blk00000003_sig0000035a,
|
2801 |
|
|
O => blk00000003_sig000002c4
|
2802 |
|
|
);
|
2803 |
|
|
blk00000003_blk00000234 : LUT3
|
2804 |
|
|
generic map(
|
2805 |
|
|
INIT => X"AB"
|
2806 |
|
|
)
|
2807 |
|
|
port map (
|
2808 |
|
|
I0 => blk00000003_sig0000015f,
|
2809 |
|
|
I1 => blk00000003_sig0000024e,
|
2810 |
|
|
I2 => blk00000003_sig0000024f,
|
2811 |
|
|
O => blk00000003_sig00000170
|
2812 |
|
|
);
|
2813 |
|
|
blk00000003_blk00000233 : LUT3
|
2814 |
|
|
generic map(
|
2815 |
|
|
INIT => X"E4"
|
2816 |
|
|
)
|
2817 |
|
|
port map (
|
2818 |
|
|
I0 => blk00000003_sig00000354,
|
2819 |
|
|
I1 => blk00000003_sig00000363,
|
2820 |
|
|
I2 => blk00000003_sig0000035b,
|
2821 |
|
|
O => blk00000003_sig000002c7
|
2822 |
|
|
);
|
2823 |
|
|
blk00000003_blk00000232 : LUT5
|
2824 |
|
|
generic map(
|
2825 |
|
|
INIT => X"02020257"
|
2826 |
|
|
)
|
2827 |
|
|
port map (
|
2828 |
|
|
I0 => blk00000003_sig000002b4,
|
2829 |
|
|
I1 => blk00000003_sig00000108,
|
2830 |
|
|
I2 => blk00000003_sig00000109,
|
2831 |
|
|
I3 => blk00000003_sig000000f1,
|
2832 |
|
|
I4 => blk00000003_sig000000f2,
|
2833 |
|
|
O => blk00000003_sig0000021c
|
2834 |
|
|
);
|
2835 |
|
|
blk00000003_blk00000231 : LUT6
|
2836 |
|
|
generic map(
|
2837 |
|
|
INIT => X"AAAAF0F0FF00CCCC"
|
2838 |
|
|
)
|
2839 |
|
|
port map (
|
2840 |
|
|
I0 => blk00000003_sig000000fb,
|
2841 |
|
|
I1 => blk00000003_sig000000f2,
|
2842 |
|
|
I2 => blk00000003_sig000000e4,
|
2843 |
|
|
I3 => blk00000003_sig00000109,
|
2844 |
|
|
I4 => blk00000003_sig000002b4,
|
2845 |
|
|
I5 => blk00000003_sig00000372,
|
2846 |
|
|
O => blk00000003_sig000001b6
|
2847 |
|
|
);
|
2848 |
|
|
blk00000003_blk00000230 : LUT6
|
2849 |
|
|
generic map(
|
2850 |
|
|
INIT => X"AAAAF0F0FF00CCCC"
|
2851 |
|
|
)
|
2852 |
|
|
port map (
|
2853 |
|
|
I0 => blk00000003_sig000000fa,
|
2854 |
|
|
I1 => blk00000003_sig000000f1,
|
2855 |
|
|
I2 => blk00000003_sig000000e3,
|
2856 |
|
|
I3 => blk00000003_sig00000108,
|
2857 |
|
|
I4 => blk00000003_sig000002b4,
|
2858 |
|
|
I5 => blk00000003_sig00000372,
|
2859 |
|
|
O => blk00000003_sig000001b8
|
2860 |
|
|
);
|
2861 |
|
|
blk00000003_blk0000022f : LUT6
|
2862 |
|
|
generic map(
|
2863 |
|
|
INIT => X"AAAAF0F0FF00CCCC"
|
2864 |
|
|
)
|
2865 |
|
|
port map (
|
2866 |
|
|
I0 => blk00000003_sig000000f9,
|
2867 |
|
|
I1 => blk00000003_sig000000f0,
|
2868 |
|
|
I2 => blk00000003_sig000000e2,
|
2869 |
|
|
I3 => blk00000003_sig00000107,
|
2870 |
|
|
I4 => blk00000003_sig000002b4,
|
2871 |
|
|
I5 => blk00000003_sig00000372,
|
2872 |
|
|
O => blk00000003_sig000001ba
|
2873 |
|
|
);
|
2874 |
|
|
blk00000003_blk0000022e : LUT6
|
2875 |
|
|
generic map(
|
2876 |
|
|
INIT => X"AAAAF0F0FF00CCCC"
|
2877 |
|
|
)
|
2878 |
|
|
port map (
|
2879 |
|
|
I0 => blk00000003_sig000000f8,
|
2880 |
|
|
I1 => blk00000003_sig000000ef,
|
2881 |
|
|
I2 => blk00000003_sig000000e1,
|
2882 |
|
|
I3 => blk00000003_sig00000106,
|
2883 |
|
|
I4 => blk00000003_sig000002b4,
|
2884 |
|
|
I5 => blk00000003_sig00000372,
|
2885 |
|
|
O => blk00000003_sig000001bc
|
2886 |
|
|
);
|
2887 |
|
|
blk00000003_blk0000022d : LUT6
|
2888 |
|
|
generic map(
|
2889 |
|
|
INIT => X"AAAAF0F0FF00CCCC"
|
2890 |
|
|
)
|
2891 |
|
|
port map (
|
2892 |
|
|
I0 => blk00000003_sig000000f7,
|
2893 |
|
|
I1 => blk00000003_sig000000ee,
|
2894 |
|
|
I2 => blk00000003_sig000000e0,
|
2895 |
|
|
I3 => blk00000003_sig00000105,
|
2896 |
|
|
I4 => blk00000003_sig000002b4,
|
2897 |
|
|
I5 => blk00000003_sig00000372,
|
2898 |
|
|
O => blk00000003_sig000001be
|
2899 |
|
|
);
|
2900 |
|
|
blk00000003_blk0000022c : LUT6
|
2901 |
|
|
generic map(
|
2902 |
|
|
INIT => X"AAAAF0F0FF00CCCC"
|
2903 |
|
|
)
|
2904 |
|
|
port map (
|
2905 |
|
|
I0 => blk00000003_sig000000f6,
|
2906 |
|
|
I1 => blk00000003_sig000000ed,
|
2907 |
|
|
I2 => blk00000003_sig000000df,
|
2908 |
|
|
I3 => blk00000003_sig00000104,
|
2909 |
|
|
I4 => blk00000003_sig000002b4,
|
2910 |
|
|
I5 => blk00000003_sig00000372,
|
2911 |
|
|
O => blk00000003_sig000001c0
|
2912 |
|
|
);
|
2913 |
|
|
blk00000003_blk0000022b : LUT6
|
2914 |
|
|
generic map(
|
2915 |
|
|
INIT => X"AAAAF0F0FF00CCCC"
|
2916 |
|
|
)
|
2917 |
|
|
port map (
|
2918 |
|
|
I0 => blk00000003_sig000000f5,
|
2919 |
|
|
I1 => blk00000003_sig000000ec,
|
2920 |
|
|
I2 => blk00000003_sig000000de,
|
2921 |
|
|
I3 => blk00000003_sig00000103,
|
2922 |
|
|
I4 => blk00000003_sig000002b4,
|
2923 |
|
|
I5 => blk00000003_sig00000372,
|
2924 |
|
|
O => blk00000003_sig000001c2
|
2925 |
|
|
);
|
2926 |
|
|
blk00000003_blk0000022a : LUT6
|
2927 |
|
|
generic map(
|
2928 |
|
|
INIT => X"AAAAF0F0FF00CCCC"
|
2929 |
|
|
)
|
2930 |
|
|
port map (
|
2931 |
|
|
I0 => blk00000003_sig000000f4,
|
2932 |
|
|
I1 => blk00000003_sig000000eb,
|
2933 |
|
|
I2 => blk00000003_sig000000dd,
|
2934 |
|
|
I3 => blk00000003_sig00000102,
|
2935 |
|
|
I4 => blk00000003_sig000002b4,
|
2936 |
|
|
I5 => blk00000003_sig00000372,
|
2937 |
|
|
O => blk00000003_sig000001c4
|
2938 |
|
|
);
|
2939 |
|
|
blk00000003_blk00000229 : LUT6
|
2940 |
|
|
generic map(
|
2941 |
|
|
INIT => X"AAAAF0F0FF00CCCC"
|
2942 |
|
|
)
|
2943 |
|
|
port map (
|
2944 |
|
|
I0 => blk00000003_sig000000f3,
|
2945 |
|
|
I1 => blk00000003_sig000000ea,
|
2946 |
|
|
I2 => blk00000003_sig000000dc,
|
2947 |
|
|
I3 => blk00000003_sig00000101,
|
2948 |
|
|
I4 => blk00000003_sig000002b4,
|
2949 |
|
|
I5 => blk00000003_sig00000372,
|
2950 |
|
|
O => blk00000003_sig000001c6
|
2951 |
|
|
);
|
2952 |
|
|
blk00000003_blk00000228 : LUT2
|
2953 |
|
|
generic map(
|
2954 |
|
|
INIT => X"8"
|
2955 |
|
|
)
|
2956 |
|
|
port map (
|
2957 |
|
|
I0 => blk00000003_sig00000321,
|
2958 |
|
|
I1 => blk00000003_sig0000031c,
|
2959 |
|
|
O => blk00000003_sig0000033b
|
2960 |
|
|
);
|
2961 |
|
|
blk00000003_blk00000227 : LUT6
|
2962 |
|
|
generic map(
|
2963 |
|
|
INIT => X"0000000080000000"
|
2964 |
|
|
)
|
2965 |
|
|
port map (
|
2966 |
|
|
I0 => blk00000003_sig000001a2,
|
2967 |
|
|
I1 => blk00000003_sig000001a3,
|
2968 |
|
|
I2 => blk00000003_sig000001a4,
|
2969 |
|
|
I3 => blk00000003_sig0000019e,
|
2970 |
|
|
I4 => blk00000003_sig0000019f,
|
2971 |
|
|
I5 => blk00000003_sig00000371,
|
2972 |
|
|
O => blk00000003_sig0000032a
|
2973 |
|
|
);
|
2974 |
|
|
blk00000003_blk00000226 : LUT5
|
2975 |
|
|
generic map(
|
2976 |
|
|
INIT => X"FFFFBFFF"
|
2977 |
|
|
)
|
2978 |
|
|
port map (
|
2979 |
|
|
I0 => blk00000003_sig0000032c,
|
2980 |
|
|
I1 => blk00000003_sig000001a0,
|
2981 |
|
|
I2 => blk00000003_sig000001a1,
|
2982 |
|
|
I3 => blk00000003_sig000001a5,
|
2983 |
|
|
I4 => blk00000003_sig00000330,
|
2984 |
|
|
O => blk00000003_sig00000371
|
2985 |
|
|
);
|
2986 |
|
|
blk00000003_blk00000225 : LUT5
|
2987 |
|
|
generic map(
|
2988 |
|
|
INIT => X"02020257"
|
2989 |
|
|
)
|
2990 |
|
|
port map (
|
2991 |
|
|
I0 => blk00000003_sig000002b4,
|
2992 |
|
|
I1 => blk00000003_sig00000106,
|
2993 |
|
|
I2 => blk00000003_sig00000107,
|
2994 |
|
|
I3 => blk00000003_sig000000ef,
|
2995 |
|
|
I4 => blk00000003_sig000000f0,
|
2996 |
|
|
O => blk00000003_sig0000021b
|
2997 |
|
|
);
|
2998 |
|
|
blk00000003_blk00000224 : LUT5
|
2999 |
|
|
generic map(
|
3000 |
|
|
INIT => X"02020257"
|
3001 |
|
|
)
|
3002 |
|
|
port map (
|
3003 |
|
|
I0 => blk00000003_sig000002b4,
|
3004 |
|
|
I1 => blk00000003_sig00000104,
|
3005 |
|
|
I2 => blk00000003_sig00000105,
|
3006 |
|
|
I3 => blk00000003_sig000000ed,
|
3007 |
|
|
I4 => blk00000003_sig000000ee,
|
3008 |
|
|
O => blk00000003_sig00000219
|
3009 |
|
|
);
|
3010 |
|
|
blk00000003_blk00000223 : LUT5
|
3011 |
|
|
generic map(
|
3012 |
|
|
INIT => X"02020257"
|
3013 |
|
|
)
|
3014 |
|
|
port map (
|
3015 |
|
|
I0 => blk00000003_sig000002b4,
|
3016 |
|
|
I1 => blk00000003_sig00000102,
|
3017 |
|
|
I2 => blk00000003_sig00000103,
|
3018 |
|
|
I3 => blk00000003_sig000000eb,
|
3019 |
|
|
I4 => blk00000003_sig000000ec,
|
3020 |
|
|
O => blk00000003_sig00000217
|
3021 |
|
|
);
|
3022 |
|
|
blk00000003_blk00000222 : LUT5
|
3023 |
|
|
generic map(
|
3024 |
|
|
INIT => X"02020257"
|
3025 |
|
|
)
|
3026 |
|
|
port map (
|
3027 |
|
|
I0 => blk00000003_sig000002b4,
|
3028 |
|
|
I1 => blk00000003_sig00000100,
|
3029 |
|
|
I2 => blk00000003_sig00000101,
|
3030 |
|
|
I3 => blk00000003_sig000000e9,
|
3031 |
|
|
I4 => blk00000003_sig000000ea,
|
3032 |
|
|
O => blk00000003_sig00000215
|
3033 |
|
|
);
|
3034 |
|
|
blk00000003_blk00000221 : LUT5
|
3035 |
|
|
generic map(
|
3036 |
|
|
INIT => X"02020257"
|
3037 |
|
|
)
|
3038 |
|
|
port map (
|
3039 |
|
|
I0 => blk00000003_sig000002b4,
|
3040 |
|
|
I1 => blk00000003_sig000000fe,
|
3041 |
|
|
I2 => blk00000003_sig000000ff,
|
3042 |
|
|
I3 => blk00000003_sig000000e7,
|
3043 |
|
|
I4 => blk00000003_sig000000e8,
|
3044 |
|
|
O => blk00000003_sig00000213
|
3045 |
|
|
);
|
3046 |
|
|
blk00000003_blk00000220 : LUT5
|
3047 |
|
|
generic map(
|
3048 |
|
|
INIT => X"02020257"
|
3049 |
|
|
)
|
3050 |
|
|
port map (
|
3051 |
|
|
I0 => blk00000003_sig000002b4,
|
3052 |
|
|
I1 => blk00000003_sig000000fc,
|
3053 |
|
|
I2 => blk00000003_sig000000fd,
|
3054 |
|
|
I3 => blk00000003_sig000000e5,
|
3055 |
|
|
I4 => blk00000003_sig000000e6,
|
3056 |
|
|
O => blk00000003_sig00000210
|
3057 |
|
|
);
|
3058 |
|
|
blk00000003_blk0000021f : LUT3
|
3059 |
|
|
generic map(
|
3060 |
|
|
INIT => X"E4"
|
3061 |
|
|
)
|
3062 |
|
|
port map (
|
3063 |
|
|
I0 => blk00000003_sig0000015f,
|
3064 |
|
|
I1 => blk00000003_sig0000024a,
|
3065 |
|
|
I2 => blk00000003_sig0000025a,
|
3066 |
|
|
O => blk00000003_sig00000193
|
3067 |
|
|
);
|
3068 |
|
|
blk00000003_blk0000021e : LUT3
|
3069 |
|
|
generic map(
|
3070 |
|
|
INIT => X"E4"
|
3071 |
|
|
)
|
3072 |
|
|
port map (
|
3073 |
|
|
I0 => blk00000003_sig0000015f,
|
3074 |
|
|
I1 => blk00000003_sig00000249,
|
3075 |
|
|
I2 => blk00000003_sig00000259,
|
3076 |
|
|
O => blk00000003_sig00000192
|
3077 |
|
|
);
|
3078 |
|
|
blk00000003_blk0000021d : LUT3
|
3079 |
|
|
generic map(
|
3080 |
|
|
INIT => X"E4"
|
3081 |
|
|
)
|
3082 |
|
|
port map (
|
3083 |
|
|
I0 => blk00000003_sig0000015f,
|
3084 |
|
|
I1 => blk00000003_sig00000248,
|
3085 |
|
|
I2 => blk00000003_sig00000258,
|
3086 |
|
|
O => blk00000003_sig00000191
|
3087 |
|
|
);
|
3088 |
|
|
blk00000003_blk0000021c : LUT3
|
3089 |
|
|
generic map(
|
3090 |
|
|
INIT => X"E4"
|
3091 |
|
|
)
|
3092 |
|
|
port map (
|
3093 |
|
|
I0 => blk00000003_sig0000015f,
|
3094 |
|
|
I1 => blk00000003_sig00000247,
|
3095 |
|
|
I2 => blk00000003_sig00000257,
|
3096 |
|
|
O => blk00000003_sig00000190
|
3097 |
|
|
);
|
3098 |
|
|
blk00000003_blk0000021b : LUT3
|
3099 |
|
|
generic map(
|
3100 |
|
|
INIT => X"E4"
|
3101 |
|
|
)
|
3102 |
|
|
port map (
|
3103 |
|
|
I0 => blk00000003_sig0000015f,
|
3104 |
|
|
I1 => blk00000003_sig00000246,
|
3105 |
|
|
I2 => blk00000003_sig00000256,
|
3106 |
|
|
O => blk00000003_sig0000018f
|
3107 |
|
|
);
|
3108 |
|
|
blk00000003_blk0000021a : LUT3
|
3109 |
|
|
generic map(
|
3110 |
|
|
INIT => X"E4"
|
3111 |
|
|
)
|
3112 |
|
|
port map (
|
3113 |
|
|
I0 => blk00000003_sig0000015f,
|
3114 |
|
|
I1 => blk00000003_sig00000245,
|
3115 |
|
|
I2 => blk00000003_sig00000255,
|
3116 |
|
|
O => blk00000003_sig0000018e
|
3117 |
|
|
);
|
3118 |
|
|
blk00000003_blk00000219 : LUT3
|
3119 |
|
|
generic map(
|
3120 |
|
|
INIT => X"E4"
|
3121 |
|
|
)
|
3122 |
|
|
port map (
|
3123 |
|
|
I0 => blk00000003_sig0000015f,
|
3124 |
|
|
I1 => blk00000003_sig00000244,
|
3125 |
|
|
I2 => blk00000003_sig00000254,
|
3126 |
|
|
O => blk00000003_sig0000018d
|
3127 |
|
|
);
|
3128 |
|
|
blk00000003_blk00000218 : LUT3
|
3129 |
|
|
generic map(
|
3130 |
|
|
INIT => X"E4"
|
3131 |
|
|
)
|
3132 |
|
|
port map (
|
3133 |
|
|
I0 => blk00000003_sig0000015f,
|
3134 |
|
|
I1 => blk00000003_sig00000243,
|
3135 |
|
|
I2 => blk00000003_sig00000253,
|
3136 |
|
|
O => blk00000003_sig0000018c
|
3137 |
|
|
);
|
3138 |
|
|
blk00000003_blk00000217 : LUT3
|
3139 |
|
|
generic map(
|
3140 |
|
|
INIT => X"E4"
|
3141 |
|
|
)
|
3142 |
|
|
port map (
|
3143 |
|
|
I0 => blk00000003_sig0000015f,
|
3144 |
|
|
I1 => blk00000003_sig00000242,
|
3145 |
|
|
I2 => blk00000003_sig00000252,
|
3146 |
|
|
O => blk00000003_sig0000018b
|
3147 |
|
|
);
|
3148 |
|
|
blk00000003_blk00000216 : LUT3
|
3149 |
|
|
generic map(
|
3150 |
|
|
INIT => X"E4"
|
3151 |
|
|
)
|
3152 |
|
|
port map (
|
3153 |
|
|
I0 => blk00000003_sig0000015f,
|
3154 |
|
|
I1 => blk00000003_sig00000241,
|
3155 |
|
|
I2 => blk00000003_sig00000251,
|
3156 |
|
|
O => blk00000003_sig0000018a
|
3157 |
|
|
);
|
3158 |
|
|
blk00000003_blk00000215 : LUT3
|
3159 |
|
|
generic map(
|
3160 |
|
|
INIT => X"E4"
|
3161 |
|
|
)
|
3162 |
|
|
port map (
|
3163 |
|
|
I0 => blk00000003_sig0000015f,
|
3164 |
|
|
I1 => blk00000003_sig00000240,
|
3165 |
|
|
I2 => blk00000003_sig00000250,
|
3166 |
|
|
O => blk00000003_sig00000189
|
3167 |
|
|
);
|
3168 |
|
|
blk00000003_blk00000214 : LUT6
|
3169 |
|
|
generic map(
|
3170 |
|
|
INIT => X"0000000000000001"
|
3171 |
|
|
)
|
3172 |
|
|
port map (
|
3173 |
|
|
I0 => sig00000002,
|
3174 |
|
|
I1 => sig00000003,
|
3175 |
|
|
I2 => sig00000004,
|
3176 |
|
|
I3 => sig00000005,
|
3177 |
|
|
I4 => sig00000006,
|
3178 |
|
|
I5 => blk00000003_sig00000370,
|
3179 |
|
|
O => blk00000003_sig0000031b
|
3180 |
|
|
);
|
3181 |
|
|
blk00000003_blk00000213 : LUT3
|
3182 |
|
|
generic map(
|
3183 |
|
|
INIT => X"FE"
|
3184 |
|
|
)
|
3185 |
|
|
port map (
|
3186 |
|
|
I0 => sig00000007,
|
3187 |
|
|
I1 => sig00000008,
|
3188 |
|
|
I2 => sig00000009,
|
3189 |
|
|
O => blk00000003_sig00000370
|
3190 |
|
|
);
|
3191 |
|
|
blk00000003_blk00000212 : LUT4
|
3192 |
|
|
generic map(
|
3193 |
|
|
INIT => X"9009"
|
3194 |
|
|
)
|
3195 |
|
|
port map (
|
3196 |
|
|
I0 => sig00000040,
|
3197 |
|
|
I1 => sig00000020,
|
3198 |
|
|
I2 => sig0000003f,
|
3199 |
|
|
I3 => sig0000001f,
|
3200 |
|
|
O => blk00000003_sig000002b3
|
3201 |
|
|
);
|
3202 |
|
|
blk00000003_blk00000211 : LUT4
|
3203 |
|
|
generic map(
|
3204 |
|
|
INIT => X"8AEF"
|
3205 |
|
|
)
|
3206 |
|
|
port map (
|
3207 |
|
|
I0 => sig0000003f,
|
3208 |
|
|
I1 => sig00000040,
|
3209 |
|
|
I2 => sig00000020,
|
3210 |
|
|
I3 => sig0000001f,
|
3211 |
|
|
O => blk00000003_sig000002b2
|
3212 |
|
|
);
|
3213 |
|
|
blk00000003_blk00000210 : LUT4
|
3214 |
|
|
generic map(
|
3215 |
|
|
INIT => X"9009"
|
3216 |
|
|
)
|
3217 |
|
|
port map (
|
3218 |
|
|
I0 => sig0000003e,
|
3219 |
|
|
I1 => sig0000001e,
|
3220 |
|
|
I2 => sig0000003d,
|
3221 |
|
|
I3 => sig0000001d,
|
3222 |
|
|
O => blk00000003_sig000002b1
|
3223 |
|
|
);
|
3224 |
|
|
blk00000003_blk0000020f : LUT4
|
3225 |
|
|
generic map(
|
3226 |
|
|
INIT => X"8AEF"
|
3227 |
|
|
)
|
3228 |
|
|
port map (
|
3229 |
|
|
I0 => sig0000003d,
|
3230 |
|
|
I1 => sig0000003e,
|
3231 |
|
|
I2 => sig0000001e,
|
3232 |
|
|
I3 => sig0000001d,
|
3233 |
|
|
O => blk00000003_sig000002b0
|
3234 |
|
|
);
|
3235 |
|
|
blk00000003_blk0000020e : LUT2
|
3236 |
|
|
generic map(
|
3237 |
|
|
INIT => X"2"
|
3238 |
|
|
)
|
3239 |
|
|
port map (
|
3240 |
|
|
I0 => blk00000003_sig000000d9,
|
3241 |
|
|
I1 => blk00000003_sig000000d1,
|
3242 |
|
|
O => blk00000003_sig000000cb
|
3243 |
|
|
);
|
3244 |
|
|
blk00000003_blk0000020d : LUT2
|
3245 |
|
|
generic map(
|
3246 |
|
|
INIT => X"8"
|
3247 |
|
|
)
|
3248 |
|
|
port map (
|
3249 |
|
|
I0 => blk00000003_sig000000d1,
|
3250 |
|
|
I1 => blk00000003_sig000000d9,
|
3251 |
|
|
O => blk00000003_sig000000d8
|
3252 |
|
|
);
|
3253 |
|
|
blk00000003_blk0000020c : LUT4
|
3254 |
|
|
generic map(
|
3255 |
|
|
INIT => X"9009"
|
3256 |
|
|
)
|
3257 |
|
|
port map (
|
3258 |
|
|
I0 => sig0000003c,
|
3259 |
|
|
I1 => sig0000001c,
|
3260 |
|
|
I2 => sig0000003b,
|
3261 |
|
|
I3 => sig0000001b,
|
3262 |
|
|
O => blk00000003_sig000002ae
|
3263 |
|
|
);
|
3264 |
|
|
blk00000003_blk0000020b : LUT4
|
3265 |
|
|
generic map(
|
3266 |
|
|
INIT => X"8AEF"
|
3267 |
|
|
)
|
3268 |
|
|
port map (
|
3269 |
|
|
I0 => sig0000003b,
|
3270 |
|
|
I1 => sig0000003c,
|
3271 |
|
|
I2 => sig0000001c,
|
3272 |
|
|
I3 => sig0000001b,
|
3273 |
|
|
O => blk00000003_sig000002ad
|
3274 |
|
|
);
|
3275 |
|
|
blk00000003_blk0000020a : LUT4
|
3276 |
|
|
generic map(
|
3277 |
|
|
INIT => X"9009"
|
3278 |
|
|
)
|
3279 |
|
|
port map (
|
3280 |
|
|
I0 => sig0000003a,
|
3281 |
|
|
I1 => sig0000001a,
|
3282 |
|
|
I2 => sig00000039,
|
3283 |
|
|
I3 => sig00000019,
|
3284 |
|
|
O => blk00000003_sig000002ab
|
3285 |
|
|
);
|
3286 |
|
|
blk00000003_blk00000209 : LUT4
|
3287 |
|
|
generic map(
|
3288 |
|
|
INIT => X"8AEF"
|
3289 |
|
|
)
|
3290 |
|
|
port map (
|
3291 |
|
|
I0 => sig00000039,
|
3292 |
|
|
I1 => sig0000003a,
|
3293 |
|
|
I2 => sig0000001a,
|
3294 |
|
|
I3 => sig00000019,
|
3295 |
|
|
O => blk00000003_sig000002aa
|
3296 |
|
|
);
|
3297 |
|
|
blk00000003_blk00000208 : LUT4
|
3298 |
|
|
generic map(
|
3299 |
|
|
INIT => X"9009"
|
3300 |
|
|
)
|
3301 |
|
|
port map (
|
3302 |
|
|
I0 => sig00000038,
|
3303 |
|
|
I1 => sig00000018,
|
3304 |
|
|
I2 => sig00000037,
|
3305 |
|
|
I3 => sig00000017,
|
3306 |
|
|
O => blk00000003_sig000002a8
|
3307 |
|
|
);
|
3308 |
|
|
blk00000003_blk00000207 : LUT4
|
3309 |
|
|
generic map(
|
3310 |
|
|
INIT => X"8AEF"
|
3311 |
|
|
)
|
3312 |
|
|
port map (
|
3313 |
|
|
I0 => sig00000037,
|
3314 |
|
|
I1 => sig00000038,
|
3315 |
|
|
I2 => sig00000018,
|
3316 |
|
|
I3 => sig00000017,
|
3317 |
|
|
O => blk00000003_sig000002a7
|
3318 |
|
|
);
|
3319 |
|
|
blk00000003_blk00000206 : LUT3
|
3320 |
|
|
generic map(
|
3321 |
|
|
INIT => X"E4"
|
3322 |
|
|
)
|
3323 |
|
|
port map (
|
3324 |
|
|
I0 => blk00000003_sig00000354,
|
3325 |
|
|
I1 => blk00000003_sig00000364,
|
3326 |
|
|
I2 => blk00000003_sig0000035c,
|
3327 |
|
|
O => blk00000003_sig000002ca
|
3328 |
|
|
);
|
3329 |
|
|
blk00000003_blk00000205 : LUT4
|
3330 |
|
|
generic map(
|
3331 |
|
|
INIT => X"9009"
|
3332 |
|
|
)
|
3333 |
|
|
port map (
|
3334 |
|
|
I0 => sig00000036,
|
3335 |
|
|
I1 => sig00000016,
|
3336 |
|
|
I2 => sig00000035,
|
3337 |
|
|
I3 => sig00000015,
|
3338 |
|
|
O => blk00000003_sig000002a5
|
3339 |
|
|
);
|
3340 |
|
|
blk00000003_blk00000204 : LUT4
|
3341 |
|
|
generic map(
|
3342 |
|
|
INIT => X"8AEF"
|
3343 |
|
|
)
|
3344 |
|
|
port map (
|
3345 |
|
|
I0 => sig00000035,
|
3346 |
|
|
I1 => sig00000036,
|
3347 |
|
|
I2 => sig00000016,
|
3348 |
|
|
I3 => sig00000015,
|
3349 |
|
|
O => blk00000003_sig000002a4
|
3350 |
|
|
);
|
3351 |
|
|
blk00000003_blk00000203 : LUT4
|
3352 |
|
|
generic map(
|
3353 |
|
|
INIT => X"9009"
|
3354 |
|
|
)
|
3355 |
|
|
port map (
|
3356 |
|
|
I0 => sig00000034,
|
3357 |
|
|
I1 => sig00000014,
|
3358 |
|
|
I2 => sig00000033,
|
3359 |
|
|
I3 => sig00000013,
|
3360 |
|
|
O => blk00000003_sig000002a2
|
3361 |
|
|
);
|
3362 |
|
|
blk00000003_blk00000202 : LUT4
|
3363 |
|
|
generic map(
|
3364 |
|
|
INIT => X"8AEF"
|
3365 |
|
|
)
|
3366 |
|
|
port map (
|
3367 |
|
|
I0 => sig00000033,
|
3368 |
|
|
I1 => sig00000034,
|
3369 |
|
|
I2 => sig00000014,
|
3370 |
|
|
I3 => sig00000013,
|
3371 |
|
|
O => blk00000003_sig000002a1
|
3372 |
|
|
);
|
3373 |
|
|
blk00000003_blk00000201 : LUT4
|
3374 |
|
|
generic map(
|
3375 |
|
|
INIT => X"9009"
|
3376 |
|
|
)
|
3377 |
|
|
port map (
|
3378 |
|
|
I0 => sig00000032,
|
3379 |
|
|
I1 => sig00000012,
|
3380 |
|
|
I2 => sig00000031,
|
3381 |
|
|
I3 => sig00000011,
|
3382 |
|
|
O => blk00000003_sig0000029f
|
3383 |
|
|
);
|
3384 |
|
|
blk00000003_blk00000200 : LUT6
|
3385 |
|
|
generic map(
|
3386 |
|
|
INIT => X"FBEAEAEA51404040"
|
3387 |
|
|
)
|
3388 |
|
|
port map (
|
3389 |
|
|
I0 => blk00000003_sig00000240,
|
3390 |
|
|
I1 => blk00000003_sig00000241,
|
3391 |
|
|
I2 => blk00000003_sig00000258,
|
3392 |
|
|
I3 => blk00000003_sig00000242,
|
3393 |
|
|
I4 => blk00000003_sig00000259,
|
3394 |
|
|
I5 => blk00000003_sig00000257,
|
3395 |
|
|
O => blk00000003_sig000001ae
|
3396 |
|
|
);
|
3397 |
|
|
blk00000003_blk000001ff : LUT6
|
3398 |
|
|
generic map(
|
3399 |
|
|
INIT => X"FBEAEAEA51404040"
|
3400 |
|
|
)
|
3401 |
|
|
port map (
|
3402 |
|
|
I0 => blk00000003_sig00000240,
|
3403 |
|
|
I1 => blk00000003_sig00000241,
|
3404 |
|
|
I2 => blk00000003_sig00000259,
|
3405 |
|
|
I3 => blk00000003_sig00000242,
|
3406 |
|
|
I4 => blk00000003_sig0000025a,
|
3407 |
|
|
I5 => blk00000003_sig00000258,
|
3408 |
|
|
O => blk00000003_sig000001ab
|
3409 |
|
|
);
|
3410 |
|
|
blk00000003_blk000001fe : LUT4
|
3411 |
|
|
generic map(
|
3412 |
|
|
INIT => X"8AEF"
|
3413 |
|
|
)
|
3414 |
|
|
port map (
|
3415 |
|
|
I0 => sig00000031,
|
3416 |
|
|
I1 => sig00000032,
|
3417 |
|
|
I2 => sig00000012,
|
3418 |
|
|
I3 => sig00000011,
|
3419 |
|
|
O => blk00000003_sig0000029e
|
3420 |
|
|
);
|
3421 |
|
|
blk00000003_blk000001fd : LUT4
|
3422 |
|
|
generic map(
|
3423 |
|
|
INIT => X"151F"
|
3424 |
|
|
)
|
3425 |
|
|
port map (
|
3426 |
|
|
I0 => blk00000003_sig00000240,
|
3427 |
|
|
I1 => blk00000003_sig00000241,
|
3428 |
|
|
I2 => blk00000003_sig0000025a,
|
3429 |
|
|
I3 => blk00000003_sig00000259,
|
3430 |
|
|
O => blk00000003_sig000001b1
|
3431 |
|
|
);
|
3432 |
|
|
blk00000003_blk000001fc : LUT4
|
3433 |
|
|
generic map(
|
3434 |
|
|
INIT => X"9009"
|
3435 |
|
|
)
|
3436 |
|
|
port map (
|
3437 |
|
|
I0 => sig00000030,
|
3438 |
|
|
I1 => sig00000010,
|
3439 |
|
|
I2 => sig0000002f,
|
3440 |
|
|
I3 => sig0000000f,
|
3441 |
|
|
O => blk00000003_sig0000029c
|
3442 |
|
|
);
|
3443 |
|
|
blk00000003_blk000001fb : LUT6
|
3444 |
|
|
generic map(
|
3445 |
|
|
INIT => X"8000000000000000"
|
3446 |
|
|
)
|
3447 |
|
|
port map (
|
3448 |
|
|
I0 => sig00000002,
|
3449 |
|
|
I1 => sig00000003,
|
3450 |
|
|
I2 => sig00000004,
|
3451 |
|
|
I3 => sig00000005,
|
3452 |
|
|
I4 => sig00000006,
|
3453 |
|
|
I5 => blk00000003_sig0000036f,
|
3454 |
|
|
O => blk00000003_sig00000319
|
3455 |
|
|
);
|
3456 |
|
|
blk00000003_blk000001fa : LUT3
|
3457 |
|
|
generic map(
|
3458 |
|
|
INIT => X"80"
|
3459 |
|
|
)
|
3460 |
|
|
port map (
|
3461 |
|
|
I0 => sig00000007,
|
3462 |
|
|
I1 => sig00000008,
|
3463 |
|
|
I2 => sig00000009,
|
3464 |
|
|
O => blk00000003_sig0000036f
|
3465 |
|
|
);
|
3466 |
|
|
blk00000003_blk000001f9 : LUT6
|
3467 |
|
|
generic map(
|
3468 |
|
|
INIT => X"8000000000000000"
|
3469 |
|
|
)
|
3470 |
|
|
port map (
|
3471 |
|
|
I0 => sig00000022,
|
3472 |
|
|
I1 => sig00000023,
|
3473 |
|
|
I2 => sig00000024,
|
3474 |
|
|
I3 => sig00000025,
|
3475 |
|
|
I4 => sig00000026,
|
3476 |
|
|
I5 => blk00000003_sig0000036e,
|
3477 |
|
|
O => blk00000003_sig0000031e
|
3478 |
|
|
);
|
3479 |
|
|
blk00000003_blk000001f8 : LUT3
|
3480 |
|
|
generic map(
|
3481 |
|
|
INIT => X"80"
|
3482 |
|
|
)
|
3483 |
|
|
port map (
|
3484 |
|
|
I0 => sig00000027,
|
3485 |
|
|
I1 => sig00000028,
|
3486 |
|
|
I2 => sig00000029,
|
3487 |
|
|
O => blk00000003_sig0000036e
|
3488 |
|
|
);
|
3489 |
|
|
blk00000003_blk000001f7 : LUT6
|
3490 |
|
|
generic map(
|
3491 |
|
|
INIT => X"0000000000000001"
|
3492 |
|
|
)
|
3493 |
|
|
port map (
|
3494 |
|
|
I0 => sig00000022,
|
3495 |
|
|
I1 => sig00000023,
|
3496 |
|
|
I2 => sig00000024,
|
3497 |
|
|
I3 => sig00000025,
|
3498 |
|
|
I4 => sig00000026,
|
3499 |
|
|
I5 => blk00000003_sig0000036d,
|
3500 |
|
|
O => blk00000003_sig00000320
|
3501 |
|
|
);
|
3502 |
|
|
blk00000003_blk000001f6 : LUT3
|
3503 |
|
|
generic map(
|
3504 |
|
|
INIT => X"FE"
|
3505 |
|
|
)
|
3506 |
|
|
port map (
|
3507 |
|
|
I0 => sig00000027,
|
3508 |
|
|
I1 => sig00000028,
|
3509 |
|
|
I2 => sig00000029,
|
3510 |
|
|
O => blk00000003_sig0000036d
|
3511 |
|
|
);
|
3512 |
|
|
blk00000003_blk000001f5 : LUT4
|
3513 |
|
|
generic map(
|
3514 |
|
|
INIT => X"8AEF"
|
3515 |
|
|
)
|
3516 |
|
|
port map (
|
3517 |
|
|
I0 => sig0000002f,
|
3518 |
|
|
I1 => sig00000030,
|
3519 |
|
|
I2 => sig00000010,
|
3520 |
|
|
I3 => sig0000000f,
|
3521 |
|
|
O => blk00000003_sig0000029b
|
3522 |
|
|
);
|
3523 |
|
|
blk00000003_blk000001f4 : LUT4
|
3524 |
|
|
generic map(
|
3525 |
|
|
INIT => X"9009"
|
3526 |
|
|
)
|
3527 |
|
|
port map (
|
3528 |
|
|
I0 => sig0000002e,
|
3529 |
|
|
I1 => sig0000000e,
|
3530 |
|
|
I2 => sig0000002d,
|
3531 |
|
|
I3 => sig0000000d,
|
3532 |
|
|
O => blk00000003_sig00000299
|
3533 |
|
|
);
|
3534 |
|
|
blk00000003_blk000001f3 : LUT4
|
3535 |
|
|
generic map(
|
3536 |
|
|
INIT => X"8AEF"
|
3537 |
|
|
)
|
3538 |
|
|
port map (
|
3539 |
|
|
I0 => sig0000002d,
|
3540 |
|
|
I1 => sig0000002e,
|
3541 |
|
|
I2 => sig0000000e,
|
3542 |
|
|
I3 => sig0000000d,
|
3543 |
|
|
O => blk00000003_sig00000298
|
3544 |
|
|
);
|
3545 |
|
|
blk00000003_blk000001f2 : LUT4
|
3546 |
|
|
generic map(
|
3547 |
|
|
INIT => X"9009"
|
3548 |
|
|
)
|
3549 |
|
|
port map (
|
3550 |
|
|
I0 => sig0000002c,
|
3551 |
|
|
I1 => sig0000000c,
|
3552 |
|
|
I2 => sig0000002b,
|
3553 |
|
|
I3 => sig0000000b,
|
3554 |
|
|
O => blk00000003_sig00000296
|
3555 |
|
|
);
|
3556 |
|
|
blk00000003_blk000001f1 : LUT4
|
3557 |
|
|
generic map(
|
3558 |
|
|
INIT => X"8AEF"
|
3559 |
|
|
)
|
3560 |
|
|
port map (
|
3561 |
|
|
I0 => sig0000002b,
|
3562 |
|
|
I1 => sig0000002c,
|
3563 |
|
|
I2 => sig0000000c,
|
3564 |
|
|
I3 => sig0000000b,
|
3565 |
|
|
O => blk00000003_sig00000295
|
3566 |
|
|
);
|
3567 |
|
|
blk00000003_blk000001f0 : LUT6
|
3568 |
|
|
generic map(
|
3569 |
|
|
INIT => X"FFFFFFFFFFFFFFFE"
|
3570 |
|
|
)
|
3571 |
|
|
port map (
|
3572 |
|
|
I0 => blk00000003_sig0000036c,
|
3573 |
|
|
I1 => blk00000003_sig0000032b,
|
3574 |
|
|
I2 => blk00000003_sig0000032d,
|
3575 |
|
|
I3 => blk00000003_sig0000032f,
|
3576 |
|
|
I4 => blk00000003_sig00000369,
|
3577 |
|
|
I5 => blk00000003_sig0000036a,
|
3578 |
|
|
O => blk00000003_sig00000327
|
3579 |
|
|
);
|
3580 |
|
|
blk00000003_blk000001ef : LUT6
|
3581 |
|
|
generic map(
|
3582 |
|
|
INIT => X"AAAAAAAAAAAAABAA"
|
3583 |
|
|
)
|
3584 |
|
|
port map (
|
3585 |
|
|
I0 => blk00000003_sig00000369,
|
3586 |
|
|
I1 => blk00000003_sig0000036a,
|
3587 |
|
|
I2 => blk00000003_sig0000036c,
|
3588 |
|
|
I3 => blk00000003_sig0000032b,
|
3589 |
|
|
I4 => blk00000003_sig0000032d,
|
3590 |
|
|
I5 => blk00000003_sig0000032f,
|
3591 |
|
|
O => blk00000003_sig00000323
|
3592 |
|
|
);
|
3593 |
|
|
blk00000003_blk000001ee : LUT6
|
3594 |
|
|
generic map(
|
3595 |
|
|
INIT => X"FFFFFFFF55555554"
|
3596 |
|
|
)
|
3597 |
|
|
port map (
|
3598 |
|
|
I0 => blk00000003_sig00000369,
|
3599 |
|
|
I1 => blk00000003_sig0000036c,
|
3600 |
|
|
I2 => blk00000003_sig0000032b,
|
3601 |
|
|
I3 => blk00000003_sig0000032d,
|
3602 |
|
|
I4 => blk00000003_sig0000032f,
|
3603 |
|
|
I5 => blk00000003_sig0000036a,
|
3604 |
|
|
O => blk00000003_sig00000326
|
3605 |
|
|
);
|
3606 |
|
|
blk00000003_blk000001ed : LUT5
|
3607 |
|
|
generic map(
|
3608 |
|
|
INIT => X"AAAAAAA9"
|
3609 |
|
|
)
|
3610 |
|
|
port map (
|
3611 |
|
|
I0 => blk00000003_sig000000d1,
|
3612 |
|
|
I1 => blk00000003_sig000000d3,
|
3613 |
|
|
I2 => blk00000003_sig000000d5,
|
3614 |
|
|
I3 => blk00000003_sig000000cf,
|
3615 |
|
|
I4 => blk00000003_sig000000cd,
|
3616 |
|
|
O => blk00000003_sig000000d0
|
3617 |
|
|
);
|
3618 |
|
|
blk00000003_blk000001ec : LUT5
|
3619 |
|
|
generic map(
|
3620 |
|
|
INIT => X"55555554"
|
3621 |
|
|
)
|
3622 |
|
|
port map (
|
3623 |
|
|
I0 => blk00000003_sig00000369,
|
3624 |
|
|
I1 => blk00000003_sig0000036c,
|
3625 |
|
|
I2 => blk00000003_sig0000036a,
|
3626 |
|
|
I3 => blk00000003_sig0000032d,
|
3627 |
|
|
I4 => blk00000003_sig0000032f,
|
3628 |
|
|
O => blk00000003_sig00000324
|
3629 |
|
|
);
|
3630 |
|
|
blk00000003_blk000001eb : LUT4
|
3631 |
|
|
generic map(
|
3632 |
|
|
INIT => X"9009"
|
3633 |
|
|
)
|
3634 |
|
|
port map (
|
3635 |
|
|
I0 => sig0000002a,
|
3636 |
|
|
I1 => sig0000000a,
|
3637 |
|
|
I2 => sig00000029,
|
3638 |
|
|
I3 => sig00000009,
|
3639 |
|
|
O => blk00000003_sig00000293
|
3640 |
|
|
);
|
3641 |
|
|
blk00000003_blk000001ea : LUT4
|
3642 |
|
|
generic map(
|
3643 |
|
|
INIT => X"CCC9"
|
3644 |
|
|
)
|
3645 |
|
|
port map (
|
3646 |
|
|
I0 => blk00000003_sig000000d3,
|
3647 |
|
|
I1 => blk00000003_sig000000cd,
|
3648 |
|
|
I2 => blk00000003_sig000000d5,
|
3649 |
|
|
I3 => blk00000003_sig000000cf,
|
3650 |
|
|
O => blk00000003_sig000000cc
|
3651 |
|
|
);
|
3652 |
|
|
blk00000003_blk000001e9 : LUT4
|
3653 |
|
|
generic map(
|
3654 |
|
|
INIT => X"EC4C"
|
3655 |
|
|
)
|
3656 |
|
|
port map (
|
3657 |
|
|
I0 => blk00000003_sig0000031a,
|
3658 |
|
|
I1 => blk00000003_sig00000366,
|
3659 |
|
|
I2 => blk00000003_sig0000031d,
|
3660 |
|
|
I3 => blk00000003_sig00000365,
|
3661 |
|
|
O => blk00000003_sig00000345
|
3662 |
|
|
);
|
3663 |
|
|
blk00000003_blk000001e8 : LUT4
|
3664 |
|
|
generic map(
|
3665 |
|
|
INIT => X"0200"
|
3666 |
|
|
)
|
3667 |
|
|
port map (
|
3668 |
|
|
I0 => blk00000003_sig00000138,
|
3669 |
|
|
I1 => blk00000003_sig0000013a,
|
3670 |
|
|
I2 => blk00000003_sig0000017e,
|
3671 |
|
|
I3 => blk00000003_sig0000017d,
|
3672 |
|
|
O => blk00000003_sig00000147
|
3673 |
|
|
);
|
3674 |
|
|
blk00000003_blk000001e7 : LUT4
|
3675 |
|
|
generic map(
|
3676 |
|
|
INIT => X"0200"
|
3677 |
|
|
)
|
3678 |
|
|
port map (
|
3679 |
|
|
I0 => blk00000003_sig0000013a,
|
3680 |
|
|
I1 => blk00000003_sig0000013c,
|
3681 |
|
|
I2 => blk00000003_sig00000186,
|
3682 |
|
|
I3 => blk00000003_sig00000185,
|
3683 |
|
|
O => blk00000003_sig00000143
|
3684 |
|
|
);
|
3685 |
|
|
blk00000003_blk000001e6 : LUT4
|
3686 |
|
|
generic map(
|
3687 |
|
|
INIT => X"0200"
|
3688 |
|
|
)
|
3689 |
|
|
port map (
|
3690 |
|
|
I0 => blk00000003_sig0000013c,
|
3691 |
|
|
I1 => blk00000003_sig0000013e,
|
3692 |
|
|
I2 => blk00000003_sig00000184,
|
3693 |
|
|
I3 => blk00000003_sig00000183,
|
3694 |
|
|
O => blk00000003_sig0000013f
|
3695 |
|
|
);
|
3696 |
|
|
blk00000003_blk000001e5 : LUT4
|
3697 |
|
|
generic map(
|
3698 |
|
|
INIT => X"0200"
|
3699 |
|
|
)
|
3700 |
|
|
port map (
|
3701 |
|
|
I0 => blk00000003_sig00000130,
|
3702 |
|
|
I1 => blk00000003_sig00000132,
|
3703 |
|
|
I2 => blk00000003_sig00000172,
|
3704 |
|
|
I3 => blk00000003_sig00000171,
|
3705 |
|
|
O => blk00000003_sig00000157
|
3706 |
|
|
);
|
3707 |
|
|
blk00000003_blk000001e4 : LUT4
|
3708 |
|
|
generic map(
|
3709 |
|
|
INIT => X"0200"
|
3710 |
|
|
)
|
3711 |
|
|
port map (
|
3712 |
|
|
I0 => blk00000003_sig00000132,
|
3713 |
|
|
I1 => blk00000003_sig00000134,
|
3714 |
|
|
I2 => blk00000003_sig0000017a,
|
3715 |
|
|
I3 => blk00000003_sig00000179,
|
3716 |
|
|
O => blk00000003_sig00000153
|
3717 |
|
|
);
|
3718 |
|
|
blk00000003_blk000001e3 : LUT4
|
3719 |
|
|
generic map(
|
3720 |
|
|
INIT => X"0200"
|
3721 |
|
|
)
|
3722 |
|
|
port map (
|
3723 |
|
|
I0 => blk00000003_sig00000134,
|
3724 |
|
|
I1 => blk00000003_sig00000136,
|
3725 |
|
|
I2 => blk00000003_sig00000178,
|
3726 |
|
|
I3 => blk00000003_sig00000177,
|
3727 |
|
|
O => blk00000003_sig0000014f
|
3728 |
|
|
);
|
3729 |
|
|
blk00000003_blk000001e2 : LUT4
|
3730 |
|
|
generic map(
|
3731 |
|
|
INIT => X"0200"
|
3732 |
|
|
)
|
3733 |
|
|
port map (
|
3734 |
|
|
I0 => blk00000003_sig00000136,
|
3735 |
|
|
I1 => blk00000003_sig00000138,
|
3736 |
|
|
I2 => blk00000003_sig00000180,
|
3737 |
|
|
I3 => blk00000003_sig0000017f,
|
3738 |
|
|
O => blk00000003_sig0000014b
|
3739 |
|
|
);
|
3740 |
|
|
blk00000003_blk000001e1 : LUT4
|
3741 |
|
|
generic map(
|
3742 |
|
|
INIT => X"8000"
|
3743 |
|
|
)
|
3744 |
|
|
port map (
|
3745 |
|
|
I0 => blk00000003_sig0000031f,
|
3746 |
|
|
I1 => blk00000003_sig00000322,
|
3747 |
|
|
I2 => blk00000003_sig0000031a,
|
3748 |
|
|
I3 => blk00000003_sig0000031d,
|
3749 |
|
|
O => blk00000003_sig0000033f
|
3750 |
|
|
);
|
3751 |
|
|
blk00000003_blk000001e0 : LUT4
|
3752 |
|
|
generic map(
|
3753 |
|
|
INIT => X"F888"
|
3754 |
|
|
)
|
3755 |
|
|
port map (
|
3756 |
|
|
I0 => blk00000003_sig0000031f,
|
3757 |
|
|
I1 => blk00000003_sig00000322,
|
3758 |
|
|
I2 => blk00000003_sig0000031a,
|
3759 |
|
|
I3 => blk00000003_sig0000031d,
|
3760 |
|
|
O => blk00000003_sig00000341
|
3761 |
|
|
);
|
3762 |
|
|
blk00000003_blk000001df : LUT4
|
3763 |
|
|
generic map(
|
3764 |
|
|
INIT => X"22F2"
|
3765 |
|
|
)
|
3766 |
|
|
port map (
|
3767 |
|
|
I0 => blk00000003_sig0000031a,
|
3768 |
|
|
I1 => blk00000003_sig0000031d,
|
3769 |
|
|
I2 => blk00000003_sig0000031f,
|
3770 |
|
|
I3 => blk00000003_sig00000322,
|
3771 |
|
|
O => blk00000003_sig0000033d
|
3772 |
|
|
);
|
3773 |
|
|
blk00000003_blk000001de : LUT4
|
3774 |
|
|
generic map(
|
3775 |
|
|
INIT => X"A8AA"
|
3776 |
|
|
)
|
3777 |
|
|
port map (
|
3778 |
|
|
I0 => blk00000003_sig0000036b,
|
3779 |
|
|
I1 => blk00000003_sig0000036a,
|
3780 |
|
|
I2 => blk00000003_sig00000369,
|
3781 |
|
|
I3 => blk00000003_sig0000036c,
|
3782 |
|
|
O => blk00000003_sig0000034b
|
3783 |
|
|
);
|
3784 |
|
|
blk00000003_blk000001dd : LUT3
|
3785 |
|
|
generic map(
|
3786 |
|
|
INIT => X"C9"
|
3787 |
|
|
)
|
3788 |
|
|
port map (
|
3789 |
|
|
I0 => blk00000003_sig000000d3,
|
3790 |
|
|
I1 => blk00000003_sig000000cf,
|
3791 |
|
|
I2 => blk00000003_sig000000d5,
|
3792 |
|
|
O => blk00000003_sig000000ce
|
3793 |
|
|
);
|
3794 |
|
|
blk00000003_blk000001dc : LUT3
|
3795 |
|
|
generic map(
|
3796 |
|
|
INIT => X"E4"
|
3797 |
|
|
)
|
3798 |
|
|
port map (
|
3799 |
|
|
I0 => blk00000003_sig000002b4,
|
3800 |
|
|
I1 => blk00000003_sig00000109,
|
3801 |
|
|
I2 => blk00000003_sig000000f2,
|
3802 |
|
|
O => blk00000003_sig000001c8
|
3803 |
|
|
);
|
3804 |
|
|
blk00000003_blk000001db : LUT3
|
3805 |
|
|
generic map(
|
3806 |
|
|
INIT => X"E4"
|
3807 |
|
|
)
|
3808 |
|
|
port map (
|
3809 |
|
|
I0 => blk00000003_sig000002b4,
|
3810 |
|
|
I1 => blk00000003_sig000000ff,
|
3811 |
|
|
I2 => blk00000003_sig000000e8,
|
3812 |
|
|
O => blk00000003_sig000001dc
|
3813 |
|
|
);
|
3814 |
|
|
blk00000003_blk000001da : LUT3
|
3815 |
|
|
generic map(
|
3816 |
|
|
INIT => X"E4"
|
3817 |
|
|
)
|
3818 |
|
|
port map (
|
3819 |
|
|
I0 => blk00000003_sig000002b4,
|
3820 |
|
|
I1 => blk00000003_sig000000fe,
|
3821 |
|
|
I2 => blk00000003_sig000000e7,
|
3822 |
|
|
O => blk00000003_sig000001de
|
3823 |
|
|
);
|
3824 |
|
|
blk00000003_blk000001d9 : LUT3
|
3825 |
|
|
generic map(
|
3826 |
|
|
INIT => X"E4"
|
3827 |
|
|
)
|
3828 |
|
|
port map (
|
3829 |
|
|
I0 => blk00000003_sig000002b4,
|
3830 |
|
|
I1 => blk00000003_sig000000fd,
|
3831 |
|
|
I2 => blk00000003_sig000000e6,
|
3832 |
|
|
O => blk00000003_sig000001e0
|
3833 |
|
|
);
|
3834 |
|
|
blk00000003_blk000001d8 : LUT3
|
3835 |
|
|
generic map(
|
3836 |
|
|
INIT => X"E4"
|
3837 |
|
|
)
|
3838 |
|
|
port map (
|
3839 |
|
|
I0 => blk00000003_sig000002b4,
|
3840 |
|
|
I1 => blk00000003_sig000000fc,
|
3841 |
|
|
I2 => blk00000003_sig000000e5,
|
3842 |
|
|
O => blk00000003_sig000001e2
|
3843 |
|
|
);
|
3844 |
|
|
blk00000003_blk000001d7 : LUT3
|
3845 |
|
|
generic map(
|
3846 |
|
|
INIT => X"E4"
|
3847 |
|
|
)
|
3848 |
|
|
port map (
|
3849 |
|
|
I0 => blk00000003_sig000002b4,
|
3850 |
|
|
I1 => blk00000003_sig000000fb,
|
3851 |
|
|
I2 => blk00000003_sig000000e4,
|
3852 |
|
|
O => blk00000003_sig000001e4
|
3853 |
|
|
);
|
3854 |
|
|
blk00000003_blk000001d6 : LUT3
|
3855 |
|
|
generic map(
|
3856 |
|
|
INIT => X"E4"
|
3857 |
|
|
)
|
3858 |
|
|
port map (
|
3859 |
|
|
I0 => blk00000003_sig000002b4,
|
3860 |
|
|
I1 => blk00000003_sig000000fa,
|
3861 |
|
|
I2 => blk00000003_sig000000e3,
|
3862 |
|
|
O => blk00000003_sig000001e6
|
3863 |
|
|
);
|
3864 |
|
|
blk00000003_blk000001d5 : LUT3
|
3865 |
|
|
generic map(
|
3866 |
|
|
INIT => X"E4"
|
3867 |
|
|
)
|
3868 |
|
|
port map (
|
3869 |
|
|
I0 => blk00000003_sig000002b4,
|
3870 |
|
|
I1 => blk00000003_sig000000f9,
|
3871 |
|
|
I2 => blk00000003_sig000000e2,
|
3872 |
|
|
O => blk00000003_sig000001e8
|
3873 |
|
|
);
|
3874 |
|
|
blk00000003_blk000001d4 : LUT3
|
3875 |
|
|
generic map(
|
3876 |
|
|
INIT => X"E4"
|
3877 |
|
|
)
|
3878 |
|
|
port map (
|
3879 |
|
|
I0 => blk00000003_sig000002b4,
|
3880 |
|
|
I1 => blk00000003_sig000000f8,
|
3881 |
|
|
I2 => blk00000003_sig000000e1,
|
3882 |
|
|
O => blk00000003_sig000001ea
|
3883 |
|
|
);
|
3884 |
|
|
blk00000003_blk000001d3 : LUT3
|
3885 |
|
|
generic map(
|
3886 |
|
|
INIT => X"E4"
|
3887 |
|
|
)
|
3888 |
|
|
port map (
|
3889 |
|
|
I0 => blk00000003_sig000002b4,
|
3890 |
|
|
I1 => blk00000003_sig000000f7,
|
3891 |
|
|
I2 => blk00000003_sig000000e0,
|
3892 |
|
|
O => blk00000003_sig000001ec
|
3893 |
|
|
);
|
3894 |
|
|
blk00000003_blk000001d2 : LUT3
|
3895 |
|
|
generic map(
|
3896 |
|
|
INIT => X"E4"
|
3897 |
|
|
)
|
3898 |
|
|
port map (
|
3899 |
|
|
I0 => blk00000003_sig000002b4,
|
3900 |
|
|
I1 => blk00000003_sig000000f6,
|
3901 |
|
|
I2 => blk00000003_sig000000df,
|
3902 |
|
|
O => blk00000003_sig000001ee
|
3903 |
|
|
);
|
3904 |
|
|
blk00000003_blk000001d1 : LUT3
|
3905 |
|
|
generic map(
|
3906 |
|
|
INIT => X"E4"
|
3907 |
|
|
)
|
3908 |
|
|
port map (
|
3909 |
|
|
I0 => blk00000003_sig000002b4,
|
3910 |
|
|
I1 => blk00000003_sig00000108,
|
3911 |
|
|
I2 => blk00000003_sig000000f1,
|
3912 |
|
|
O => blk00000003_sig000001ca
|
3913 |
|
|
);
|
3914 |
|
|
blk00000003_blk000001d0 : LUT3
|
3915 |
|
|
generic map(
|
3916 |
|
|
INIT => X"E4"
|
3917 |
|
|
)
|
3918 |
|
|
port map (
|
3919 |
|
|
I0 => blk00000003_sig000002b4,
|
3920 |
|
|
I1 => blk00000003_sig000000f5,
|
3921 |
|
|
I2 => blk00000003_sig000000de,
|
3922 |
|
|
O => blk00000003_sig000001f0
|
3923 |
|
|
);
|
3924 |
|
|
blk00000003_blk000001cf : LUT3
|
3925 |
|
|
generic map(
|
3926 |
|
|
INIT => X"E4"
|
3927 |
|
|
)
|
3928 |
|
|
port map (
|
3929 |
|
|
I0 => blk00000003_sig000002b4,
|
3930 |
|
|
I1 => blk00000003_sig000000f4,
|
3931 |
|
|
I2 => blk00000003_sig000000dd,
|
3932 |
|
|
O => blk00000003_sig000001f2
|
3933 |
|
|
);
|
3934 |
|
|
blk00000003_blk000001ce : LUT3
|
3935 |
|
|
generic map(
|
3936 |
|
|
INIT => X"E4"
|
3937 |
|
|
)
|
3938 |
|
|
port map (
|
3939 |
|
|
I0 => blk00000003_sig000002b4,
|
3940 |
|
|
I1 => blk00000003_sig000000f3,
|
3941 |
|
|
I2 => blk00000003_sig000000dc,
|
3942 |
|
|
O => blk00000003_sig000001f4
|
3943 |
|
|
);
|
3944 |
|
|
blk00000003_blk000001cd : LUT3
|
3945 |
|
|
generic map(
|
3946 |
|
|
INIT => X"E4"
|
3947 |
|
|
)
|
3948 |
|
|
port map (
|
3949 |
|
|
I0 => blk00000003_sig000002b4,
|
3950 |
|
|
I1 => blk00000003_sig00000107,
|
3951 |
|
|
I2 => blk00000003_sig000000f0,
|
3952 |
|
|
O => blk00000003_sig000001cc
|
3953 |
|
|
);
|
3954 |
|
|
blk00000003_blk000001cc : LUT3
|
3955 |
|
|
generic map(
|
3956 |
|
|
INIT => X"E4"
|
3957 |
|
|
)
|
3958 |
|
|
port map (
|
3959 |
|
|
I0 => blk00000003_sig000002b4,
|
3960 |
|
|
I1 => blk00000003_sig00000106,
|
3961 |
|
|
I2 => blk00000003_sig000000ef,
|
3962 |
|
|
O => blk00000003_sig000001ce
|
3963 |
|
|
);
|
3964 |
|
|
blk00000003_blk000001cb : LUT3
|
3965 |
|
|
generic map(
|
3966 |
|
|
INIT => X"E4"
|
3967 |
|
|
)
|
3968 |
|
|
port map (
|
3969 |
|
|
I0 => blk00000003_sig000002b4,
|
3970 |
|
|
I1 => blk00000003_sig00000105,
|
3971 |
|
|
I2 => blk00000003_sig000000ee,
|
3972 |
|
|
O => blk00000003_sig000001d0
|
3973 |
|
|
);
|
3974 |
|
|
blk00000003_blk000001ca : LUT3
|
3975 |
|
|
generic map(
|
3976 |
|
|
INIT => X"E4"
|
3977 |
|
|
)
|
3978 |
|
|
port map (
|
3979 |
|
|
I0 => blk00000003_sig000002b4,
|
3980 |
|
|
I1 => blk00000003_sig00000104,
|
3981 |
|
|
I2 => blk00000003_sig000000ed,
|
3982 |
|
|
O => blk00000003_sig000001d2
|
3983 |
|
|
);
|
3984 |
|
|
blk00000003_blk000001c9 : LUT3
|
3985 |
|
|
generic map(
|
3986 |
|
|
INIT => X"E4"
|
3987 |
|
|
)
|
3988 |
|
|
port map (
|
3989 |
|
|
I0 => blk00000003_sig000002b4,
|
3990 |
|
|
I1 => blk00000003_sig00000103,
|
3991 |
|
|
I2 => blk00000003_sig000000ec,
|
3992 |
|
|
O => blk00000003_sig000001d4
|
3993 |
|
|
);
|
3994 |
|
|
blk00000003_blk000001c8 : LUT3
|
3995 |
|
|
generic map(
|
3996 |
|
|
INIT => X"E4"
|
3997 |
|
|
)
|
3998 |
|
|
port map (
|
3999 |
|
|
I0 => blk00000003_sig000002b4,
|
4000 |
|
|
I1 => blk00000003_sig00000102,
|
4001 |
|
|
I2 => blk00000003_sig000000eb,
|
4002 |
|
|
O => blk00000003_sig000001d6
|
4003 |
|
|
);
|
4004 |
|
|
blk00000003_blk000001c7 : LUT3
|
4005 |
|
|
generic map(
|
4006 |
|
|
INIT => X"E4"
|
4007 |
|
|
)
|
4008 |
|
|
port map (
|
4009 |
|
|
I0 => blk00000003_sig000002b4,
|
4010 |
|
|
I1 => blk00000003_sig00000101,
|
4011 |
|
|
I2 => blk00000003_sig000000ea,
|
4012 |
|
|
O => blk00000003_sig000001d8
|
4013 |
|
|
);
|
4014 |
|
|
blk00000003_blk000001c6 : LUT3
|
4015 |
|
|
generic map(
|
4016 |
|
|
INIT => X"E4"
|
4017 |
|
|
)
|
4018 |
|
|
port map (
|
4019 |
|
|
I0 => blk00000003_sig000002b4,
|
4020 |
|
|
I1 => blk00000003_sig00000100,
|
4021 |
|
|
I2 => blk00000003_sig000000e9,
|
4022 |
|
|
O => blk00000003_sig000001da
|
4023 |
|
|
);
|
4024 |
|
|
blk00000003_blk000001c5 : LUT3
|
4025 |
|
|
generic map(
|
4026 |
|
|
INIT => X"E4"
|
4027 |
|
|
)
|
4028 |
|
|
port map (
|
4029 |
|
|
I0 => blk00000003_sig00000136,
|
4030 |
|
|
I1 => blk00000003_sig00000132,
|
4031 |
|
|
I2 => blk00000003_sig0000013a,
|
4032 |
|
|
O => blk00000003_sig00000163
|
4033 |
|
|
);
|
4034 |
|
|
blk00000003_blk000001c4 : LUT3
|
4035 |
|
|
generic map(
|
4036 |
|
|
INIT => X"E4"
|
4037 |
|
|
)
|
4038 |
|
|
port map (
|
4039 |
|
|
I0 => blk00000003_sig000002b4,
|
4040 |
|
|
I1 => blk00000003_sig00000365,
|
4041 |
|
|
I2 => blk00000003_sig00000366,
|
4042 |
|
|
O => blk00000003_sig00000349
|
4043 |
|
|
);
|
4044 |
|
|
blk00000003_blk000001c3 : LUT3
|
4045 |
|
|
generic map(
|
4046 |
|
|
INIT => X"20"
|
4047 |
|
|
)
|
4048 |
|
|
port map (
|
4049 |
|
|
I0 => blk00000003_sig00000138,
|
4050 |
|
|
I1 => blk00000003_sig0000013a,
|
4051 |
|
|
I2 => blk00000003_sig0000017e,
|
4052 |
|
|
O => blk00000003_sig00000149
|
4053 |
|
|
);
|
4054 |
|
|
blk00000003_blk000001c2 : LUT3
|
4055 |
|
|
generic map(
|
4056 |
|
|
INIT => X"20"
|
4057 |
|
|
)
|
4058 |
|
|
port map (
|
4059 |
|
|
I0 => blk00000003_sig0000013a,
|
4060 |
|
|
I1 => blk00000003_sig0000013c,
|
4061 |
|
|
I2 => blk00000003_sig00000186,
|
4062 |
|
|
O => blk00000003_sig00000145
|
4063 |
|
|
);
|
4064 |
|
|
blk00000003_blk000001c1 : LUT3
|
4065 |
|
|
generic map(
|
4066 |
|
|
INIT => X"20"
|
4067 |
|
|
)
|
4068 |
|
|
port map (
|
4069 |
|
|
I0 => blk00000003_sig0000013c,
|
4070 |
|
|
I1 => blk00000003_sig0000013e,
|
4071 |
|
|
I2 => blk00000003_sig00000184,
|
4072 |
|
|
O => blk00000003_sig00000141
|
4073 |
|
|
);
|
4074 |
|
|
blk00000003_blk000001c0 : LUT3
|
4075 |
|
|
generic map(
|
4076 |
|
|
INIT => X"10"
|
4077 |
|
|
)
|
4078 |
|
|
port map (
|
4079 |
|
|
I0 => blk00000003_sig00000130,
|
4080 |
|
|
I1 => blk00000003_sig00000174,
|
4081 |
|
|
I2 => blk00000003_sig00000173,
|
4082 |
|
|
O => blk00000003_sig0000015b
|
4083 |
|
|
);
|
4084 |
|
|
blk00000003_blk000001bf : LUT3
|
4085 |
|
|
generic map(
|
4086 |
|
|
INIT => X"20"
|
4087 |
|
|
)
|
4088 |
|
|
port map (
|
4089 |
|
|
I0 => blk00000003_sig00000130,
|
4090 |
|
|
I1 => blk00000003_sig00000132,
|
4091 |
|
|
I2 => blk00000003_sig00000172,
|
4092 |
|
|
O => blk00000003_sig00000159
|
4093 |
|
|
);
|
4094 |
|
|
blk00000003_blk000001be : LUT3
|
4095 |
|
|
generic map(
|
4096 |
|
|
INIT => X"20"
|
4097 |
|
|
)
|
4098 |
|
|
port map (
|
4099 |
|
|
I0 => blk00000003_sig00000132,
|
4100 |
|
|
I1 => blk00000003_sig00000134,
|
4101 |
|
|
I2 => blk00000003_sig0000017a,
|
4102 |
|
|
O => blk00000003_sig00000155
|
4103 |
|
|
);
|
4104 |
|
|
blk00000003_blk000001bd : LUT3
|
4105 |
|
|
generic map(
|
4106 |
|
|
INIT => X"20"
|
4107 |
|
|
)
|
4108 |
|
|
port map (
|
4109 |
|
|
I0 => blk00000003_sig00000134,
|
4110 |
|
|
I1 => blk00000003_sig00000136,
|
4111 |
|
|
I2 => blk00000003_sig00000178,
|
4112 |
|
|
O => blk00000003_sig00000151
|
4113 |
|
|
);
|
4114 |
|
|
blk00000003_blk000001bc : LUT3
|
4115 |
|
|
generic map(
|
4116 |
|
|
INIT => X"20"
|
4117 |
|
|
)
|
4118 |
|
|
port map (
|
4119 |
|
|
I0 => blk00000003_sig00000136,
|
4120 |
|
|
I1 => blk00000003_sig00000138,
|
4121 |
|
|
I2 => blk00000003_sig00000180,
|
4122 |
|
|
O => blk00000003_sig0000014d
|
4123 |
|
|
);
|
4124 |
|
|
blk00000003_blk000001bb : LUT3
|
4125 |
|
|
generic map(
|
4126 |
|
|
INIT => X"A2"
|
4127 |
|
|
)
|
4128 |
|
|
port map (
|
4129 |
|
|
I0 => blk00000003_sig000001ad,
|
4130 |
|
|
I1 => blk00000003_sig000001b4,
|
4131 |
|
|
I2 => blk00000003_sig000001b0,
|
4132 |
|
|
O => blk00000003_sig000001b5
|
4133 |
|
|
);
|
4134 |
|
|
blk00000003_blk000001ba : LUT2
|
4135 |
|
|
generic map(
|
4136 |
|
|
INIT => X"6"
|
4137 |
|
|
)
|
4138 |
|
|
port map (
|
4139 |
|
|
I0 => blk00000003_sig00000366,
|
4140 |
|
|
I1 => blk00000003_sig00000365,
|
4141 |
|
|
O => blk00000003_sig00000343
|
4142 |
|
|
);
|
4143 |
|
|
blk00000003_blk000001b9 : LUT2
|
4144 |
|
|
generic map(
|
4145 |
|
|
INIT => X"9"
|
4146 |
|
|
)
|
4147 |
|
|
port map (
|
4148 |
|
|
I0 => blk00000003_sig000000d5,
|
4149 |
|
|
I1 => blk00000003_sig000000d3,
|
4150 |
|
|
O => blk00000003_sig000000d4
|
4151 |
|
|
);
|
4152 |
|
|
blk00000003_blk000001b8 : LUT2
|
4153 |
|
|
generic map(
|
4154 |
|
|
INIT => X"2"
|
4155 |
|
|
)
|
4156 |
|
|
port map (
|
4157 |
|
|
I0 => blk00000003_sig0000026b,
|
4158 |
|
|
I1 => blk00000003_sig0000026a,
|
4159 |
|
|
O => blk00000003_sig00000271
|
4160 |
|
|
);
|
4161 |
|
|
blk00000003_blk000001b7 : LUT2
|
4162 |
|
|
generic map(
|
4163 |
|
|
INIT => X"8"
|
4164 |
|
|
)
|
4165 |
|
|
port map (
|
4166 |
|
|
I0 => blk00000003_sig00000160,
|
4167 |
|
|
I1 => blk00000003_sig0000013e,
|
4168 |
|
|
O => blk00000003_sig00000328
|
4169 |
|
|
);
|
4170 |
|
|
blk00000003_blk000001b6 : LUT2
|
4171 |
|
|
generic map(
|
4172 |
|
|
INIT => X"2"
|
4173 |
|
|
)
|
4174 |
|
|
port map (
|
4175 |
|
|
I0 => blk00000003_sig00000174,
|
4176 |
|
|
I1 => blk00000003_sig00000130,
|
4177 |
|
|
O => blk00000003_sig0000015d
|
4178 |
|
|
);
|
4179 |
|
|
blk00000003_blk000001b5 : LUT2
|
4180 |
|
|
generic map(
|
4181 |
|
|
INIT => X"8"
|
4182 |
|
|
)
|
4183 |
|
|
port map (
|
4184 |
|
|
I0 => blk00000003_sig00000173,
|
4185 |
|
|
I1 => blk00000003_sig00000174,
|
4186 |
|
|
O => blk00000003_sig000001a9
|
4187 |
|
|
);
|
4188 |
|
|
blk00000003_blk000001b4 : LUT2
|
4189 |
|
|
generic map(
|
4190 |
|
|
INIT => X"8"
|
4191 |
|
|
)
|
4192 |
|
|
port map (
|
4193 |
|
|
I0 => blk00000003_sig000001b2,
|
4194 |
|
|
I1 => blk00000003_sig00000273,
|
4195 |
|
|
O => blk00000003_sig000001b3
|
4196 |
|
|
);
|
4197 |
|
|
blk00000003_blk000001b3 : LUT2
|
4198 |
|
|
generic map(
|
4199 |
|
|
INIT => X"8"
|
4200 |
|
|
)
|
4201 |
|
|
port map (
|
4202 |
|
|
I0 => blk00000003_sig00000365,
|
4203 |
|
|
I1 => blk00000003_sig00000366,
|
4204 |
|
|
O => blk00000003_sig00000347
|
4205 |
|
|
);
|
4206 |
|
|
blk00000003_blk000001b2 : LUT2
|
4207 |
|
|
generic map(
|
4208 |
|
|
INIT => X"2"
|
4209 |
|
|
)
|
4210 |
|
|
port map (
|
4211 |
|
|
I0 => blk00000003_sig00000369,
|
4212 |
|
|
I1 => blk00000003_sig0000036a,
|
4213 |
|
|
O => blk00000003_sig00000325
|
4214 |
|
|
);
|
4215 |
|
|
blk00000003_blk000001b1 : LUT2
|
4216 |
|
|
generic map(
|
4217 |
|
|
INIT => X"2"
|
4218 |
|
|
)
|
4219 |
|
|
port map (
|
4220 |
|
|
I0 => blk00000003_sig00000368,
|
4221 |
|
|
I1 => blk00000003_sig000000d9,
|
4222 |
|
|
O => blk00000003_sig000000d6
|
4223 |
|
|
);
|
4224 |
|
|
blk00000003_blk000001b0 : LUT2
|
4225 |
|
|
generic map(
|
4226 |
|
|
INIT => X"8"
|
4227 |
|
|
)
|
4228 |
|
|
port map (
|
4229 |
|
|
I0 => sig00000041,
|
4230 |
|
|
I1 => blk00000003_sig000000d7,
|
4231 |
|
|
O => blk00000003_sig000000da
|
4232 |
|
|
);
|
4233 |
|
|
blk00000003_blk000001af : LUT4
|
4234 |
|
|
generic map(
|
4235 |
|
|
INIT => X"8AEF"
|
4236 |
|
|
)
|
4237 |
|
|
port map (
|
4238 |
|
|
I0 => sig00000029,
|
4239 |
|
|
I1 => sig0000002a,
|
4240 |
|
|
I2 => sig0000000a,
|
4241 |
|
|
I3 => sig00000009,
|
4242 |
|
|
O => blk00000003_sig00000292
|
4243 |
|
|
);
|
4244 |
|
|
blk00000003_blk000001ae : LUT6
|
4245 |
|
|
generic map(
|
4246 |
|
|
INIT => X"0000000000000001"
|
4247 |
|
|
)
|
4248 |
|
|
port map (
|
4249 |
|
|
I0 => sig00000020,
|
4250 |
|
|
I1 => sig0000001f,
|
4251 |
|
|
I2 => sig0000001e,
|
4252 |
|
|
I3 => sig0000001d,
|
4253 |
|
|
I4 => sig0000001c,
|
4254 |
|
|
I5 => sig0000001b,
|
4255 |
|
|
O => blk00000003_sig000002cd
|
4256 |
|
|
);
|
4257 |
|
|
blk00000003_blk000001ad : LUT6
|
4258 |
|
|
generic map(
|
4259 |
|
|
INIT => X"0000000000000001"
|
4260 |
|
|
)
|
4261 |
|
|
port map (
|
4262 |
|
|
I0 => sig00000040,
|
4263 |
|
|
I1 => sig0000003f,
|
4264 |
|
|
I2 => sig0000003e,
|
4265 |
|
|
I3 => sig0000003d,
|
4266 |
|
|
I4 => sig0000003c,
|
4267 |
|
|
I5 => sig0000003b,
|
4268 |
|
|
O => blk00000003_sig000002d5
|
4269 |
|
|
);
|
4270 |
|
|
blk00000003_blk000001ac : LUT4
|
4271 |
|
|
generic map(
|
4272 |
|
|
INIT => X"9009"
|
4273 |
|
|
)
|
4274 |
|
|
port map (
|
4275 |
|
|
I0 => sig00000028,
|
4276 |
|
|
I1 => sig00000008,
|
4277 |
|
|
I2 => sig00000027,
|
4278 |
|
|
I3 => sig00000007,
|
4279 |
|
|
O => blk00000003_sig00000290
|
4280 |
|
|
);
|
4281 |
|
|
blk00000003_blk000001ab : LUT4
|
4282 |
|
|
generic map(
|
4283 |
|
|
INIT => X"8AEF"
|
4284 |
|
|
)
|
4285 |
|
|
port map (
|
4286 |
|
|
I0 => sig00000027,
|
4287 |
|
|
I1 => sig00000028,
|
4288 |
|
|
I2 => sig00000008,
|
4289 |
|
|
I3 => sig00000007,
|
4290 |
|
|
O => blk00000003_sig0000028f
|
4291 |
|
|
);
|
4292 |
|
|
blk00000003_blk000001aa : LUT6
|
4293 |
|
|
generic map(
|
4294 |
|
|
INIT => X"0000000000000001"
|
4295 |
|
|
)
|
4296 |
|
|
port map (
|
4297 |
|
|
I0 => sig0000001a,
|
4298 |
|
|
I1 => sig00000019,
|
4299 |
|
|
I2 => sig00000018,
|
4300 |
|
|
I3 => sig00000017,
|
4301 |
|
|
I4 => sig00000016,
|
4302 |
|
|
I5 => sig00000015,
|
4303 |
|
|
O => blk00000003_sig000002cf
|
4304 |
|
|
);
|
4305 |
|
|
blk00000003_blk000001a9 : LUT6
|
4306 |
|
|
generic map(
|
4307 |
|
|
INIT => X"0000000000000001"
|
4308 |
|
|
)
|
4309 |
|
|
port map (
|
4310 |
|
|
I0 => sig0000003a,
|
4311 |
|
|
I1 => sig00000039,
|
4312 |
|
|
I2 => sig00000038,
|
4313 |
|
|
I3 => sig00000037,
|
4314 |
|
|
I4 => sig00000036,
|
4315 |
|
|
I5 => sig00000035,
|
4316 |
|
|
O => blk00000003_sig000002d7
|
4317 |
|
|
);
|
4318 |
|
|
blk00000003_blk000001a8 : LUT4
|
4319 |
|
|
generic map(
|
4320 |
|
|
INIT => X"9009"
|
4321 |
|
|
)
|
4322 |
|
|
port map (
|
4323 |
|
|
I0 => sig00000026,
|
4324 |
|
|
I1 => sig00000006,
|
4325 |
|
|
I2 => sig00000025,
|
4326 |
|
|
I3 => sig00000005,
|
4327 |
|
|
O => blk00000003_sig0000028d
|
4328 |
|
|
);
|
4329 |
|
|
blk00000003_blk000001a7 : LUT4
|
4330 |
|
|
generic map(
|
4331 |
|
|
INIT => X"8AEF"
|
4332 |
|
|
)
|
4333 |
|
|
port map (
|
4334 |
|
|
I0 => sig00000025,
|
4335 |
|
|
I1 => sig00000026,
|
4336 |
|
|
I2 => sig00000006,
|
4337 |
|
|
I3 => sig00000005,
|
4338 |
|
|
O => blk00000003_sig0000028c
|
4339 |
|
|
);
|
4340 |
|
|
blk00000003_blk000001a6 : LUT6
|
4341 |
|
|
generic map(
|
4342 |
|
|
INIT => X"0000000000000001"
|
4343 |
|
|
)
|
4344 |
|
|
port map (
|
4345 |
|
|
I0 => sig00000014,
|
4346 |
|
|
I1 => sig00000013,
|
4347 |
|
|
I2 => sig00000012,
|
4348 |
|
|
I3 => sig00000011,
|
4349 |
|
|
I4 => sig00000010,
|
4350 |
|
|
I5 => sig0000000f,
|
4351 |
|
|
O => blk00000003_sig000002d1
|
4352 |
|
|
);
|
4353 |
|
|
blk00000003_blk000001a5 : LUT6
|
4354 |
|
|
generic map(
|
4355 |
|
|
INIT => X"0000000000000001"
|
4356 |
|
|
)
|
4357 |
|
|
port map (
|
4358 |
|
|
I0 => sig00000034,
|
4359 |
|
|
I1 => sig00000033,
|
4360 |
|
|
I2 => sig00000032,
|
4361 |
|
|
I3 => sig00000031,
|
4362 |
|
|
I4 => sig00000030,
|
4363 |
|
|
I5 => sig0000002f,
|
4364 |
|
|
O => blk00000003_sig000002d9
|
4365 |
|
|
);
|
4366 |
|
|
blk00000003_blk000001a4 : LUT4
|
4367 |
|
|
generic map(
|
4368 |
|
|
INIT => X"9009"
|
4369 |
|
|
)
|
4370 |
|
|
port map (
|
4371 |
|
|
I0 => sig00000024,
|
4372 |
|
|
I1 => sig00000004,
|
4373 |
|
|
I2 => sig00000023,
|
4374 |
|
|
I3 => sig00000003,
|
4375 |
|
|
O => blk00000003_sig0000028a
|
4376 |
|
|
);
|
4377 |
|
|
blk00000003_blk000001a3 : LUT4
|
4378 |
|
|
generic map(
|
4379 |
|
|
INIT => X"8AEF"
|
4380 |
|
|
)
|
4381 |
|
|
port map (
|
4382 |
|
|
I0 => sig00000023,
|
4383 |
|
|
I1 => sig00000024,
|
4384 |
|
|
I2 => sig00000004,
|
4385 |
|
|
I3 => sig00000003,
|
4386 |
|
|
O => blk00000003_sig00000289
|
4387 |
|
|
);
|
4388 |
|
|
blk00000003_blk000001a2 : LUT5
|
4389 |
|
|
generic map(
|
4390 |
|
|
INIT => X"00000001"
|
4391 |
|
|
)
|
4392 |
|
|
port map (
|
4393 |
|
|
I0 => sig0000000e,
|
4394 |
|
|
I1 => sig0000000d,
|
4395 |
|
|
I2 => sig0000000c,
|
4396 |
|
|
I3 => sig0000000b,
|
4397 |
|
|
I4 => sig0000000a,
|
4398 |
|
|
O => blk00000003_sig000002d3
|
4399 |
|
|
);
|
4400 |
|
|
blk00000003_blk000001a1 : LUT5
|
4401 |
|
|
generic map(
|
4402 |
|
|
INIT => X"00000001"
|
4403 |
|
|
)
|
4404 |
|
|
port map (
|
4405 |
|
|
I0 => sig0000002e,
|
4406 |
|
|
I1 => sig0000002d,
|
4407 |
|
|
I2 => sig0000002c,
|
4408 |
|
|
I3 => sig0000002b,
|
4409 |
|
|
I4 => sig0000002a,
|
4410 |
|
|
O => blk00000003_sig000002db
|
4411 |
|
|
);
|
4412 |
|
|
blk00000003_blk000001a0 : LUT2
|
4413 |
|
|
generic map(
|
4414 |
|
|
INIT => X"9"
|
4415 |
|
|
)
|
4416 |
|
|
port map (
|
4417 |
|
|
I0 => sig00000022,
|
4418 |
|
|
I1 => sig00000002,
|
4419 |
|
|
O => blk00000003_sig00000286
|
4420 |
|
|
);
|
4421 |
|
|
blk00000003_blk0000019f : LUT2
|
4422 |
|
|
generic map(
|
4423 |
|
|
INIT => X"D"
|
4424 |
|
|
)
|
4425 |
|
|
port map (
|
4426 |
|
|
I0 => sig00000002,
|
4427 |
|
|
I1 => sig00000022,
|
4428 |
|
|
O => blk00000003_sig00000285
|
4429 |
|
|
);
|
4430 |
|
|
blk00000003_blk0000019e : LUT2
|
4431 |
|
|
generic map(
|
4432 |
|
|
INIT => X"6"
|
4433 |
|
|
)
|
4434 |
|
|
port map (
|
4435 |
|
|
I0 => sig00000021,
|
4436 |
|
|
I1 => sig00000001,
|
4437 |
|
|
O => blk00000003_sig00000367
|
4438 |
|
|
);
|
4439 |
|
|
blk00000003_blk0000019d : FDE
|
4440 |
|
|
generic map(
|
4441 |
|
|
INIT => '0'
|
4442 |
|
|
)
|
4443 |
|
|
port map (
|
4444 |
|
|
C => sig00000042,
|
4445 |
|
|
CE => blk00000003_sig00000067,
|
4446 |
|
|
D => blk00000003_sig00000367,
|
4447 |
|
|
Q => blk00000003_sig00000270
|
4448 |
|
|
);
|
4449 |
|
|
blk00000003_blk0000019c : FDE
|
4450 |
|
|
generic map(
|
4451 |
|
|
INIT => '0'
|
4452 |
|
|
)
|
4453 |
|
|
port map (
|
4454 |
|
|
C => sig00000042,
|
4455 |
|
|
CE => blk00000003_sig00000067,
|
4456 |
|
|
D => sig00000021,
|
4457 |
|
|
Q => blk00000003_sig00000366
|
4458 |
|
|
);
|
4459 |
|
|
blk00000003_blk0000019b : FDE
|
4460 |
|
|
generic map(
|
4461 |
|
|
INIT => '0'
|
4462 |
|
|
)
|
4463 |
|
|
port map (
|
4464 |
|
|
C => sig00000042,
|
4465 |
|
|
CE => blk00000003_sig00000067,
|
4466 |
|
|
D => sig00000001,
|
4467 |
|
|
Q => blk00000003_sig00000365
|
4468 |
|
|
);
|
4469 |
|
|
blk00000003_blk0000019a : FDE
|
4470 |
|
|
generic map(
|
4471 |
|
|
INIT => '0'
|
4472 |
|
|
)
|
4473 |
|
|
port map (
|
4474 |
|
|
C => sig00000042,
|
4475 |
|
|
CE => blk00000003_sig00000067,
|
4476 |
|
|
D => sig00000022,
|
4477 |
|
|
Q => blk00000003_sig00000364
|
4478 |
|
|
);
|
4479 |
|
|
blk00000003_blk00000199 : FDE
|
4480 |
|
|
generic map(
|
4481 |
|
|
INIT => '0'
|
4482 |
|
|
)
|
4483 |
|
|
port map (
|
4484 |
|
|
C => sig00000042,
|
4485 |
|
|
CE => blk00000003_sig00000067,
|
4486 |
|
|
D => sig00000023,
|
4487 |
|
|
Q => blk00000003_sig00000363
|
4488 |
|
|
);
|
4489 |
|
|
blk00000003_blk00000198 : FDE
|
4490 |
|
|
generic map(
|
4491 |
|
|
INIT => '0'
|
4492 |
|
|
)
|
4493 |
|
|
port map (
|
4494 |
|
|
C => sig00000042,
|
4495 |
|
|
CE => blk00000003_sig00000067,
|
4496 |
|
|
D => sig00000024,
|
4497 |
|
|
Q => blk00000003_sig00000362
|
4498 |
|
|
);
|
4499 |
|
|
blk00000003_blk00000197 : FDE
|
4500 |
|
|
generic map(
|
4501 |
|
|
INIT => '0'
|
4502 |
|
|
)
|
4503 |
|
|
port map (
|
4504 |
|
|
C => sig00000042,
|
4505 |
|
|
CE => blk00000003_sig00000067,
|
4506 |
|
|
D => sig00000025,
|
4507 |
|
|
Q => blk00000003_sig00000361
|
4508 |
|
|
);
|
4509 |
|
|
blk00000003_blk00000196 : FDE
|
4510 |
|
|
generic map(
|
4511 |
|
|
INIT => '0'
|
4512 |
|
|
)
|
4513 |
|
|
port map (
|
4514 |
|
|
C => sig00000042,
|
4515 |
|
|
CE => blk00000003_sig00000067,
|
4516 |
|
|
D => sig00000026,
|
4517 |
|
|
Q => blk00000003_sig00000360
|
4518 |
|
|
);
|
4519 |
|
|
blk00000003_blk00000195 : FDE
|
4520 |
|
|
generic map(
|
4521 |
|
|
INIT => '0'
|
4522 |
|
|
)
|
4523 |
|
|
port map (
|
4524 |
|
|
C => sig00000042,
|
4525 |
|
|
CE => blk00000003_sig00000067,
|
4526 |
|
|
D => sig00000027,
|
4527 |
|
|
Q => blk00000003_sig0000035f
|
4528 |
|
|
);
|
4529 |
|
|
blk00000003_blk00000194 : FDE
|
4530 |
|
|
generic map(
|
4531 |
|
|
INIT => '0'
|
4532 |
|
|
)
|
4533 |
|
|
port map (
|
4534 |
|
|
C => sig00000042,
|
4535 |
|
|
CE => blk00000003_sig00000067,
|
4536 |
|
|
D => sig00000028,
|
4537 |
|
|
Q => blk00000003_sig0000035e
|
4538 |
|
|
);
|
4539 |
|
|
blk00000003_blk00000193 : FDE
|
4540 |
|
|
generic map(
|
4541 |
|
|
INIT => '0'
|
4542 |
|
|
)
|
4543 |
|
|
port map (
|
4544 |
|
|
C => sig00000042,
|
4545 |
|
|
CE => blk00000003_sig00000067,
|
4546 |
|
|
D => sig00000029,
|
4547 |
|
|
Q => blk00000003_sig0000035d
|
4548 |
|
|
);
|
4549 |
|
|
blk00000003_blk00000192 : FDE
|
4550 |
|
|
generic map(
|
4551 |
|
|
INIT => '0'
|
4552 |
|
|
)
|
4553 |
|
|
port map (
|
4554 |
|
|
C => sig00000042,
|
4555 |
|
|
CE => blk00000003_sig00000067,
|
4556 |
|
|
D => sig00000002,
|
4557 |
|
|
Q => blk00000003_sig0000035c
|
4558 |
|
|
);
|
4559 |
|
|
blk00000003_blk00000191 : FDE
|
4560 |
|
|
generic map(
|
4561 |
|
|
INIT => '0'
|
4562 |
|
|
)
|
4563 |
|
|
port map (
|
4564 |
|
|
C => sig00000042,
|
4565 |
|
|
CE => blk00000003_sig00000067,
|
4566 |
|
|
D => sig00000003,
|
4567 |
|
|
Q => blk00000003_sig0000035b
|
4568 |
|
|
);
|
4569 |
|
|
blk00000003_blk00000190 : FDE
|
4570 |
|
|
generic map(
|
4571 |
|
|
INIT => '0'
|
4572 |
|
|
)
|
4573 |
|
|
port map (
|
4574 |
|
|
C => sig00000042,
|
4575 |
|
|
CE => blk00000003_sig00000067,
|
4576 |
|
|
D => sig00000004,
|
4577 |
|
|
Q => blk00000003_sig0000035a
|
4578 |
|
|
);
|
4579 |
|
|
blk00000003_blk0000018f : FDE
|
4580 |
|
|
generic map(
|
4581 |
|
|
INIT => '0'
|
4582 |
|
|
)
|
4583 |
|
|
port map (
|
4584 |
|
|
C => sig00000042,
|
4585 |
|
|
CE => blk00000003_sig00000067,
|
4586 |
|
|
D => sig00000005,
|
4587 |
|
|
Q => blk00000003_sig00000359
|
4588 |
|
|
);
|
4589 |
|
|
blk00000003_blk0000018e : FDE
|
4590 |
|
|
generic map(
|
4591 |
|
|
INIT => '0'
|
4592 |
|
|
)
|
4593 |
|
|
port map (
|
4594 |
|
|
C => sig00000042,
|
4595 |
|
|
CE => blk00000003_sig00000067,
|
4596 |
|
|
D => sig00000006,
|
4597 |
|
|
Q => blk00000003_sig00000358
|
4598 |
|
|
);
|
4599 |
|
|
blk00000003_blk0000018d : FDE
|
4600 |
|
|
generic map(
|
4601 |
|
|
INIT => '0'
|
4602 |
|
|
)
|
4603 |
|
|
port map (
|
4604 |
|
|
C => sig00000042,
|
4605 |
|
|
CE => blk00000003_sig00000067,
|
4606 |
|
|
D => sig00000007,
|
4607 |
|
|
Q => blk00000003_sig00000357
|
4608 |
|
|
);
|
4609 |
|
|
blk00000003_blk0000018c : FDE
|
4610 |
|
|
generic map(
|
4611 |
|
|
INIT => '0'
|
4612 |
|
|
)
|
4613 |
|
|
port map (
|
4614 |
|
|
C => sig00000042,
|
4615 |
|
|
CE => blk00000003_sig00000067,
|
4616 |
|
|
D => sig00000008,
|
4617 |
|
|
Q => blk00000003_sig00000356
|
4618 |
|
|
);
|
4619 |
|
|
blk00000003_blk0000018b : FDE
|
4620 |
|
|
generic map(
|
4621 |
|
|
INIT => '0'
|
4622 |
|
|
)
|
4623 |
|
|
port map (
|
4624 |
|
|
C => sig00000042,
|
4625 |
|
|
CE => blk00000003_sig00000067,
|
4626 |
|
|
D => sig00000009,
|
4627 |
|
|
Q => blk00000003_sig00000355
|
4628 |
|
|
);
|
4629 |
|
|
blk00000003_blk0000018a : FD
|
4630 |
|
|
generic map(
|
4631 |
|
|
INIT => '0'
|
4632 |
|
|
)
|
4633 |
|
|
port map (
|
4634 |
|
|
C => sig00000042,
|
4635 |
|
|
D => blk00000003_sig00000301,
|
4636 |
|
|
Q => blk00000003_sig00000354
|
4637 |
|
|
);
|
4638 |
|
|
blk00000003_blk00000189 : FD
|
4639 |
|
|
generic map(
|
4640 |
|
|
INIT => '0'
|
4641 |
|
|
)
|
4642 |
|
|
port map (
|
4643 |
|
|
C => sig00000042,
|
4644 |
|
|
D => blk00000003_sig00000304,
|
4645 |
|
|
Q => blk00000003_sig00000353
|
4646 |
|
|
);
|
4647 |
|
|
blk00000003_blk00000188 : FD
|
4648 |
|
|
generic map(
|
4649 |
|
|
INIT => '0'
|
4650 |
|
|
)
|
4651 |
|
|
port map (
|
4652 |
|
|
C => sig00000042,
|
4653 |
|
|
D => blk00000003_sig00000307,
|
4654 |
|
|
Q => blk00000003_sig00000352
|
4655 |
|
|
);
|
4656 |
|
|
blk00000003_blk00000187 : FD
|
4657 |
|
|
generic map(
|
4658 |
|
|
INIT => '0'
|
4659 |
|
|
)
|
4660 |
|
|
port map (
|
4661 |
|
|
C => sig00000042,
|
4662 |
|
|
D => blk00000003_sig0000030a,
|
4663 |
|
|
Q => blk00000003_sig00000351
|
4664 |
|
|
);
|
4665 |
|
|
blk00000003_blk00000186 : FD
|
4666 |
|
|
generic map(
|
4667 |
|
|
INIT => '0'
|
4668 |
|
|
)
|
4669 |
|
|
port map (
|
4670 |
|
|
C => sig00000042,
|
4671 |
|
|
D => blk00000003_sig0000030d,
|
4672 |
|
|
Q => blk00000003_sig00000350
|
4673 |
|
|
);
|
4674 |
|
|
blk00000003_blk00000185 : FD
|
4675 |
|
|
generic map(
|
4676 |
|
|
INIT => '0'
|
4677 |
|
|
)
|
4678 |
|
|
port map (
|
4679 |
|
|
C => sig00000042,
|
4680 |
|
|
D => blk00000003_sig00000310,
|
4681 |
|
|
Q => blk00000003_sig0000034f
|
4682 |
|
|
);
|
4683 |
|
|
blk00000003_blk00000184 : FD
|
4684 |
|
|
generic map(
|
4685 |
|
|
INIT => '0'
|
4686 |
|
|
)
|
4687 |
|
|
port map (
|
4688 |
|
|
C => sig00000042,
|
4689 |
|
|
D => blk00000003_sig00000313,
|
4690 |
|
|
Q => blk00000003_sig0000034e
|
4691 |
|
|
);
|
4692 |
|
|
blk00000003_blk00000183 : FD
|
4693 |
|
|
generic map(
|
4694 |
|
|
INIT => '0'
|
4695 |
|
|
)
|
4696 |
|
|
port map (
|
4697 |
|
|
C => sig00000042,
|
4698 |
|
|
D => blk00000003_sig00000316,
|
4699 |
|
|
Q => blk00000003_sig0000034d
|
4700 |
|
|
);
|
4701 |
|
|
blk00000003_blk00000182 : FD
|
4702 |
|
|
generic map(
|
4703 |
|
|
INIT => '0'
|
4704 |
|
|
)
|
4705 |
|
|
port map (
|
4706 |
|
|
C => sig00000042,
|
4707 |
|
|
D => blk00000003_sig00000318,
|
4708 |
|
|
Q => blk00000003_sig0000034c
|
4709 |
|
|
);
|
4710 |
|
|
blk00000003_blk00000181 : FDE
|
4711 |
|
|
generic map(
|
4712 |
|
|
INIT => '0'
|
4713 |
|
|
)
|
4714 |
|
|
port map (
|
4715 |
|
|
C => sig00000042,
|
4716 |
|
|
CE => blk00000003_sig00000067,
|
4717 |
|
|
D => blk00000003_sig0000034b,
|
4718 |
|
|
Q => blk00000003_sig0000010d
|
4719 |
|
|
);
|
4720 |
|
|
blk00000003_blk00000180 : FDE
|
4721 |
|
|
generic map(
|
4722 |
|
|
INIT => '0'
|
4723 |
|
|
)
|
4724 |
|
|
port map (
|
4725 |
|
|
C => sig00000042,
|
4726 |
|
|
CE => blk00000003_sig00000067,
|
4727 |
|
|
D => blk00000003_sig00000349,
|
4728 |
|
|
Q => blk00000003_sig0000034a
|
4729 |
|
|
);
|
4730 |
|
|
blk00000003_blk0000017f : FDE
|
4731 |
|
|
generic map(
|
4732 |
|
|
INIT => '0'
|
4733 |
|
|
)
|
4734 |
|
|
port map (
|
4735 |
|
|
C => sig00000042,
|
4736 |
|
|
CE => blk00000003_sig00000067,
|
4737 |
|
|
D => blk00000003_sig00000347,
|
4738 |
|
|
Q => blk00000003_sig00000348
|
4739 |
|
|
);
|
4740 |
|
|
blk00000003_blk0000017e : FDE
|
4741 |
|
|
generic map(
|
4742 |
|
|
INIT => '0'
|
4743 |
|
|
)
|
4744 |
|
|
port map (
|
4745 |
|
|
C => sig00000042,
|
4746 |
|
|
CE => blk00000003_sig00000067,
|
4747 |
|
|
D => blk00000003_sig00000345,
|
4748 |
|
|
Q => blk00000003_sig00000346
|
4749 |
|
|
);
|
4750 |
|
|
blk00000003_blk0000017d : FDE
|
4751 |
|
|
generic map(
|
4752 |
|
|
INIT => '0'
|
4753 |
|
|
)
|
4754 |
|
|
port map (
|
4755 |
|
|
C => sig00000042,
|
4756 |
|
|
CE => blk00000003_sig00000067,
|
4757 |
|
|
D => blk00000003_sig00000343,
|
4758 |
|
|
Q => blk00000003_sig00000344
|
4759 |
|
|
);
|
4760 |
|
|
blk00000003_blk0000017c : FDE
|
4761 |
|
|
generic map(
|
4762 |
|
|
INIT => '0'
|
4763 |
|
|
)
|
4764 |
|
|
port map (
|
4765 |
|
|
C => sig00000042,
|
4766 |
|
|
CE => blk00000003_sig00000067,
|
4767 |
|
|
D => blk00000003_sig00000341,
|
4768 |
|
|
Q => blk00000003_sig00000342
|
4769 |
|
|
);
|
4770 |
|
|
blk00000003_blk0000017b : FDE
|
4771 |
|
|
generic map(
|
4772 |
|
|
INIT => '0'
|
4773 |
|
|
)
|
4774 |
|
|
port map (
|
4775 |
|
|
C => sig00000042,
|
4776 |
|
|
CE => blk00000003_sig00000067,
|
4777 |
|
|
D => blk00000003_sig0000033f,
|
4778 |
|
|
Q => blk00000003_sig00000340
|
4779 |
|
|
);
|
4780 |
|
|
blk00000003_blk0000017a : FDE
|
4781 |
|
|
generic map(
|
4782 |
|
|
INIT => '0'
|
4783 |
|
|
)
|
4784 |
|
|
port map (
|
4785 |
|
|
C => sig00000042,
|
4786 |
|
|
CE => blk00000003_sig00000067,
|
4787 |
|
|
D => blk00000003_sig0000033d,
|
4788 |
|
|
Q => blk00000003_sig0000033e
|
4789 |
|
|
);
|
4790 |
|
|
blk00000003_blk00000179 : FDE
|
4791 |
|
|
generic map(
|
4792 |
|
|
INIT => '0'
|
4793 |
|
|
)
|
4794 |
|
|
port map (
|
4795 |
|
|
C => sig00000042,
|
4796 |
|
|
CE => blk00000003_sig00000067,
|
4797 |
|
|
D => blk00000003_sig0000033b,
|
4798 |
|
|
Q => blk00000003_sig0000033c
|
4799 |
|
|
);
|
4800 |
|
|
blk00000003_blk00000178 : FD
|
4801 |
|
|
generic map(
|
4802 |
|
|
INIT => '0'
|
4803 |
|
|
)
|
4804 |
|
|
port map (
|
4805 |
|
|
C => sig00000042,
|
4806 |
|
|
D => blk00000003_sig00000339,
|
4807 |
|
|
Q => blk00000003_sig0000033a
|
4808 |
|
|
);
|
4809 |
|
|
blk00000003_blk00000177 : FD
|
4810 |
|
|
generic map(
|
4811 |
|
|
INIT => '0'
|
4812 |
|
|
)
|
4813 |
|
|
port map (
|
4814 |
|
|
C => sig00000042,
|
4815 |
|
|
D => blk00000003_sig000002cc,
|
4816 |
|
|
Q => blk00000003_sig00000338
|
4817 |
|
|
);
|
4818 |
|
|
blk00000003_blk00000176 : FD
|
4819 |
|
|
generic map(
|
4820 |
|
|
INIT => '0'
|
4821 |
|
|
)
|
4822 |
|
|
port map (
|
4823 |
|
|
C => sig00000042,
|
4824 |
|
|
D => blk00000003_sig000002c9,
|
4825 |
|
|
Q => blk00000003_sig00000337
|
4826 |
|
|
);
|
4827 |
|
|
blk00000003_blk00000175 : FD
|
4828 |
|
|
generic map(
|
4829 |
|
|
INIT => '0'
|
4830 |
|
|
)
|
4831 |
|
|
port map (
|
4832 |
|
|
C => sig00000042,
|
4833 |
|
|
D => blk00000003_sig000002c6,
|
4834 |
|
|
Q => blk00000003_sig00000336
|
4835 |
|
|
);
|
4836 |
|
|
blk00000003_blk00000174 : FD
|
4837 |
|
|
generic map(
|
4838 |
|
|
INIT => '0'
|
4839 |
|
|
)
|
4840 |
|
|
port map (
|
4841 |
|
|
C => sig00000042,
|
4842 |
|
|
D => blk00000003_sig000002c3,
|
4843 |
|
|
Q => blk00000003_sig00000335
|
4844 |
|
|
);
|
4845 |
|
|
blk00000003_blk00000173 : FD
|
4846 |
|
|
generic map(
|
4847 |
|
|
INIT => '0'
|
4848 |
|
|
)
|
4849 |
|
|
port map (
|
4850 |
|
|
C => sig00000042,
|
4851 |
|
|
D => blk00000003_sig000002c0,
|
4852 |
|
|
Q => blk00000003_sig00000334
|
4853 |
|
|
);
|
4854 |
|
|
blk00000003_blk00000172 : FD
|
4855 |
|
|
generic map(
|
4856 |
|
|
INIT => '0'
|
4857 |
|
|
)
|
4858 |
|
|
port map (
|
4859 |
|
|
C => sig00000042,
|
4860 |
|
|
D => blk00000003_sig000002bd,
|
4861 |
|
|
Q => blk00000003_sig00000333
|
4862 |
|
|
);
|
4863 |
|
|
blk00000003_blk00000171 : FD
|
4864 |
|
|
generic map(
|
4865 |
|
|
INIT => '0'
|
4866 |
|
|
)
|
4867 |
|
|
port map (
|
4868 |
|
|
C => sig00000042,
|
4869 |
|
|
D => blk00000003_sig000002ba,
|
4870 |
|
|
Q => blk00000003_sig00000332
|
4871 |
|
|
);
|
4872 |
|
|
blk00000003_blk00000170 : FD
|
4873 |
|
|
generic map(
|
4874 |
|
|
INIT => '0'
|
4875 |
|
|
)
|
4876 |
|
|
port map (
|
4877 |
|
|
C => sig00000042,
|
4878 |
|
|
D => blk00000003_sig000002b7,
|
4879 |
|
|
Q => blk00000003_sig00000331
|
4880 |
|
|
);
|
4881 |
|
|
blk00000003_blk0000016f : FD
|
4882 |
|
|
generic map(
|
4883 |
|
|
INIT => '0'
|
4884 |
|
|
)
|
4885 |
|
|
port map (
|
4886 |
|
|
C => sig00000042,
|
4887 |
|
|
D => blk00000003_sig000002de,
|
4888 |
|
|
Q => blk00000003_sig0000032c
|
4889 |
|
|
);
|
4890 |
|
|
blk00000003_blk0000016e : FD
|
4891 |
|
|
generic map(
|
4892 |
|
|
INIT => '0'
|
4893 |
|
|
)
|
4894 |
|
|
port map (
|
4895 |
|
|
C => sig00000042,
|
4896 |
|
|
D => blk00000003_sig000002e0,
|
4897 |
|
|
Q => blk00000003_sig00000330
|
4898 |
|
|
);
|
4899 |
|
|
blk00000003_blk0000016d : FD
|
4900 |
|
|
generic map(
|
4901 |
|
|
INIT => '0'
|
4902 |
|
|
)
|
4903 |
|
|
port map (
|
4904 |
|
|
C => sig00000042,
|
4905 |
|
|
D => blk00000003_sig000002e3,
|
4906 |
|
|
Q => blk00000003_sig0000019e
|
4907 |
|
|
);
|
4908 |
|
|
blk00000003_blk0000016c : FD
|
4909 |
|
|
generic map(
|
4910 |
|
|
INIT => '0'
|
4911 |
|
|
)
|
4912 |
|
|
port map (
|
4913 |
|
|
C => sig00000042,
|
4914 |
|
|
D => blk00000003_sig000002e7,
|
4915 |
|
|
Q => blk00000003_sig0000019f
|
4916 |
|
|
);
|
4917 |
|
|
blk00000003_blk0000016b : FD
|
4918 |
|
|
generic map(
|
4919 |
|
|
INIT => '0'
|
4920 |
|
|
)
|
4921 |
|
|
port map (
|
4922 |
|
|
C => sig00000042,
|
4923 |
|
|
D => blk00000003_sig000002eb,
|
4924 |
|
|
Q => blk00000003_sig000001a0
|
4925 |
|
|
);
|
4926 |
|
|
blk00000003_blk0000016a : FD
|
4927 |
|
|
generic map(
|
4928 |
|
|
INIT => '0'
|
4929 |
|
|
)
|
4930 |
|
|
port map (
|
4931 |
|
|
C => sig00000042,
|
4932 |
|
|
D => blk00000003_sig000002ef,
|
4933 |
|
|
Q => blk00000003_sig000001a1
|
4934 |
|
|
);
|
4935 |
|
|
blk00000003_blk00000169 : FD
|
4936 |
|
|
generic map(
|
4937 |
|
|
INIT => '0'
|
4938 |
|
|
)
|
4939 |
|
|
port map (
|
4940 |
|
|
C => sig00000042,
|
4941 |
|
|
D => blk00000003_sig000002f3,
|
4942 |
|
|
Q => blk00000003_sig000001a2
|
4943 |
|
|
);
|
4944 |
|
|
blk00000003_blk00000168 : FD
|
4945 |
|
|
generic map(
|
4946 |
|
|
INIT => '0'
|
4947 |
|
|
)
|
4948 |
|
|
port map (
|
4949 |
|
|
C => sig00000042,
|
4950 |
|
|
D => blk00000003_sig000002f7,
|
4951 |
|
|
Q => blk00000003_sig000001a3
|
4952 |
|
|
);
|
4953 |
|
|
blk00000003_blk00000167 : FD
|
4954 |
|
|
generic map(
|
4955 |
|
|
INIT => '0'
|
4956 |
|
|
)
|
4957 |
|
|
port map (
|
4958 |
|
|
C => sig00000042,
|
4959 |
|
|
D => blk00000003_sig000002fb,
|
4960 |
|
|
Q => blk00000003_sig000001a4
|
4961 |
|
|
);
|
4962 |
|
|
blk00000003_blk00000166 : FD
|
4963 |
|
|
generic map(
|
4964 |
|
|
INIT => '0'
|
4965 |
|
|
)
|
4966 |
|
|
port map (
|
4967 |
|
|
C => sig00000042,
|
4968 |
|
|
D => blk00000003_sig000002fe,
|
4969 |
|
|
Q => blk00000003_sig000001a5
|
4970 |
|
|
);
|
4971 |
|
|
blk00000003_blk00000165 : FDE
|
4972 |
|
|
generic map(
|
4973 |
|
|
INIT => '0'
|
4974 |
|
|
)
|
4975 |
|
|
port map (
|
4976 |
|
|
C => sig00000042,
|
4977 |
|
|
CE => blk00000003_sig00000067,
|
4978 |
|
|
D => blk00000003_sig0000032e,
|
4979 |
|
|
Q => blk00000003_sig0000032f
|
4980 |
|
|
);
|
4981 |
|
|
blk00000003_blk00000164 : FDE
|
4982 |
|
|
generic map(
|
4983 |
|
|
INIT => '0'
|
4984 |
|
|
)
|
4985 |
|
|
port map (
|
4986 |
|
|
C => sig00000042,
|
4987 |
|
|
CE => blk00000003_sig00000067,
|
4988 |
|
|
D => blk00000003_sig0000032c,
|
4989 |
|
|
Q => blk00000003_sig0000032d
|
4990 |
|
|
);
|
4991 |
|
|
blk00000003_blk00000163 : FDE
|
4992 |
|
|
generic map(
|
4993 |
|
|
INIT => '0'
|
4994 |
|
|
)
|
4995 |
|
|
port map (
|
4996 |
|
|
C => sig00000042,
|
4997 |
|
|
CE => blk00000003_sig00000067,
|
4998 |
|
|
D => blk00000003_sig0000032a,
|
4999 |
|
|
Q => blk00000003_sig0000032b
|
5000 |
|
|
);
|
5001 |
|
|
blk00000003_blk00000162 : FD
|
5002 |
|
|
generic map(
|
5003 |
|
|
INIT => '0'
|
5004 |
|
|
)
|
5005 |
|
|
port map (
|
5006 |
|
|
C => sig00000042,
|
5007 |
|
|
D => blk00000003_sig00000328,
|
5008 |
|
|
Q => blk00000003_sig00000329
|
5009 |
|
|
);
|
5010 |
|
|
blk00000003_blk00000161 : FD
|
5011 |
|
|
generic map(
|
5012 |
|
|
INIT => '0'
|
5013 |
|
|
)
|
5014 |
|
|
port map (
|
5015 |
|
|
C => sig00000042,
|
5016 |
|
|
D => blk00000003_sig00000327,
|
5017 |
|
|
Q => blk00000003_sig0000010b
|
5018 |
|
|
);
|
5019 |
|
|
blk00000003_blk00000160 : FD
|
5020 |
|
|
generic map(
|
5021 |
|
|
INIT => '0'
|
5022 |
|
|
)
|
5023 |
|
|
port map (
|
5024 |
|
|
C => sig00000042,
|
5025 |
|
|
D => blk00000003_sig00000326,
|
5026 |
|
|
Q => blk00000003_sig0000011b
|
5027 |
|
|
);
|
5028 |
|
|
blk00000003_blk0000015f : FD
|
5029 |
|
|
generic map(
|
5030 |
|
|
INIT => '0'
|
5031 |
|
|
)
|
5032 |
|
|
port map (
|
5033 |
|
|
C => sig00000042,
|
5034 |
|
|
D => blk00000003_sig00000325,
|
5035 |
|
|
Q => blk00000003_sig0000011c
|
5036 |
|
|
);
|
5037 |
|
|
blk00000003_blk0000015e : FD
|
5038 |
|
|
generic map(
|
5039 |
|
|
INIT => '0'
|
5040 |
|
|
)
|
5041 |
|
|
port map (
|
5042 |
|
|
C => sig00000042,
|
5043 |
|
|
D => blk00000003_sig00000324,
|
5044 |
|
|
Q => blk00000003_sig00000126
|
5045 |
|
|
);
|
5046 |
|
|
blk00000003_blk0000015d : FD
|
5047 |
|
|
generic map(
|
5048 |
|
|
INIT => '0'
|
5049 |
|
|
)
|
5050 |
|
|
port map (
|
5051 |
|
|
C => sig00000042,
|
5052 |
|
|
D => blk00000003_sig00000323,
|
5053 |
|
|
Q => blk00000003_sig00000127
|
5054 |
|
|
);
|
5055 |
|
|
blk00000003_blk0000015c : FDE
|
5056 |
|
|
generic map(
|
5057 |
|
|
INIT => '0'
|
5058 |
|
|
)
|
5059 |
|
|
port map (
|
5060 |
|
|
C => sig00000042,
|
5061 |
|
|
CE => blk00000003_sig00000067,
|
5062 |
|
|
D => blk00000003_sig000002dc,
|
5063 |
|
|
Q => blk00000003_sig00000322
|
5064 |
|
|
);
|
5065 |
|
|
blk00000003_blk0000015b : FDE
|
5066 |
|
|
generic map(
|
5067 |
|
|
INIT => '0'
|
5068 |
|
|
)
|
5069 |
|
|
port map (
|
5070 |
|
|
C => sig00000042,
|
5071 |
|
|
CE => blk00000003_sig00000067,
|
5072 |
|
|
D => blk00000003_sig00000320,
|
5073 |
|
|
Q => blk00000003_sig00000321
|
5074 |
|
|
);
|
5075 |
|
|
blk00000003_blk0000015a : FDE
|
5076 |
|
|
generic map(
|
5077 |
|
|
INIT => '0'
|
5078 |
|
|
)
|
5079 |
|
|
port map (
|
5080 |
|
|
C => sig00000042,
|
5081 |
|
|
CE => blk00000003_sig00000067,
|
5082 |
|
|
D => blk00000003_sig0000031e,
|
5083 |
|
|
Q => blk00000003_sig0000031f
|
5084 |
|
|
);
|
5085 |
|
|
blk00000003_blk00000159 : FDE
|
5086 |
|
|
generic map(
|
5087 |
|
|
INIT => '0'
|
5088 |
|
|
)
|
5089 |
|
|
port map (
|
5090 |
|
|
C => sig00000042,
|
5091 |
|
|
CE => blk00000003_sig00000067,
|
5092 |
|
|
D => blk00000003_sig000002d4,
|
5093 |
|
|
Q => blk00000003_sig0000031d
|
5094 |
|
|
);
|
5095 |
|
|
blk00000003_blk00000158 : FDE
|
5096 |
|
|
generic map(
|
5097 |
|
|
INIT => '0'
|
5098 |
|
|
)
|
5099 |
|
|
port map (
|
5100 |
|
|
C => sig00000042,
|
5101 |
|
|
CE => blk00000003_sig00000067,
|
5102 |
|
|
D => blk00000003_sig0000031b,
|
5103 |
|
|
Q => blk00000003_sig0000031c
|
5104 |
|
|
);
|
5105 |
|
|
blk00000003_blk00000157 : FDE
|
5106 |
|
|
generic map(
|
5107 |
|
|
INIT => '0'
|
5108 |
|
|
)
|
5109 |
|
|
port map (
|
5110 |
|
|
C => sig00000042,
|
5111 |
|
|
CE => blk00000003_sig00000067,
|
5112 |
|
|
D => blk00000003_sig00000319,
|
5113 |
|
|
Q => blk00000003_sig0000031a
|
5114 |
|
|
);
|
5115 |
|
|
blk00000003_blk00000156 : LUT2
|
5116 |
|
|
generic map(
|
5117 |
|
|
INIT => X"9"
|
5118 |
|
|
)
|
5119 |
|
|
port map (
|
5120 |
|
|
I0 => sig00000029,
|
5121 |
|
|
I1 => sig00000009,
|
5122 |
|
|
O => blk00000003_sig00000317
|
5123 |
|
|
);
|
5124 |
|
|
blk00000003_blk00000155 : MUXCY
|
5125 |
|
|
port map (
|
5126 |
|
|
CI => blk00000003_sig00000067,
|
5127 |
|
|
DI => sig00000029,
|
5128 |
|
|
S => blk00000003_sig00000317,
|
5129 |
|
|
O => blk00000003_sig00000314
|
5130 |
|
|
);
|
5131 |
|
|
blk00000003_blk00000154 : XORCY
|
5132 |
|
|
port map (
|
5133 |
|
|
CI => blk00000003_sig00000067,
|
5134 |
|
|
LI => blk00000003_sig00000317,
|
5135 |
|
|
O => blk00000003_sig00000318
|
5136 |
|
|
);
|
5137 |
|
|
blk00000003_blk00000153 : LUT2
|
5138 |
|
|
generic map(
|
5139 |
|
|
INIT => X"9"
|
5140 |
|
|
)
|
5141 |
|
|
port map (
|
5142 |
|
|
I0 => sig00000028,
|
5143 |
|
|
I1 => sig00000008,
|
5144 |
|
|
O => blk00000003_sig00000315
|
5145 |
|
|
);
|
5146 |
|
|
blk00000003_blk00000152 : MUXCY
|
5147 |
|
|
port map (
|
5148 |
|
|
CI => blk00000003_sig00000314,
|
5149 |
|
|
DI => sig00000028,
|
5150 |
|
|
S => blk00000003_sig00000315,
|
5151 |
|
|
O => blk00000003_sig00000311
|
5152 |
|
|
);
|
5153 |
|
|
blk00000003_blk00000151 : XORCY
|
5154 |
|
|
port map (
|
5155 |
|
|
CI => blk00000003_sig00000314,
|
5156 |
|
|
LI => blk00000003_sig00000315,
|
5157 |
|
|
O => blk00000003_sig00000316
|
5158 |
|
|
);
|
5159 |
|
|
blk00000003_blk00000150 : LUT2
|
5160 |
|
|
generic map(
|
5161 |
|
|
INIT => X"9"
|
5162 |
|
|
)
|
5163 |
|
|
port map (
|
5164 |
|
|
I0 => sig00000027,
|
5165 |
|
|
I1 => sig00000007,
|
5166 |
|
|
O => blk00000003_sig00000312
|
5167 |
|
|
);
|
5168 |
|
|
blk00000003_blk0000014f : MUXCY
|
5169 |
|
|
port map (
|
5170 |
|
|
CI => blk00000003_sig00000311,
|
5171 |
|
|
DI => sig00000027,
|
5172 |
|
|
S => blk00000003_sig00000312,
|
5173 |
|
|
O => blk00000003_sig0000030e
|
5174 |
|
|
);
|
5175 |
|
|
blk00000003_blk0000014e : XORCY
|
5176 |
|
|
port map (
|
5177 |
|
|
CI => blk00000003_sig00000311,
|
5178 |
|
|
LI => blk00000003_sig00000312,
|
5179 |
|
|
O => blk00000003_sig00000313
|
5180 |
|
|
);
|
5181 |
|
|
blk00000003_blk0000014d : LUT2
|
5182 |
|
|
generic map(
|
5183 |
|
|
INIT => X"9"
|
5184 |
|
|
)
|
5185 |
|
|
port map (
|
5186 |
|
|
I0 => sig00000026,
|
5187 |
|
|
I1 => sig00000006,
|
5188 |
|
|
O => blk00000003_sig0000030f
|
5189 |
|
|
);
|
5190 |
|
|
blk00000003_blk0000014c : MUXCY
|
5191 |
|
|
port map (
|
5192 |
|
|
CI => blk00000003_sig0000030e,
|
5193 |
|
|
DI => sig00000026,
|
5194 |
|
|
S => blk00000003_sig0000030f,
|
5195 |
|
|
O => blk00000003_sig0000030b
|
5196 |
|
|
);
|
5197 |
|
|
blk00000003_blk0000014b : XORCY
|
5198 |
|
|
port map (
|
5199 |
|
|
CI => blk00000003_sig0000030e,
|
5200 |
|
|
LI => blk00000003_sig0000030f,
|
5201 |
|
|
O => blk00000003_sig00000310
|
5202 |
|
|
);
|
5203 |
|
|
blk00000003_blk0000014a : LUT2
|
5204 |
|
|
generic map(
|
5205 |
|
|
INIT => X"9"
|
5206 |
|
|
)
|
5207 |
|
|
port map (
|
5208 |
|
|
I0 => sig00000025,
|
5209 |
|
|
I1 => sig00000005,
|
5210 |
|
|
O => blk00000003_sig0000030c
|
5211 |
|
|
);
|
5212 |
|
|
blk00000003_blk00000149 : MUXCY
|
5213 |
|
|
port map (
|
5214 |
|
|
CI => blk00000003_sig0000030b,
|
5215 |
|
|
DI => sig00000025,
|
5216 |
|
|
S => blk00000003_sig0000030c,
|
5217 |
|
|
O => blk00000003_sig00000308
|
5218 |
|
|
);
|
5219 |
|
|
blk00000003_blk00000148 : XORCY
|
5220 |
|
|
port map (
|
5221 |
|
|
CI => blk00000003_sig0000030b,
|
5222 |
|
|
LI => blk00000003_sig0000030c,
|
5223 |
|
|
O => blk00000003_sig0000030d
|
5224 |
|
|
);
|
5225 |
|
|
blk00000003_blk00000147 : LUT2
|
5226 |
|
|
generic map(
|
5227 |
|
|
INIT => X"9"
|
5228 |
|
|
)
|
5229 |
|
|
port map (
|
5230 |
|
|
I0 => sig00000024,
|
5231 |
|
|
I1 => sig00000004,
|
5232 |
|
|
O => blk00000003_sig00000309
|
5233 |
|
|
);
|
5234 |
|
|
blk00000003_blk00000146 : MUXCY
|
5235 |
|
|
port map (
|
5236 |
|
|
CI => blk00000003_sig00000308,
|
5237 |
|
|
DI => sig00000024,
|
5238 |
|
|
S => blk00000003_sig00000309,
|
5239 |
|
|
O => blk00000003_sig00000305
|
5240 |
|
|
);
|
5241 |
|
|
blk00000003_blk00000145 : XORCY
|
5242 |
|
|
port map (
|
5243 |
|
|
CI => blk00000003_sig00000308,
|
5244 |
|
|
LI => blk00000003_sig00000309,
|
5245 |
|
|
O => blk00000003_sig0000030a
|
5246 |
|
|
);
|
5247 |
|
|
blk00000003_blk00000144 : LUT2
|
5248 |
|
|
generic map(
|
5249 |
|
|
INIT => X"9"
|
5250 |
|
|
)
|
5251 |
|
|
port map (
|
5252 |
|
|
I0 => sig00000023,
|
5253 |
|
|
I1 => sig00000003,
|
5254 |
|
|
O => blk00000003_sig00000306
|
5255 |
|
|
);
|
5256 |
|
|
blk00000003_blk00000143 : MUXCY
|
5257 |
|
|
port map (
|
5258 |
|
|
CI => blk00000003_sig00000305,
|
5259 |
|
|
DI => sig00000023,
|
5260 |
|
|
S => blk00000003_sig00000306,
|
5261 |
|
|
O => blk00000003_sig00000302
|
5262 |
|
|
);
|
5263 |
|
|
blk00000003_blk00000142 : XORCY
|
5264 |
|
|
port map (
|
5265 |
|
|
CI => blk00000003_sig00000305,
|
5266 |
|
|
LI => blk00000003_sig00000306,
|
5267 |
|
|
O => blk00000003_sig00000307
|
5268 |
|
|
);
|
5269 |
|
|
blk00000003_blk00000141 : LUT2
|
5270 |
|
|
generic map(
|
5271 |
|
|
INIT => X"9"
|
5272 |
|
|
)
|
5273 |
|
|
port map (
|
5274 |
|
|
I0 => sig00000022,
|
5275 |
|
|
I1 => sig00000002,
|
5276 |
|
|
O => blk00000003_sig00000303
|
5277 |
|
|
);
|
5278 |
|
|
blk00000003_blk00000140 : MUXCY
|
5279 |
|
|
port map (
|
5280 |
|
|
CI => blk00000003_sig00000302,
|
5281 |
|
|
DI => sig00000022,
|
5282 |
|
|
S => blk00000003_sig00000303,
|
5283 |
|
|
O => blk00000003_sig00000300
|
5284 |
|
|
);
|
5285 |
|
|
blk00000003_blk0000013f : XORCY
|
5286 |
|
|
port map (
|
5287 |
|
|
CI => blk00000003_sig00000302,
|
5288 |
|
|
LI => blk00000003_sig00000303,
|
5289 |
|
|
O => blk00000003_sig00000304
|
5290 |
|
|
);
|
5291 |
|
|
blk00000003_blk0000013e : XORCY
|
5292 |
|
|
port map (
|
5293 |
|
|
CI => blk00000003_sig00000300,
|
5294 |
|
|
LI => blk00000003_sig00000067,
|
5295 |
|
|
O => blk00000003_sig00000301
|
5296 |
|
|
);
|
5297 |
|
|
blk00000003_blk0000013d : LUT2
|
5298 |
|
|
generic map(
|
5299 |
|
|
INIT => X"9"
|
5300 |
|
|
)
|
5301 |
|
|
port map (
|
5302 |
|
|
I0 => blk00000003_sig000002ff,
|
5303 |
|
|
I1 => blk00000003_sig00000168,
|
5304 |
|
|
O => blk00000003_sig000002fd
|
5305 |
|
|
);
|
5306 |
|
|
blk00000003_blk0000013c : MUXCY
|
5307 |
|
|
port map (
|
5308 |
|
|
CI => blk00000003_sig00000067,
|
5309 |
|
|
DI => blk00000003_sig000002ff,
|
5310 |
|
|
S => blk00000003_sig000002fd,
|
5311 |
|
|
O => blk00000003_sig000002f9
|
5312 |
|
|
);
|
5313 |
|
|
blk00000003_blk0000013b : XORCY
|
5314 |
|
|
port map (
|
5315 |
|
|
CI => blk00000003_sig00000067,
|
5316 |
|
|
LI => blk00000003_sig000002fd,
|
5317 |
|
|
O => blk00000003_sig000002fe
|
5318 |
|
|
);
|
5319 |
|
|
blk00000003_blk0000013a : LUT2
|
5320 |
|
|
generic map(
|
5321 |
|
|
INIT => X"9"
|
5322 |
|
|
)
|
5323 |
|
|
port map (
|
5324 |
|
|
I0 => blk00000003_sig000002fc,
|
5325 |
|
|
I1 => blk00000003_sig00000166,
|
5326 |
|
|
O => blk00000003_sig000002fa
|
5327 |
|
|
);
|
5328 |
|
|
blk00000003_blk00000139 : MUXCY
|
5329 |
|
|
port map (
|
5330 |
|
|
CI => blk00000003_sig000002f9,
|
5331 |
|
|
DI => blk00000003_sig000002fc,
|
5332 |
|
|
S => blk00000003_sig000002fa,
|
5333 |
|
|
O => blk00000003_sig000002f5
|
5334 |
|
|
);
|
5335 |
|
|
blk00000003_blk00000138 : XORCY
|
5336 |
|
|
port map (
|
5337 |
|
|
CI => blk00000003_sig000002f9,
|
5338 |
|
|
LI => blk00000003_sig000002fa,
|
5339 |
|
|
O => blk00000003_sig000002fb
|
5340 |
|
|
);
|
5341 |
|
|
blk00000003_blk00000137 : LUT2
|
5342 |
|
|
generic map(
|
5343 |
|
|
INIT => X"9"
|
5344 |
|
|
)
|
5345 |
|
|
port map (
|
5346 |
|
|
I0 => blk00000003_sig000002f8,
|
5347 |
|
|
I1 => blk00000003_sig00000164,
|
5348 |
|
|
O => blk00000003_sig000002f6
|
5349 |
|
|
);
|
5350 |
|
|
blk00000003_blk00000136 : MUXCY
|
5351 |
|
|
port map (
|
5352 |
|
|
CI => blk00000003_sig000002f5,
|
5353 |
|
|
DI => blk00000003_sig000002f8,
|
5354 |
|
|
S => blk00000003_sig000002f6,
|
5355 |
|
|
O => blk00000003_sig000002f1
|
5356 |
|
|
);
|
5357 |
|
|
blk00000003_blk00000135 : XORCY
|
5358 |
|
|
port map (
|
5359 |
|
|
CI => blk00000003_sig000002f5,
|
5360 |
|
|
LI => blk00000003_sig000002f6,
|
5361 |
|
|
O => blk00000003_sig000002f7
|
5362 |
|
|
);
|
5363 |
|
|
blk00000003_blk00000134 : LUT2
|
5364 |
|
|
generic map(
|
5365 |
|
|
INIT => X"9"
|
5366 |
|
|
)
|
5367 |
|
|
port map (
|
5368 |
|
|
I0 => blk00000003_sig000002f4,
|
5369 |
|
|
I1 => blk00000003_sig00000162,
|
5370 |
|
|
O => blk00000003_sig000002f2
|
5371 |
|
|
);
|
5372 |
|
|
blk00000003_blk00000133 : MUXCY
|
5373 |
|
|
port map (
|
5374 |
|
|
CI => blk00000003_sig000002f1,
|
5375 |
|
|
DI => blk00000003_sig000002f4,
|
5376 |
|
|
S => blk00000003_sig000002f2,
|
5377 |
|
|
O => blk00000003_sig000002ed
|
5378 |
|
|
);
|
5379 |
|
|
blk00000003_blk00000132 : XORCY
|
5380 |
|
|
port map (
|
5381 |
|
|
CI => blk00000003_sig000002f1,
|
5382 |
|
|
LI => blk00000003_sig000002f2,
|
5383 |
|
|
O => blk00000003_sig000002f3
|
5384 |
|
|
);
|
5385 |
|
|
blk00000003_blk00000131 : LUT2
|
5386 |
|
|
generic map(
|
5387 |
|
|
INIT => X"9"
|
5388 |
|
|
)
|
5389 |
|
|
port map (
|
5390 |
|
|
I0 => blk00000003_sig000002f0,
|
5391 |
|
|
I1 => blk00000003_sig00000161,
|
5392 |
|
|
O => blk00000003_sig000002ee
|
5393 |
|
|
);
|
5394 |
|
|
blk00000003_blk00000130 : MUXCY
|
5395 |
|
|
port map (
|
5396 |
|
|
CI => blk00000003_sig000002ed,
|
5397 |
|
|
DI => blk00000003_sig000002f0,
|
5398 |
|
|
S => blk00000003_sig000002ee,
|
5399 |
|
|
O => blk00000003_sig000002e9
|
5400 |
|
|
);
|
5401 |
|
|
blk00000003_blk0000012f : XORCY
|
5402 |
|
|
port map (
|
5403 |
|
|
CI => blk00000003_sig000002ed,
|
5404 |
|
|
LI => blk00000003_sig000002ee,
|
5405 |
|
|
O => blk00000003_sig000002ef
|
5406 |
|
|
);
|
5407 |
|
|
blk00000003_blk0000012e : MUXCY
|
5408 |
|
|
port map (
|
5409 |
|
|
CI => blk00000003_sig000002e9,
|
5410 |
|
|
DI => blk00000003_sig000002ec,
|
5411 |
|
|
S => blk00000003_sig000002ea,
|
5412 |
|
|
O => blk00000003_sig000002e5
|
5413 |
|
|
);
|
5414 |
|
|
blk00000003_blk0000012d : XORCY
|
5415 |
|
|
port map (
|
5416 |
|
|
CI => blk00000003_sig000002e9,
|
5417 |
|
|
LI => blk00000003_sig000002ea,
|
5418 |
|
|
O => blk00000003_sig000002eb
|
5419 |
|
|
);
|
5420 |
|
|
blk00000003_blk0000012c : MUXCY
|
5421 |
|
|
port map (
|
5422 |
|
|
CI => blk00000003_sig000002e5,
|
5423 |
|
|
DI => blk00000003_sig000002e8,
|
5424 |
|
|
S => blk00000003_sig000002e6,
|
5425 |
|
|
O => blk00000003_sig000002e1
|
5426 |
|
|
);
|
5427 |
|
|
blk00000003_blk0000012b : XORCY
|
5428 |
|
|
port map (
|
5429 |
|
|
CI => blk00000003_sig000002e5,
|
5430 |
|
|
LI => blk00000003_sig000002e6,
|
5431 |
|
|
O => blk00000003_sig000002e7
|
5432 |
|
|
);
|
5433 |
|
|
blk00000003_blk0000012a : MUXCY
|
5434 |
|
|
port map (
|
5435 |
|
|
CI => blk00000003_sig000002e1,
|
5436 |
|
|
DI => blk00000003_sig000002e4,
|
5437 |
|
|
S => blk00000003_sig000002e2,
|
5438 |
|
|
O => blk00000003_sig000002df
|
5439 |
|
|
);
|
5440 |
|
|
blk00000003_blk00000129 : XORCY
|
5441 |
|
|
port map (
|
5442 |
|
|
CI => blk00000003_sig000002e1,
|
5443 |
|
|
LI => blk00000003_sig000002e2,
|
5444 |
|
|
O => blk00000003_sig000002e3
|
5445 |
|
|
);
|
5446 |
|
|
blk00000003_blk00000128 : MUXCY
|
5447 |
|
|
port map (
|
5448 |
|
|
CI => blk00000003_sig000002df,
|
5449 |
|
|
DI => blk00000003_sig00000066,
|
5450 |
|
|
S => blk00000003_sig00000067,
|
5451 |
|
|
O => blk00000003_sig000002dd
|
5452 |
|
|
);
|
5453 |
|
|
blk00000003_blk00000127 : XORCY
|
5454 |
|
|
port map (
|
5455 |
|
|
CI => blk00000003_sig000002df,
|
5456 |
|
|
LI => blk00000003_sig00000067,
|
5457 |
|
|
O => blk00000003_sig000002e0
|
5458 |
|
|
);
|
5459 |
|
|
blk00000003_blk00000126 : XORCY
|
5460 |
|
|
port map (
|
5461 |
|
|
CI => blk00000003_sig000002dd,
|
5462 |
|
|
LI => blk00000003_sig00000067,
|
5463 |
|
|
O => blk00000003_sig000002de
|
5464 |
|
|
);
|
5465 |
|
|
blk00000003_blk00000125 : MUXCY
|
5466 |
|
|
port map (
|
5467 |
|
|
CI => blk00000003_sig000002da,
|
5468 |
|
|
DI => blk00000003_sig00000066,
|
5469 |
|
|
S => blk00000003_sig000002db,
|
5470 |
|
|
O => blk00000003_sig000002dc
|
5471 |
|
|
);
|
5472 |
|
|
blk00000003_blk00000124 : MUXCY
|
5473 |
|
|
port map (
|
5474 |
|
|
CI => blk00000003_sig000002d8,
|
5475 |
|
|
DI => blk00000003_sig00000066,
|
5476 |
|
|
S => blk00000003_sig000002d9,
|
5477 |
|
|
O => blk00000003_sig000002da
|
5478 |
|
|
);
|
5479 |
|
|
blk00000003_blk00000123 : MUXCY
|
5480 |
|
|
port map (
|
5481 |
|
|
CI => blk00000003_sig000002d6,
|
5482 |
|
|
DI => blk00000003_sig00000066,
|
5483 |
|
|
S => blk00000003_sig000002d7,
|
5484 |
|
|
O => blk00000003_sig000002d8
|
5485 |
|
|
);
|
5486 |
|
|
blk00000003_blk00000122 : MUXCY
|
5487 |
|
|
port map (
|
5488 |
|
|
CI => blk00000003_sig00000067,
|
5489 |
|
|
DI => blk00000003_sig00000066,
|
5490 |
|
|
S => blk00000003_sig000002d5,
|
5491 |
|
|
O => blk00000003_sig000002d6
|
5492 |
|
|
);
|
5493 |
|
|
blk00000003_blk00000121 : MUXCY
|
5494 |
|
|
port map (
|
5495 |
|
|
CI => blk00000003_sig000002d2,
|
5496 |
|
|
DI => blk00000003_sig00000066,
|
5497 |
|
|
S => blk00000003_sig000002d3,
|
5498 |
|
|
O => blk00000003_sig000002d4
|
5499 |
|
|
);
|
5500 |
|
|
blk00000003_blk00000120 : MUXCY
|
5501 |
|
|
port map (
|
5502 |
|
|
CI => blk00000003_sig000002d0,
|
5503 |
|
|
DI => blk00000003_sig00000066,
|
5504 |
|
|
S => blk00000003_sig000002d1,
|
5505 |
|
|
O => blk00000003_sig000002d2
|
5506 |
|
|
);
|
5507 |
|
|
blk00000003_blk0000011f : MUXCY
|
5508 |
|
|
port map (
|
5509 |
|
|
CI => blk00000003_sig000002ce,
|
5510 |
|
|
DI => blk00000003_sig00000066,
|
5511 |
|
|
S => blk00000003_sig000002cf,
|
5512 |
|
|
O => blk00000003_sig000002d0
|
5513 |
|
|
);
|
5514 |
|
|
blk00000003_blk0000011e : MUXCY
|
5515 |
|
|
port map (
|
5516 |
|
|
CI => blk00000003_sig00000067,
|
5517 |
|
|
DI => blk00000003_sig00000066,
|
5518 |
|
|
S => blk00000003_sig000002cd,
|
5519 |
|
|
O => blk00000003_sig000002ce
|
5520 |
|
|
);
|
5521 |
|
|
blk00000003_blk0000011d : XORCY
|
5522 |
|
|
port map (
|
5523 |
|
|
CI => blk00000003_sig000002cb,
|
5524 |
|
|
LI => blk00000003_sig00000066,
|
5525 |
|
|
O => NLW_blk00000003_blk0000011d_O_UNCONNECTED
|
5526 |
|
|
);
|
5527 |
|
|
blk00000003_blk0000011c : XORCY
|
5528 |
|
|
port map (
|
5529 |
|
|
CI => blk00000003_sig000002c8,
|
5530 |
|
|
LI => blk00000003_sig000002ca,
|
5531 |
|
|
O => blk00000003_sig000002cc
|
5532 |
|
|
);
|
5533 |
|
|
blk00000003_blk0000011b : MUXCY
|
5534 |
|
|
port map (
|
5535 |
|
|
CI => blk00000003_sig000002c8,
|
5536 |
|
|
DI => blk00000003_sig00000066,
|
5537 |
|
|
S => blk00000003_sig000002ca,
|
5538 |
|
|
O => blk00000003_sig000002cb
|
5539 |
|
|
);
|
5540 |
|
|
blk00000003_blk0000011a : XORCY
|
5541 |
|
|
port map (
|
5542 |
|
|
CI => blk00000003_sig000002c5,
|
5543 |
|
|
LI => blk00000003_sig000002c7,
|
5544 |
|
|
O => blk00000003_sig000002c9
|
5545 |
|
|
);
|
5546 |
|
|
blk00000003_blk00000119 : MUXCY
|
5547 |
|
|
port map (
|
5548 |
|
|
CI => blk00000003_sig000002c5,
|
5549 |
|
|
DI => blk00000003_sig00000066,
|
5550 |
|
|
S => blk00000003_sig000002c7,
|
5551 |
|
|
O => blk00000003_sig000002c8
|
5552 |
|
|
);
|
5553 |
|
|
blk00000003_blk00000118 : XORCY
|
5554 |
|
|
port map (
|
5555 |
|
|
CI => blk00000003_sig000002c2,
|
5556 |
|
|
LI => blk00000003_sig000002c4,
|
5557 |
|
|
O => blk00000003_sig000002c6
|
5558 |
|
|
);
|
5559 |
|
|
blk00000003_blk00000117 : MUXCY
|
5560 |
|
|
port map (
|
5561 |
|
|
CI => blk00000003_sig000002c2,
|
5562 |
|
|
DI => blk00000003_sig00000066,
|
5563 |
|
|
S => blk00000003_sig000002c4,
|
5564 |
|
|
O => blk00000003_sig000002c5
|
5565 |
|
|
);
|
5566 |
|
|
blk00000003_blk00000116 : XORCY
|
5567 |
|
|
port map (
|
5568 |
|
|
CI => blk00000003_sig000002bf,
|
5569 |
|
|
LI => blk00000003_sig000002c1,
|
5570 |
|
|
O => blk00000003_sig000002c3
|
5571 |
|
|
);
|
5572 |
|
|
blk00000003_blk00000115 : MUXCY
|
5573 |
|
|
port map (
|
5574 |
|
|
CI => blk00000003_sig000002bf,
|
5575 |
|
|
DI => blk00000003_sig00000066,
|
5576 |
|
|
S => blk00000003_sig000002c1,
|
5577 |
|
|
O => blk00000003_sig000002c2
|
5578 |
|
|
);
|
5579 |
|
|
blk00000003_blk00000114 : XORCY
|
5580 |
|
|
port map (
|
5581 |
|
|
CI => blk00000003_sig000002bc,
|
5582 |
|
|
LI => blk00000003_sig000002be,
|
5583 |
|
|
O => blk00000003_sig000002c0
|
5584 |
|
|
);
|
5585 |
|
|
blk00000003_blk00000113 : MUXCY
|
5586 |
|
|
port map (
|
5587 |
|
|
CI => blk00000003_sig000002bc,
|
5588 |
|
|
DI => blk00000003_sig00000066,
|
5589 |
|
|
S => blk00000003_sig000002be,
|
5590 |
|
|
O => blk00000003_sig000002bf
|
5591 |
|
|
);
|
5592 |
|
|
blk00000003_blk00000112 : XORCY
|
5593 |
|
|
port map (
|
5594 |
|
|
CI => blk00000003_sig000002b9,
|
5595 |
|
|
LI => blk00000003_sig000002bb,
|
5596 |
|
|
O => blk00000003_sig000002bd
|
5597 |
|
|
);
|
5598 |
|
|
blk00000003_blk00000111 : MUXCY
|
5599 |
|
|
port map (
|
5600 |
|
|
CI => blk00000003_sig000002b9,
|
5601 |
|
|
DI => blk00000003_sig00000066,
|
5602 |
|
|
S => blk00000003_sig000002bb,
|
5603 |
|
|
O => blk00000003_sig000002bc
|
5604 |
|
|
);
|
5605 |
|
|
blk00000003_blk00000110 : XORCY
|
5606 |
|
|
port map (
|
5607 |
|
|
CI => blk00000003_sig000002b6,
|
5608 |
|
|
LI => blk00000003_sig000002b8,
|
5609 |
|
|
O => blk00000003_sig000002ba
|
5610 |
|
|
);
|
5611 |
|
|
blk00000003_blk0000010f : MUXCY
|
5612 |
|
|
port map (
|
5613 |
|
|
CI => blk00000003_sig000002b6,
|
5614 |
|
|
DI => blk00000003_sig00000066,
|
5615 |
|
|
S => blk00000003_sig000002b8,
|
5616 |
|
|
O => blk00000003_sig000002b9
|
5617 |
|
|
);
|
5618 |
|
|
blk00000003_blk0000010e : XORCY
|
5619 |
|
|
port map (
|
5620 |
|
|
CI => blk00000003_sig00000066,
|
5621 |
|
|
LI => blk00000003_sig000002b5,
|
5622 |
|
|
O => blk00000003_sig000002b7
|
5623 |
|
|
);
|
5624 |
|
|
blk00000003_blk0000010d : MUXCY
|
5625 |
|
|
port map (
|
5626 |
|
|
CI => blk00000003_sig00000066,
|
5627 |
|
|
DI => blk00000003_sig00000067,
|
5628 |
|
|
S => blk00000003_sig000002b5,
|
5629 |
|
|
O => blk00000003_sig000002b6
|
5630 |
|
|
);
|
5631 |
|
|
blk00000003_blk0000010c : FDE
|
5632 |
|
|
generic map(
|
5633 |
|
|
INIT => '0'
|
5634 |
|
|
)
|
5635 |
|
|
port map (
|
5636 |
|
|
C => sig00000042,
|
5637 |
|
|
CE => blk00000003_sig00000067,
|
5638 |
|
|
D => blk00000003_sig00000287,
|
5639 |
|
|
Q => blk00000003_sig000002b4
|
5640 |
|
|
);
|
5641 |
|
|
blk00000003_blk0000010b : MUXCY
|
5642 |
|
|
port map (
|
5643 |
|
|
CI => blk00000003_sig00000066,
|
5644 |
|
|
DI => blk00000003_sig000002b2,
|
5645 |
|
|
S => blk00000003_sig000002b3,
|
5646 |
|
|
O => blk00000003_sig000002af
|
5647 |
|
|
);
|
5648 |
|
|
blk00000003_blk0000010a : MUXCY
|
5649 |
|
|
port map (
|
5650 |
|
|
CI => blk00000003_sig000002af,
|
5651 |
|
|
DI => blk00000003_sig000002b0,
|
5652 |
|
|
S => blk00000003_sig000002b1,
|
5653 |
|
|
O => blk00000003_sig000002ac
|
5654 |
|
|
);
|
5655 |
|
|
blk00000003_blk00000109 : MUXCY
|
5656 |
|
|
port map (
|
5657 |
|
|
CI => blk00000003_sig000002ac,
|
5658 |
|
|
DI => blk00000003_sig000002ad,
|
5659 |
|
|
S => blk00000003_sig000002ae,
|
5660 |
|
|
O => blk00000003_sig000002a9
|
5661 |
|
|
);
|
5662 |
|
|
blk00000003_blk00000108 : MUXCY
|
5663 |
|
|
port map (
|
5664 |
|
|
CI => blk00000003_sig000002a9,
|
5665 |
|
|
DI => blk00000003_sig000002aa,
|
5666 |
|
|
S => blk00000003_sig000002ab,
|
5667 |
|
|
O => blk00000003_sig000002a6
|
5668 |
|
|
);
|
5669 |
|
|
blk00000003_blk00000107 : MUXCY
|
5670 |
|
|
port map (
|
5671 |
|
|
CI => blk00000003_sig000002a6,
|
5672 |
|
|
DI => blk00000003_sig000002a7,
|
5673 |
|
|
S => blk00000003_sig000002a8,
|
5674 |
|
|
O => blk00000003_sig000002a3
|
5675 |
|
|
);
|
5676 |
|
|
blk00000003_blk00000106 : MUXCY
|
5677 |
|
|
port map (
|
5678 |
|
|
CI => blk00000003_sig000002a3,
|
5679 |
|
|
DI => blk00000003_sig000002a4,
|
5680 |
|
|
S => blk00000003_sig000002a5,
|
5681 |
|
|
O => blk00000003_sig000002a0
|
5682 |
|
|
);
|
5683 |
|
|
blk00000003_blk00000105 : MUXCY
|
5684 |
|
|
port map (
|
5685 |
|
|
CI => blk00000003_sig000002a0,
|
5686 |
|
|
DI => blk00000003_sig000002a1,
|
5687 |
|
|
S => blk00000003_sig000002a2,
|
5688 |
|
|
O => blk00000003_sig0000029d
|
5689 |
|
|
);
|
5690 |
|
|
blk00000003_blk00000104 : MUXCY
|
5691 |
|
|
port map (
|
5692 |
|
|
CI => blk00000003_sig0000029d,
|
5693 |
|
|
DI => blk00000003_sig0000029e,
|
5694 |
|
|
S => blk00000003_sig0000029f,
|
5695 |
|
|
O => blk00000003_sig0000029a
|
5696 |
|
|
);
|
5697 |
|
|
blk00000003_blk00000103 : MUXCY
|
5698 |
|
|
port map (
|
5699 |
|
|
CI => blk00000003_sig0000029a,
|
5700 |
|
|
DI => blk00000003_sig0000029b,
|
5701 |
|
|
S => blk00000003_sig0000029c,
|
5702 |
|
|
O => blk00000003_sig00000297
|
5703 |
|
|
);
|
5704 |
|
|
blk00000003_blk00000102 : MUXCY
|
5705 |
|
|
port map (
|
5706 |
|
|
CI => blk00000003_sig00000297,
|
5707 |
|
|
DI => blk00000003_sig00000298,
|
5708 |
|
|
S => blk00000003_sig00000299,
|
5709 |
|
|
O => blk00000003_sig00000294
|
5710 |
|
|
);
|
5711 |
|
|
blk00000003_blk00000101 : MUXCY
|
5712 |
|
|
port map (
|
5713 |
|
|
CI => blk00000003_sig00000294,
|
5714 |
|
|
DI => blk00000003_sig00000295,
|
5715 |
|
|
S => blk00000003_sig00000296,
|
5716 |
|
|
O => blk00000003_sig00000291
|
5717 |
|
|
);
|
5718 |
|
|
blk00000003_blk00000100 : MUXCY
|
5719 |
|
|
port map (
|
5720 |
|
|
CI => blk00000003_sig00000291,
|
5721 |
|
|
DI => blk00000003_sig00000292,
|
5722 |
|
|
S => blk00000003_sig00000293,
|
5723 |
|
|
O => blk00000003_sig0000028e
|
5724 |
|
|
);
|
5725 |
|
|
blk00000003_blk000000ff : MUXCY
|
5726 |
|
|
port map (
|
5727 |
|
|
CI => blk00000003_sig0000028e,
|
5728 |
|
|
DI => blk00000003_sig0000028f,
|
5729 |
|
|
S => blk00000003_sig00000290,
|
5730 |
|
|
O => blk00000003_sig0000028b
|
5731 |
|
|
);
|
5732 |
|
|
blk00000003_blk000000fe : MUXCY
|
5733 |
|
|
port map (
|
5734 |
|
|
CI => blk00000003_sig0000028b,
|
5735 |
|
|
DI => blk00000003_sig0000028c,
|
5736 |
|
|
S => blk00000003_sig0000028d,
|
5737 |
|
|
O => blk00000003_sig00000288
|
5738 |
|
|
);
|
5739 |
|
|
blk00000003_blk000000fd : MUXCY
|
5740 |
|
|
port map (
|
5741 |
|
|
CI => blk00000003_sig00000288,
|
5742 |
|
|
DI => blk00000003_sig00000289,
|
5743 |
|
|
S => blk00000003_sig0000028a,
|
5744 |
|
|
O => blk00000003_sig00000284
|
5745 |
|
|
);
|
5746 |
|
|
blk00000003_blk000000fc : MUXCY
|
5747 |
|
|
port map (
|
5748 |
|
|
CI => blk00000003_sig00000284,
|
5749 |
|
|
DI => blk00000003_sig00000285,
|
5750 |
|
|
S => blk00000003_sig00000286,
|
5751 |
|
|
O => blk00000003_sig00000287
|
5752 |
|
|
);
|
5753 |
|
|
blk00000003_blk000000fb : FDE
|
5754 |
|
|
generic map(
|
5755 |
|
|
INIT => '0'
|
5756 |
|
|
)
|
5757 |
|
|
port map (
|
5758 |
|
|
C => sig00000042,
|
5759 |
|
|
CE => blk00000003_sig00000067,
|
5760 |
|
|
D => blk00000003_sig00000283,
|
5761 |
|
|
Q => blk00000003_sig0000022d
|
5762 |
|
|
);
|
5763 |
|
|
blk00000003_blk000000fa : FDE
|
5764 |
|
|
generic map(
|
5765 |
|
|
INIT => '0'
|
5766 |
|
|
)
|
5767 |
|
|
port map (
|
5768 |
|
|
C => sig00000042,
|
5769 |
|
|
CE => blk00000003_sig00000067,
|
5770 |
|
|
D => blk00000003_sig00000282,
|
5771 |
|
|
Q => blk00000003_sig0000022e
|
5772 |
|
|
);
|
5773 |
|
|
blk00000003_blk000000f9 : FDE
|
5774 |
|
|
generic map(
|
5775 |
|
|
INIT => '0'
|
5776 |
|
|
)
|
5777 |
|
|
port map (
|
5778 |
|
|
C => sig00000042,
|
5779 |
|
|
CE => blk00000003_sig00000067,
|
5780 |
|
|
D => blk00000003_sig00000281,
|
5781 |
|
|
Q => blk00000003_sig0000022f
|
5782 |
|
|
);
|
5783 |
|
|
blk00000003_blk000000f8 : FDE
|
5784 |
|
|
generic map(
|
5785 |
|
|
INIT => '0'
|
5786 |
|
|
)
|
5787 |
|
|
port map (
|
5788 |
|
|
C => sig00000042,
|
5789 |
|
|
CE => blk00000003_sig00000067,
|
5790 |
|
|
D => blk00000003_sig00000280,
|
5791 |
|
|
Q => blk00000003_sig00000230
|
5792 |
|
|
);
|
5793 |
|
|
blk00000003_blk000000f7 : FDE
|
5794 |
|
|
generic map(
|
5795 |
|
|
INIT => '0'
|
5796 |
|
|
)
|
5797 |
|
|
port map (
|
5798 |
|
|
C => sig00000042,
|
5799 |
|
|
CE => blk00000003_sig00000067,
|
5800 |
|
|
D => blk00000003_sig0000027f,
|
5801 |
|
|
Q => blk00000003_sig00000231
|
5802 |
|
|
);
|
5803 |
|
|
blk00000003_blk000000f6 : FDE
|
5804 |
|
|
generic map(
|
5805 |
|
|
INIT => '0'
|
5806 |
|
|
)
|
5807 |
|
|
port map (
|
5808 |
|
|
C => sig00000042,
|
5809 |
|
|
CE => blk00000003_sig00000067,
|
5810 |
|
|
D => blk00000003_sig0000027e,
|
5811 |
|
|
Q => blk00000003_sig00000232
|
5812 |
|
|
);
|
5813 |
|
|
blk00000003_blk000000f5 : FDE
|
5814 |
|
|
generic map(
|
5815 |
|
|
INIT => '0'
|
5816 |
|
|
)
|
5817 |
|
|
port map (
|
5818 |
|
|
C => sig00000042,
|
5819 |
|
|
CE => blk00000003_sig00000067,
|
5820 |
|
|
D => blk00000003_sig0000027d,
|
5821 |
|
|
Q => blk00000003_sig00000233
|
5822 |
|
|
);
|
5823 |
|
|
blk00000003_blk000000f4 : FDE
|
5824 |
|
|
generic map(
|
5825 |
|
|
INIT => '0'
|
5826 |
|
|
)
|
5827 |
|
|
port map (
|
5828 |
|
|
C => sig00000042,
|
5829 |
|
|
CE => blk00000003_sig00000067,
|
5830 |
|
|
D => blk00000003_sig0000027c,
|
5831 |
|
|
Q => blk00000003_sig00000234
|
5832 |
|
|
);
|
5833 |
|
|
blk00000003_blk000000f3 : FDE
|
5834 |
|
|
generic map(
|
5835 |
|
|
INIT => '0'
|
5836 |
|
|
)
|
5837 |
|
|
port map (
|
5838 |
|
|
C => sig00000042,
|
5839 |
|
|
CE => blk00000003_sig00000067,
|
5840 |
|
|
D => blk00000003_sig0000027b,
|
5841 |
|
|
Q => blk00000003_sig00000235
|
5842 |
|
|
);
|
5843 |
|
|
blk00000003_blk000000f2 : FDE
|
5844 |
|
|
generic map(
|
5845 |
|
|
INIT => '0'
|
5846 |
|
|
)
|
5847 |
|
|
port map (
|
5848 |
|
|
C => sig00000042,
|
5849 |
|
|
CE => blk00000003_sig00000067,
|
5850 |
|
|
D => blk00000003_sig0000027a,
|
5851 |
|
|
Q => blk00000003_sig00000236
|
5852 |
|
|
);
|
5853 |
|
|
blk00000003_blk000000f1 : FDE
|
5854 |
|
|
generic map(
|
5855 |
|
|
INIT => '0'
|
5856 |
|
|
)
|
5857 |
|
|
port map (
|
5858 |
|
|
C => sig00000042,
|
5859 |
|
|
CE => blk00000003_sig00000067,
|
5860 |
|
|
D => blk00000003_sig00000279,
|
5861 |
|
|
Q => blk00000003_sig00000237
|
5862 |
|
|
);
|
5863 |
|
|
blk00000003_blk000000f0 : FDE
|
5864 |
|
|
generic map(
|
5865 |
|
|
INIT => '0'
|
5866 |
|
|
)
|
5867 |
|
|
port map (
|
5868 |
|
|
C => sig00000042,
|
5869 |
|
|
CE => blk00000003_sig00000067,
|
5870 |
|
|
D => blk00000003_sig00000278,
|
5871 |
|
|
Q => blk00000003_sig00000238
|
5872 |
|
|
);
|
5873 |
|
|
blk00000003_blk000000ef : FDE
|
5874 |
|
|
generic map(
|
5875 |
|
|
INIT => '0'
|
5876 |
|
|
)
|
5877 |
|
|
port map (
|
5878 |
|
|
C => sig00000042,
|
5879 |
|
|
CE => blk00000003_sig00000067,
|
5880 |
|
|
D => blk00000003_sig00000277,
|
5881 |
|
|
Q => blk00000003_sig00000239
|
5882 |
|
|
);
|
5883 |
|
|
blk00000003_blk000000ee : FDE
|
5884 |
|
|
generic map(
|
5885 |
|
|
INIT => '0'
|
5886 |
|
|
)
|
5887 |
|
|
port map (
|
5888 |
|
|
C => sig00000042,
|
5889 |
|
|
CE => blk00000003_sig00000067,
|
5890 |
|
|
D => blk00000003_sig00000276,
|
5891 |
|
|
Q => blk00000003_sig0000023a
|
5892 |
|
|
);
|
5893 |
|
|
blk00000003_blk000000ed : FDE
|
5894 |
|
|
generic map(
|
5895 |
|
|
INIT => '0'
|
5896 |
|
|
)
|
5897 |
|
|
port map (
|
5898 |
|
|
C => sig00000042,
|
5899 |
|
|
CE => blk00000003_sig00000067,
|
5900 |
|
|
D => blk00000003_sig00000275,
|
5901 |
|
|
Q => blk00000003_sig0000023b
|
5902 |
|
|
);
|
5903 |
|
|
blk00000003_blk000000ec : FDE
|
5904 |
|
|
generic map(
|
5905 |
|
|
INIT => '0'
|
5906 |
|
|
)
|
5907 |
|
|
port map (
|
5908 |
|
|
C => sig00000042,
|
5909 |
|
|
CE => blk00000003_sig00000067,
|
5910 |
|
|
D => blk00000003_sig00000274,
|
5911 |
|
|
Q => blk00000003_sig0000023c
|
5912 |
|
|
);
|
5913 |
|
|
blk00000003_blk000000eb : FDE
|
5914 |
|
|
generic map(
|
5915 |
|
|
INIT => '0'
|
5916 |
|
|
)
|
5917 |
|
|
port map (
|
5918 |
|
|
C => sig00000042,
|
5919 |
|
|
CE => blk00000003_sig00000067,
|
5920 |
|
|
D => blk00000003_sig00000272,
|
5921 |
|
|
Q => blk00000003_sig00000273
|
5922 |
|
|
);
|
5923 |
|
|
blk00000003_blk000000ea : FDE
|
5924 |
|
|
generic map(
|
5925 |
|
|
INIT => '0'
|
5926 |
|
|
)
|
5927 |
|
|
port map (
|
5928 |
|
|
C => sig00000042,
|
5929 |
|
|
CE => blk00000003_sig00000067,
|
5930 |
|
|
D => blk00000003_sig00000271,
|
5931 |
|
|
Q => blk00000003_sig0000021d
|
5932 |
|
|
);
|
5933 |
|
|
blk00000003_blk000000e9 : FDE
|
5934 |
|
|
generic map(
|
5935 |
|
|
INIT => '0'
|
5936 |
|
|
)
|
5937 |
|
|
port map (
|
5938 |
|
|
C => sig00000042,
|
5939 |
|
|
CE => blk00000003_sig00000067,
|
5940 |
|
|
D => blk00000003_sig00000270,
|
5941 |
|
|
Q => blk00000003_sig0000026b
|
5942 |
|
|
);
|
5943 |
|
|
blk00000003_blk000000e8 : FDE
|
5944 |
|
|
generic map(
|
5945 |
|
|
INIT => '0'
|
5946 |
|
|
)
|
5947 |
|
|
port map (
|
5948 |
|
|
C => sig00000042,
|
5949 |
|
|
CE => blk00000003_sig00000067,
|
5950 |
|
|
D => blk00000003_sig0000026f,
|
5951 |
|
|
Q => blk00000003_sig0000023d
|
5952 |
|
|
);
|
5953 |
|
|
blk00000003_blk000000e7 : FDE
|
5954 |
|
|
generic map(
|
5955 |
|
|
INIT => '0'
|
5956 |
|
|
)
|
5957 |
|
|
port map (
|
5958 |
|
|
C => sig00000042,
|
5959 |
|
|
CE => blk00000003_sig00000067,
|
5960 |
|
|
D => blk00000003_sig0000026e,
|
5961 |
|
|
Q => blk00000003_sig0000026f
|
5962 |
|
|
);
|
5963 |
|
|
blk00000003_blk000000e6 : FDE
|
5964 |
|
|
generic map(
|
5965 |
|
|
INIT => '0'
|
5966 |
|
|
)
|
5967 |
|
|
port map (
|
5968 |
|
|
C => sig00000042,
|
5969 |
|
|
CE => blk00000003_sig00000067,
|
5970 |
|
|
D => blk00000003_sig0000026d,
|
5971 |
|
|
Q => blk00000003_sig0000023e
|
5972 |
|
|
);
|
5973 |
|
|
blk00000003_blk000000e5 : FDE
|
5974 |
|
|
generic map(
|
5975 |
|
|
INIT => '0'
|
5976 |
|
|
)
|
5977 |
|
|
port map (
|
5978 |
|
|
C => sig00000042,
|
5979 |
|
|
CE => blk00000003_sig00000067,
|
5980 |
|
|
D => blk00000003_sig0000026c,
|
5981 |
|
|
Q => blk00000003_sig0000026d
|
5982 |
|
|
);
|
5983 |
|
|
blk00000003_blk000000e4 : FDE
|
5984 |
|
|
generic map(
|
5985 |
|
|
INIT => '0'
|
5986 |
|
|
)
|
5987 |
|
|
port map (
|
5988 |
|
|
C => sig00000042,
|
5989 |
|
|
CE => blk00000003_sig00000067,
|
5990 |
|
|
D => blk00000003_sig0000026b,
|
5991 |
|
|
Q => blk00000003_sig0000023f
|
5992 |
|
|
);
|
5993 |
|
|
blk00000003_blk000000e3 : FDE
|
5994 |
|
|
generic map(
|
5995 |
|
|
INIT => '0'
|
5996 |
|
|
)
|
5997 |
|
|
port map (
|
5998 |
|
|
C => sig00000042,
|
5999 |
|
|
CE => blk00000003_sig00000067,
|
6000 |
|
|
D => blk00000003_sig00000269,
|
6001 |
|
|
Q => blk00000003_sig0000026a
|
6002 |
|
|
);
|
6003 |
|
|
blk00000003_blk000000e2 : XORCY
|
6004 |
|
|
port map (
|
6005 |
|
|
CI => blk00000003_sig00000211,
|
6006 |
|
|
LI => blk00000003_sig00000268,
|
6007 |
|
|
O => NLW_blk00000003_blk000000e2_O_UNCONNECTED
|
6008 |
|
|
);
|
6009 |
|
|
blk00000003_blk000000e1 : MUXCY
|
6010 |
|
|
port map (
|
6011 |
|
|
CI => blk00000003_sig00000211,
|
6012 |
|
|
DI => blk00000003_sig00000067,
|
6013 |
|
|
S => blk00000003_sig00000268,
|
6014 |
|
|
O => blk00000003_sig00000269
|
6015 |
|
|
);
|
6016 |
|
|
blk00000003_blk000000e0 : DSP48E
|
6017 |
|
|
generic map(
|
6018 |
|
|
ACASCREG => 1,
|
6019 |
|
|
ALUMODEREG => 1,
|
6020 |
|
|
AREG => 1,
|
6021 |
|
|
AUTORESET_PATTERN_DETECT => FALSE,
|
6022 |
|
|
AUTORESET_PATTERN_DETECT_OPTINV => "MATCH",
|
6023 |
|
|
A_INPUT => "DIRECT",
|
6024 |
|
|
BCASCREG => 1,
|
6025 |
|
|
BREG => 1,
|
6026 |
|
|
B_INPUT => "DIRECT",
|
6027 |
|
|
CARRYINREG => 1,
|
6028 |
|
|
CARRYINSELREG => 1,
|
6029 |
|
|
CREG => 1,
|
6030 |
|
|
PATTERN => X"000000000000",
|
6031 |
|
|
MREG => 1,
|
6032 |
|
|
MULTCARRYINREG => 0,
|
6033 |
|
|
OPMODEREG => 1,
|
6034 |
|
|
PREG => 1,
|
6035 |
|
|
SEL_MASK => "MASK",
|
6036 |
|
|
SEL_PATTERN => "PATTERN",
|
6037 |
|
|
SEL_ROUNDING_MASK => "SEL_MASK",
|
6038 |
|
|
SIM_MODE => "SAFE",
|
6039 |
|
|
USE_MULT => "MULT_S",
|
6040 |
|
|
USE_PATTERN_DETECT => "PATDET",
|
6041 |
|
|
USE_SIMD => "ONE48",
|
6042 |
|
|
MASK => X"FF0000FFFFFF"
|
6043 |
|
|
)
|
6044 |
|
|
port map (
|
6045 |
|
|
CARRYIN => blk00000003_sig0000021d,
|
6046 |
|
|
CEA1 => blk00000003_sig00000066,
|
6047 |
|
|
CEA2 => blk00000003_sig00000067,
|
6048 |
|
|
CEB1 => blk00000003_sig00000066,
|
6049 |
|
|
CEB2 => blk00000003_sig00000067,
|
6050 |
|
|
CEC => blk00000003_sig00000067,
|
6051 |
|
|
CECTRL => blk00000003_sig00000067,
|
6052 |
|
|
CEP => blk00000003_sig00000067,
|
6053 |
|
|
CEM => blk00000003_sig00000067,
|
6054 |
|
|
CECARRYIN => blk00000003_sig00000067,
|
6055 |
|
|
CEMULTCARRYIN => blk00000003_sig00000066,
|
6056 |
|
|
CLK => sig00000042,
|
6057 |
|
|
RSTA => blk00000003_sig00000066,
|
6058 |
|
|
RSTB => blk00000003_sig00000066,
|
6059 |
|
|
RSTC => blk00000003_sig00000066,
|
6060 |
|
|
RSTCTRL => blk00000003_sig00000066,
|
6061 |
|
|
RSTP => blk00000003_sig00000066,
|
6062 |
|
|
RSTM => blk00000003_sig00000066,
|
6063 |
|
|
RSTALLCARRYIN => blk00000003_sig00000066,
|
6064 |
|
|
CEALUMODE => blk00000003_sig00000067,
|
6065 |
|
|
RSTALUMODE => blk00000003_sig00000066,
|
6066 |
|
|
PATTERNBDETECT => NLW_blk00000003_blk000000e0_PATTERNBDETECT_UNCONNECTED,
|
6067 |
|
|
PATTERNDETECT => blk00000003_sig0000015f,
|
6068 |
|
|
OVERFLOW => NLW_blk00000003_blk000000e0_OVERFLOW_UNCONNECTED,
|
6069 |
|
|
UNDERFLOW => NLW_blk00000003_blk000000e0_UNDERFLOW_UNCONNECTED,
|
6070 |
|
|
CARRYCASCIN => blk00000003_sig00000066,
|
6071 |
|
|
CARRYCASCOUT => NLW_blk00000003_blk000000e0_CARRYCASCOUT_UNCONNECTED,
|
6072 |
|
|
MULTSIGNIN => blk00000003_sig00000066,
|
6073 |
|
|
MULTSIGNOUT => NLW_blk00000003_blk000000e0_MULTSIGNOUT_UNCONNECTED,
|
6074 |
|
|
A(29) => blk00000003_sig00000066,
|
6075 |
|
|
A(28) => blk00000003_sig00000066,
|
6076 |
|
|
A(27) => blk00000003_sig00000066,
|
6077 |
|
|
A(26) => blk00000003_sig00000066,
|
6078 |
|
|
A(25) => blk00000003_sig00000066,
|
6079 |
|
|
A(24) => blk00000003_sig00000066,
|
6080 |
|
|
A(23) => blk00000003_sig0000021e,
|
6081 |
|
|
A(22) => blk00000003_sig0000021f,
|
6082 |
|
|
A(21) => blk00000003_sig00000220,
|
6083 |
|
|
A(20) => blk00000003_sig00000221,
|
6084 |
|
|
A(19) => blk00000003_sig00000222,
|
6085 |
|
|
A(18) => blk00000003_sig00000223,
|
6086 |
|
|
A(17) => blk00000003_sig00000224,
|
6087 |
|
|
A(16) => blk00000003_sig00000225,
|
6088 |
|
|
A(15) => blk00000003_sig00000226,
|
6089 |
|
|
A(14) => blk00000003_sig00000227,
|
6090 |
|
|
A(13) => blk00000003_sig00000228,
|
6091 |
|
|
A(12) => blk00000003_sig00000229,
|
6092 |
|
|
A(11) => blk00000003_sig0000022a,
|
6093 |
|
|
A(10) => blk00000003_sig0000022b,
|
6094 |
|
|
A(9) => blk00000003_sig0000022c,
|
6095 |
|
|
A(8) => blk00000003_sig000001c7,
|
6096 |
|
|
A(7) => blk00000003_sig000001c5,
|
6097 |
|
|
A(6) => blk00000003_sig000001c3,
|
6098 |
|
|
A(5) => blk00000003_sig000001c1,
|
6099 |
|
|
A(4) => blk00000003_sig000001bf,
|
6100 |
|
|
A(3) => blk00000003_sig000001bd,
|
6101 |
|
|
A(2) => blk00000003_sig000001bb,
|
6102 |
|
|
A(1) => blk00000003_sig000001b9,
|
6103 |
|
|
A(0) => blk00000003_sig000001b7,
|
6104 |
|
|
PCIN(47) => blk00000003_sig00000066,
|
6105 |
|
|
PCIN(46) => blk00000003_sig00000066,
|
6106 |
|
|
PCIN(45) => blk00000003_sig00000066,
|
6107 |
|
|
PCIN(44) => blk00000003_sig00000066,
|
6108 |
|
|
PCIN(43) => blk00000003_sig00000066,
|
6109 |
|
|
PCIN(42) => blk00000003_sig00000066,
|
6110 |
|
|
PCIN(41) => blk00000003_sig00000066,
|
6111 |
|
|
PCIN(40) => blk00000003_sig00000066,
|
6112 |
|
|
PCIN(39) => blk00000003_sig00000066,
|
6113 |
|
|
PCIN(38) => blk00000003_sig00000066,
|
6114 |
|
|
PCIN(37) => blk00000003_sig00000066,
|
6115 |
|
|
PCIN(36) => blk00000003_sig00000066,
|
6116 |
|
|
PCIN(35) => blk00000003_sig00000066,
|
6117 |
|
|
PCIN(34) => blk00000003_sig00000066,
|
6118 |
|
|
PCIN(33) => blk00000003_sig00000066,
|
6119 |
|
|
PCIN(32) => blk00000003_sig00000066,
|
6120 |
|
|
PCIN(31) => blk00000003_sig00000066,
|
6121 |
|
|
PCIN(30) => blk00000003_sig00000066,
|
6122 |
|
|
PCIN(29) => blk00000003_sig00000066,
|
6123 |
|
|
PCIN(28) => blk00000003_sig00000066,
|
6124 |
|
|
PCIN(27) => blk00000003_sig00000066,
|
6125 |
|
|
PCIN(26) => blk00000003_sig00000066,
|
6126 |
|
|
PCIN(25) => blk00000003_sig00000066,
|
6127 |
|
|
PCIN(24) => blk00000003_sig00000066,
|
6128 |
|
|
PCIN(23) => blk00000003_sig00000066,
|
6129 |
|
|
PCIN(22) => blk00000003_sig00000066,
|
6130 |
|
|
PCIN(21) => blk00000003_sig00000066,
|
6131 |
|
|
PCIN(20) => blk00000003_sig00000066,
|
6132 |
|
|
PCIN(19) => blk00000003_sig00000066,
|
6133 |
|
|
PCIN(18) => blk00000003_sig00000066,
|
6134 |
|
|
PCIN(17) => blk00000003_sig00000066,
|
6135 |
|
|
PCIN(16) => blk00000003_sig00000066,
|
6136 |
|
|
PCIN(15) => blk00000003_sig00000066,
|
6137 |
|
|
PCIN(14) => blk00000003_sig00000066,
|
6138 |
|
|
PCIN(13) => blk00000003_sig00000066,
|
6139 |
|
|
PCIN(12) => blk00000003_sig00000066,
|
6140 |
|
|
PCIN(11) => blk00000003_sig00000066,
|
6141 |
|
|
PCIN(10) => blk00000003_sig00000066,
|
6142 |
|
|
PCIN(9) => blk00000003_sig00000066,
|
6143 |
|
|
PCIN(8) => blk00000003_sig00000066,
|
6144 |
|
|
PCIN(7) => blk00000003_sig00000066,
|
6145 |
|
|
PCIN(6) => blk00000003_sig00000066,
|
6146 |
|
|
PCIN(5) => blk00000003_sig00000066,
|
6147 |
|
|
PCIN(4) => blk00000003_sig00000066,
|
6148 |
|
|
PCIN(3) => blk00000003_sig00000066,
|
6149 |
|
|
PCIN(2) => blk00000003_sig00000066,
|
6150 |
|
|
PCIN(1) => blk00000003_sig00000066,
|
6151 |
|
|
PCIN(0) => blk00000003_sig00000066,
|
6152 |
|
|
B(17) => blk00000003_sig00000066,
|
6153 |
|
|
B(16) => blk00000003_sig00000066,
|
6154 |
|
|
B(15) => blk00000003_sig0000022d,
|
6155 |
|
|
B(14) => blk00000003_sig0000022e,
|
6156 |
|
|
B(13) => blk00000003_sig0000022f,
|
6157 |
|
|
B(12) => blk00000003_sig00000230,
|
6158 |
|
|
B(11) => blk00000003_sig00000231,
|
6159 |
|
|
B(10) => blk00000003_sig00000232,
|
6160 |
|
|
B(9) => blk00000003_sig00000233,
|
6161 |
|
|
B(8) => blk00000003_sig00000234,
|
6162 |
|
|
B(7) => blk00000003_sig00000235,
|
6163 |
|
|
B(6) => blk00000003_sig00000236,
|
6164 |
|
|
B(5) => blk00000003_sig00000237,
|
6165 |
|
|
B(4) => blk00000003_sig00000238,
|
6166 |
|
|
B(3) => blk00000003_sig00000239,
|
6167 |
|
|
B(2) => blk00000003_sig0000023a,
|
6168 |
|
|
B(1) => blk00000003_sig0000023b,
|
6169 |
|
|
B(0) => blk00000003_sig0000023c,
|
6170 |
|
|
C(47) => blk00000003_sig00000066,
|
6171 |
|
|
C(46) => blk00000003_sig00000066,
|
6172 |
|
|
C(45) => blk00000003_sig00000066,
|
6173 |
|
|
C(44) => blk00000003_sig00000066,
|
6174 |
|
|
C(43) => blk00000003_sig00000066,
|
6175 |
|
|
C(42) => blk00000003_sig00000066,
|
6176 |
|
|
C(41) => blk00000003_sig00000066,
|
6177 |
|
|
C(40) => blk00000003_sig00000066,
|
6178 |
|
|
C(39) => blk00000003_sig00000066,
|
6179 |
|
|
C(38) => blk00000003_sig0000020e,
|
6180 |
|
|
C(37) => blk00000003_sig0000020d,
|
6181 |
|
|
C(36) => blk00000003_sig0000020c,
|
6182 |
|
|
C(35) => blk00000003_sig0000020b,
|
6183 |
|
|
C(34) => blk00000003_sig0000020a,
|
6184 |
|
|
C(33) => blk00000003_sig00000209,
|
6185 |
|
|
C(32) => blk00000003_sig00000208,
|
6186 |
|
|
C(31) => blk00000003_sig00000207,
|
6187 |
|
|
C(30) => blk00000003_sig00000206,
|
6188 |
|
|
C(29) => blk00000003_sig00000205,
|
6189 |
|
|
C(28) => blk00000003_sig00000204,
|
6190 |
|
|
C(27) => blk00000003_sig00000203,
|
6191 |
|
|
C(26) => blk00000003_sig00000202,
|
6192 |
|
|
C(25) => blk00000003_sig00000201,
|
6193 |
|
|
C(24) => blk00000003_sig00000200,
|
6194 |
|
|
C(23) => blk00000003_sig000001ff,
|
6195 |
|
|
C(22) => blk00000003_sig000001fe,
|
6196 |
|
|
C(21) => blk00000003_sig000001fd,
|
6197 |
|
|
C(20) => blk00000003_sig000001fc,
|
6198 |
|
|
C(19) => blk00000003_sig000001fb,
|
6199 |
|
|
C(18) => blk00000003_sig000001fa,
|
6200 |
|
|
C(17) => blk00000003_sig000001f9,
|
6201 |
|
|
C(16) => blk00000003_sig000001f8,
|
6202 |
|
|
C(15) => blk00000003_sig000001f7,
|
6203 |
|
|
C(14) => blk00000003_sig00000066,
|
6204 |
|
|
C(13) => blk00000003_sig00000066,
|
6205 |
|
|
C(12) => blk00000003_sig00000066,
|
6206 |
|
|
C(11) => blk00000003_sig00000066,
|
6207 |
|
|
C(10) => blk00000003_sig00000066,
|
6208 |
|
|
C(9) => blk00000003_sig00000066,
|
6209 |
|
|
C(8) => blk00000003_sig00000066,
|
6210 |
|
|
C(7) => blk00000003_sig00000066,
|
6211 |
|
|
C(6) => blk00000003_sig00000066,
|
6212 |
|
|
C(5) => blk00000003_sig00000066,
|
6213 |
|
|
C(4) => blk00000003_sig00000066,
|
6214 |
|
|
C(3) => blk00000003_sig00000066,
|
6215 |
|
|
C(2) => blk00000003_sig00000066,
|
6216 |
|
|
C(1) => blk00000003_sig00000066,
|
6217 |
|
|
C(0) => blk00000003_sig00000066,
|
6218 |
|
|
CARRYINSEL(2) => blk00000003_sig00000066,
|
6219 |
|
|
CARRYINSEL(1) => blk00000003_sig00000066,
|
6220 |
|
|
CARRYINSEL(0) => blk00000003_sig00000066,
|
6221 |
|
|
OPMODE(6) => blk00000003_sig00000066,
|
6222 |
|
|
OPMODE(5) => blk00000003_sig0000023d,
|
6223 |
|
|
OPMODE(4) => blk00000003_sig0000023d,
|
6224 |
|
|
OPMODE(3) => blk00000003_sig00000066,
|
6225 |
|
|
OPMODE(2) => blk00000003_sig0000023e,
|
6226 |
|
|
OPMODE(1) => blk00000003_sig00000066,
|
6227 |
|
|
OPMODE(0) => blk00000003_sig0000023e,
|
6228 |
|
|
BCIN(17) => blk00000003_sig00000066,
|
6229 |
|
|
BCIN(16) => blk00000003_sig00000066,
|
6230 |
|
|
BCIN(15) => blk00000003_sig00000066,
|
6231 |
|
|
BCIN(14) => blk00000003_sig00000066,
|
6232 |
|
|
BCIN(13) => blk00000003_sig00000066,
|
6233 |
|
|
BCIN(12) => blk00000003_sig00000066,
|
6234 |
|
|
BCIN(11) => blk00000003_sig00000066,
|
6235 |
|
|
BCIN(10) => blk00000003_sig00000066,
|
6236 |
|
|
BCIN(9) => blk00000003_sig00000066,
|
6237 |
|
|
BCIN(8) => blk00000003_sig00000066,
|
6238 |
|
|
BCIN(7) => blk00000003_sig00000066,
|
6239 |
|
|
BCIN(6) => blk00000003_sig00000066,
|
6240 |
|
|
BCIN(5) => blk00000003_sig00000066,
|
6241 |
|
|
BCIN(4) => blk00000003_sig00000066,
|
6242 |
|
|
BCIN(3) => blk00000003_sig00000066,
|
6243 |
|
|
BCIN(2) => blk00000003_sig00000066,
|
6244 |
|
|
BCIN(1) => blk00000003_sig00000066,
|
6245 |
|
|
BCIN(0) => blk00000003_sig00000066,
|
6246 |
|
|
ALUMODE(3) => blk00000003_sig00000066,
|
6247 |
|
|
ALUMODE(2) => blk00000003_sig00000066,
|
6248 |
|
|
ALUMODE(1) => blk00000003_sig0000023f,
|
6249 |
|
|
ALUMODE(0) => blk00000003_sig0000023f,
|
6250 |
|
|
PCOUT(47) => NLW_blk00000003_blk000000e0_PCOUT_47_UNCONNECTED,
|
6251 |
|
|
PCOUT(46) => NLW_blk00000003_blk000000e0_PCOUT_46_UNCONNECTED,
|
6252 |
|
|
PCOUT(45) => NLW_blk00000003_blk000000e0_PCOUT_45_UNCONNECTED,
|
6253 |
|
|
PCOUT(44) => NLW_blk00000003_blk000000e0_PCOUT_44_UNCONNECTED,
|
6254 |
|
|
PCOUT(43) => NLW_blk00000003_blk000000e0_PCOUT_43_UNCONNECTED,
|
6255 |
|
|
PCOUT(42) => NLW_blk00000003_blk000000e0_PCOUT_42_UNCONNECTED,
|
6256 |
|
|
PCOUT(41) => NLW_blk00000003_blk000000e0_PCOUT_41_UNCONNECTED,
|
6257 |
|
|
PCOUT(40) => NLW_blk00000003_blk000000e0_PCOUT_40_UNCONNECTED,
|
6258 |
|
|
PCOUT(39) => NLW_blk00000003_blk000000e0_PCOUT_39_UNCONNECTED,
|
6259 |
|
|
PCOUT(38) => NLW_blk00000003_blk000000e0_PCOUT_38_UNCONNECTED,
|
6260 |
|
|
PCOUT(37) => NLW_blk00000003_blk000000e0_PCOUT_37_UNCONNECTED,
|
6261 |
|
|
PCOUT(36) => NLW_blk00000003_blk000000e0_PCOUT_36_UNCONNECTED,
|
6262 |
|
|
PCOUT(35) => NLW_blk00000003_blk000000e0_PCOUT_35_UNCONNECTED,
|
6263 |
|
|
PCOUT(34) => NLW_blk00000003_blk000000e0_PCOUT_34_UNCONNECTED,
|
6264 |
|
|
PCOUT(33) => NLW_blk00000003_blk000000e0_PCOUT_33_UNCONNECTED,
|
6265 |
|
|
PCOUT(32) => NLW_blk00000003_blk000000e0_PCOUT_32_UNCONNECTED,
|
6266 |
|
|
PCOUT(31) => NLW_blk00000003_blk000000e0_PCOUT_31_UNCONNECTED,
|
6267 |
|
|
PCOUT(30) => NLW_blk00000003_blk000000e0_PCOUT_30_UNCONNECTED,
|
6268 |
|
|
PCOUT(29) => NLW_blk00000003_blk000000e0_PCOUT_29_UNCONNECTED,
|
6269 |
|
|
PCOUT(28) => NLW_blk00000003_blk000000e0_PCOUT_28_UNCONNECTED,
|
6270 |
|
|
PCOUT(27) => NLW_blk00000003_blk000000e0_PCOUT_27_UNCONNECTED,
|
6271 |
|
|
PCOUT(26) => NLW_blk00000003_blk000000e0_PCOUT_26_UNCONNECTED,
|
6272 |
|
|
PCOUT(25) => NLW_blk00000003_blk000000e0_PCOUT_25_UNCONNECTED,
|
6273 |
|
|
PCOUT(24) => NLW_blk00000003_blk000000e0_PCOUT_24_UNCONNECTED,
|
6274 |
|
|
PCOUT(23) => NLW_blk00000003_blk000000e0_PCOUT_23_UNCONNECTED,
|
6275 |
|
|
PCOUT(22) => NLW_blk00000003_blk000000e0_PCOUT_22_UNCONNECTED,
|
6276 |
|
|
PCOUT(21) => NLW_blk00000003_blk000000e0_PCOUT_21_UNCONNECTED,
|
6277 |
|
|
PCOUT(20) => NLW_blk00000003_blk000000e0_PCOUT_20_UNCONNECTED,
|
6278 |
|
|
PCOUT(19) => NLW_blk00000003_blk000000e0_PCOUT_19_UNCONNECTED,
|
6279 |
|
|
PCOUT(18) => NLW_blk00000003_blk000000e0_PCOUT_18_UNCONNECTED,
|
6280 |
|
|
PCOUT(17) => NLW_blk00000003_blk000000e0_PCOUT_17_UNCONNECTED,
|
6281 |
|
|
PCOUT(16) => NLW_blk00000003_blk000000e0_PCOUT_16_UNCONNECTED,
|
6282 |
|
|
PCOUT(15) => NLW_blk00000003_blk000000e0_PCOUT_15_UNCONNECTED,
|
6283 |
|
|
PCOUT(14) => NLW_blk00000003_blk000000e0_PCOUT_14_UNCONNECTED,
|
6284 |
|
|
PCOUT(13) => NLW_blk00000003_blk000000e0_PCOUT_13_UNCONNECTED,
|
6285 |
|
|
PCOUT(12) => NLW_blk00000003_blk000000e0_PCOUT_12_UNCONNECTED,
|
6286 |
|
|
PCOUT(11) => NLW_blk00000003_blk000000e0_PCOUT_11_UNCONNECTED,
|
6287 |
|
|
PCOUT(10) => NLW_blk00000003_blk000000e0_PCOUT_10_UNCONNECTED,
|
6288 |
|
|
PCOUT(9) => NLW_blk00000003_blk000000e0_PCOUT_9_UNCONNECTED,
|
6289 |
|
|
PCOUT(8) => NLW_blk00000003_blk000000e0_PCOUT_8_UNCONNECTED,
|
6290 |
|
|
PCOUT(7) => NLW_blk00000003_blk000000e0_PCOUT_7_UNCONNECTED,
|
6291 |
|
|
PCOUT(6) => NLW_blk00000003_blk000000e0_PCOUT_6_UNCONNECTED,
|
6292 |
|
|
PCOUT(5) => NLW_blk00000003_blk000000e0_PCOUT_5_UNCONNECTED,
|
6293 |
|
|
PCOUT(4) => NLW_blk00000003_blk000000e0_PCOUT_4_UNCONNECTED,
|
6294 |
|
|
PCOUT(3) => NLW_blk00000003_blk000000e0_PCOUT_3_UNCONNECTED,
|
6295 |
|
|
PCOUT(2) => NLW_blk00000003_blk000000e0_PCOUT_2_UNCONNECTED,
|
6296 |
|
|
PCOUT(1) => NLW_blk00000003_blk000000e0_PCOUT_1_UNCONNECTED,
|
6297 |
|
|
PCOUT(0) => NLW_blk00000003_blk000000e0_PCOUT_0_UNCONNECTED,
|
6298 |
|
|
P(47) => NLW_blk00000003_blk000000e0_P_47_UNCONNECTED,
|
6299 |
|
|
P(46) => NLW_blk00000003_blk000000e0_P_46_UNCONNECTED,
|
6300 |
|
|
P(45) => NLW_blk00000003_blk000000e0_P_45_UNCONNECTED,
|
6301 |
|
|
P(44) => NLW_blk00000003_blk000000e0_P_44_UNCONNECTED,
|
6302 |
|
|
P(43) => NLW_blk00000003_blk000000e0_P_43_UNCONNECTED,
|
6303 |
|
|
P(42) => NLW_blk00000003_blk000000e0_P_42_UNCONNECTED,
|
6304 |
|
|
P(41) => NLW_blk00000003_blk000000e0_P_41_UNCONNECTED,
|
6305 |
|
|
P(40) => NLW_blk00000003_blk000000e0_P_40_UNCONNECTED,
|
6306 |
|
|
P(39) => blk00000003_sig00000240,
|
6307 |
|
|
P(38) => blk00000003_sig00000241,
|
6308 |
|
|
P(37) => blk00000003_sig00000242,
|
6309 |
|
|
P(36) => blk00000003_sig00000243,
|
6310 |
|
|
P(35) => blk00000003_sig00000244,
|
6311 |
|
|
P(34) => blk00000003_sig00000245,
|
6312 |
|
|
P(33) => blk00000003_sig00000246,
|
6313 |
|
|
P(32) => blk00000003_sig00000247,
|
6314 |
|
|
P(31) => blk00000003_sig00000248,
|
6315 |
|
|
P(30) => blk00000003_sig00000249,
|
6316 |
|
|
P(29) => blk00000003_sig0000024a,
|
6317 |
|
|
P(28) => blk00000003_sig0000024b,
|
6318 |
|
|
P(27) => blk00000003_sig0000024c,
|
6319 |
|
|
P(26) => blk00000003_sig0000024d,
|
6320 |
|
|
P(25) => blk00000003_sig0000024e,
|
6321 |
|
|
P(24) => blk00000003_sig0000024f,
|
6322 |
|
|
P(23) => blk00000003_sig00000250,
|
6323 |
|
|
P(22) => blk00000003_sig00000251,
|
6324 |
|
|
P(21) => blk00000003_sig00000252,
|
6325 |
|
|
P(20) => blk00000003_sig00000253,
|
6326 |
|
|
P(19) => blk00000003_sig00000254,
|
6327 |
|
|
P(18) => blk00000003_sig00000255,
|
6328 |
|
|
P(17) => blk00000003_sig00000256,
|
6329 |
|
|
P(16) => blk00000003_sig00000257,
|
6330 |
|
|
P(15) => blk00000003_sig00000258,
|
6331 |
|
|
P(14) => blk00000003_sig00000259,
|
6332 |
|
|
P(13) => blk00000003_sig0000025a,
|
6333 |
|
|
P(12) => blk00000003_sig0000025b,
|
6334 |
|
|
P(11) => blk00000003_sig0000025c,
|
6335 |
|
|
P(10) => blk00000003_sig0000025d,
|
6336 |
|
|
P(9) => blk00000003_sig0000025e,
|
6337 |
|
|
P(8) => blk00000003_sig0000025f,
|
6338 |
|
|
P(7) => blk00000003_sig00000260,
|
6339 |
|
|
P(6) => blk00000003_sig00000261,
|
6340 |
|
|
P(5) => blk00000003_sig00000262,
|
6341 |
|
|
P(4) => blk00000003_sig00000263,
|
6342 |
|
|
P(3) => blk00000003_sig00000264,
|
6343 |
|
|
P(2) => blk00000003_sig00000265,
|
6344 |
|
|
P(1) => blk00000003_sig00000266,
|
6345 |
|
|
P(0) => blk00000003_sig00000267,
|
6346 |
|
|
BCOUT(17) => NLW_blk00000003_blk000000e0_BCOUT_17_UNCONNECTED,
|
6347 |
|
|
BCOUT(16) => NLW_blk00000003_blk000000e0_BCOUT_16_UNCONNECTED,
|
6348 |
|
|
BCOUT(15) => NLW_blk00000003_blk000000e0_BCOUT_15_UNCONNECTED,
|
6349 |
|
|
BCOUT(14) => NLW_blk00000003_blk000000e0_BCOUT_14_UNCONNECTED,
|
6350 |
|
|
BCOUT(13) => NLW_blk00000003_blk000000e0_BCOUT_13_UNCONNECTED,
|
6351 |
|
|
BCOUT(12) => NLW_blk00000003_blk000000e0_BCOUT_12_UNCONNECTED,
|
6352 |
|
|
BCOUT(11) => NLW_blk00000003_blk000000e0_BCOUT_11_UNCONNECTED,
|
6353 |
|
|
BCOUT(10) => NLW_blk00000003_blk000000e0_BCOUT_10_UNCONNECTED,
|
6354 |
|
|
BCOUT(9) => NLW_blk00000003_blk000000e0_BCOUT_9_UNCONNECTED,
|
6355 |
|
|
BCOUT(8) => NLW_blk00000003_blk000000e0_BCOUT_8_UNCONNECTED,
|
6356 |
|
|
BCOUT(7) => NLW_blk00000003_blk000000e0_BCOUT_7_UNCONNECTED,
|
6357 |
|
|
BCOUT(6) => NLW_blk00000003_blk000000e0_BCOUT_6_UNCONNECTED,
|
6358 |
|
|
BCOUT(5) => NLW_blk00000003_blk000000e0_BCOUT_5_UNCONNECTED,
|
6359 |
|
|
BCOUT(4) => NLW_blk00000003_blk000000e0_BCOUT_4_UNCONNECTED,
|
6360 |
|
|
BCOUT(3) => NLW_blk00000003_blk000000e0_BCOUT_3_UNCONNECTED,
|
6361 |
|
|
BCOUT(2) => NLW_blk00000003_blk000000e0_BCOUT_2_UNCONNECTED,
|
6362 |
|
|
BCOUT(1) => NLW_blk00000003_blk000000e0_BCOUT_1_UNCONNECTED,
|
6363 |
|
|
BCOUT(0) => NLW_blk00000003_blk000000e0_BCOUT_0_UNCONNECTED,
|
6364 |
|
|
ACIN(29) => blk00000003_sig00000066,
|
6365 |
|
|
ACIN(28) => blk00000003_sig00000066,
|
6366 |
|
|
ACIN(27) => blk00000003_sig00000066,
|
6367 |
|
|
ACIN(26) => blk00000003_sig00000066,
|
6368 |
|
|
ACIN(25) => blk00000003_sig00000066,
|
6369 |
|
|
ACIN(24) => blk00000003_sig00000066,
|
6370 |
|
|
ACIN(23) => blk00000003_sig00000066,
|
6371 |
|
|
ACIN(22) => blk00000003_sig00000066,
|
6372 |
|
|
ACIN(21) => blk00000003_sig00000066,
|
6373 |
|
|
ACIN(20) => blk00000003_sig00000066,
|
6374 |
|
|
ACIN(19) => blk00000003_sig00000066,
|
6375 |
|
|
ACIN(18) => blk00000003_sig00000066,
|
6376 |
|
|
ACIN(17) => blk00000003_sig00000066,
|
6377 |
|
|
ACIN(16) => blk00000003_sig00000066,
|
6378 |
|
|
ACIN(15) => blk00000003_sig00000066,
|
6379 |
|
|
ACIN(14) => blk00000003_sig00000066,
|
6380 |
|
|
ACIN(13) => blk00000003_sig00000066,
|
6381 |
|
|
ACIN(12) => blk00000003_sig00000066,
|
6382 |
|
|
ACIN(11) => blk00000003_sig00000066,
|
6383 |
|
|
ACIN(10) => blk00000003_sig00000066,
|
6384 |
|
|
ACIN(9) => blk00000003_sig00000066,
|
6385 |
|
|
ACIN(8) => blk00000003_sig00000066,
|
6386 |
|
|
ACIN(7) => blk00000003_sig00000066,
|
6387 |
|
|
ACIN(6) => blk00000003_sig00000066,
|
6388 |
|
|
ACIN(5) => blk00000003_sig00000066,
|
6389 |
|
|
ACIN(4) => blk00000003_sig00000066,
|
6390 |
|
|
ACIN(3) => blk00000003_sig00000066,
|
6391 |
|
|
ACIN(2) => blk00000003_sig00000066,
|
6392 |
|
|
ACIN(1) => blk00000003_sig00000066,
|
6393 |
|
|
ACIN(0) => blk00000003_sig00000066,
|
6394 |
|
|
ACOUT(29) => NLW_blk00000003_blk000000e0_ACOUT_29_UNCONNECTED,
|
6395 |
|
|
ACOUT(28) => NLW_blk00000003_blk000000e0_ACOUT_28_UNCONNECTED,
|
6396 |
|
|
ACOUT(27) => NLW_blk00000003_blk000000e0_ACOUT_27_UNCONNECTED,
|
6397 |
|
|
ACOUT(26) => NLW_blk00000003_blk000000e0_ACOUT_26_UNCONNECTED,
|
6398 |
|
|
ACOUT(25) => NLW_blk00000003_blk000000e0_ACOUT_25_UNCONNECTED,
|
6399 |
|
|
ACOUT(24) => NLW_blk00000003_blk000000e0_ACOUT_24_UNCONNECTED,
|
6400 |
|
|
ACOUT(23) => NLW_blk00000003_blk000000e0_ACOUT_23_UNCONNECTED,
|
6401 |
|
|
ACOUT(22) => NLW_blk00000003_blk000000e0_ACOUT_22_UNCONNECTED,
|
6402 |
|
|
ACOUT(21) => NLW_blk00000003_blk000000e0_ACOUT_21_UNCONNECTED,
|
6403 |
|
|
ACOUT(20) => NLW_blk00000003_blk000000e0_ACOUT_20_UNCONNECTED,
|
6404 |
|
|
ACOUT(19) => NLW_blk00000003_blk000000e0_ACOUT_19_UNCONNECTED,
|
6405 |
|
|
ACOUT(18) => NLW_blk00000003_blk000000e0_ACOUT_18_UNCONNECTED,
|
6406 |
|
|
ACOUT(17) => NLW_blk00000003_blk000000e0_ACOUT_17_UNCONNECTED,
|
6407 |
|
|
ACOUT(16) => NLW_blk00000003_blk000000e0_ACOUT_16_UNCONNECTED,
|
6408 |
|
|
ACOUT(15) => NLW_blk00000003_blk000000e0_ACOUT_15_UNCONNECTED,
|
6409 |
|
|
ACOUT(14) => NLW_blk00000003_blk000000e0_ACOUT_14_UNCONNECTED,
|
6410 |
|
|
ACOUT(13) => NLW_blk00000003_blk000000e0_ACOUT_13_UNCONNECTED,
|
6411 |
|
|
ACOUT(12) => NLW_blk00000003_blk000000e0_ACOUT_12_UNCONNECTED,
|
6412 |
|
|
ACOUT(11) => NLW_blk00000003_blk000000e0_ACOUT_11_UNCONNECTED,
|
6413 |
|
|
ACOUT(10) => NLW_blk00000003_blk000000e0_ACOUT_10_UNCONNECTED,
|
6414 |
|
|
ACOUT(9) => NLW_blk00000003_blk000000e0_ACOUT_9_UNCONNECTED,
|
6415 |
|
|
ACOUT(8) => NLW_blk00000003_blk000000e0_ACOUT_8_UNCONNECTED,
|
6416 |
|
|
ACOUT(7) => NLW_blk00000003_blk000000e0_ACOUT_7_UNCONNECTED,
|
6417 |
|
|
ACOUT(6) => NLW_blk00000003_blk000000e0_ACOUT_6_UNCONNECTED,
|
6418 |
|
|
ACOUT(5) => NLW_blk00000003_blk000000e0_ACOUT_5_UNCONNECTED,
|
6419 |
|
|
ACOUT(4) => NLW_blk00000003_blk000000e0_ACOUT_4_UNCONNECTED,
|
6420 |
|
|
ACOUT(3) => NLW_blk00000003_blk000000e0_ACOUT_3_UNCONNECTED,
|
6421 |
|
|
ACOUT(2) => NLW_blk00000003_blk000000e0_ACOUT_2_UNCONNECTED,
|
6422 |
|
|
ACOUT(1) => NLW_blk00000003_blk000000e0_ACOUT_1_UNCONNECTED,
|
6423 |
|
|
ACOUT(0) => NLW_blk00000003_blk000000e0_ACOUT_0_UNCONNECTED,
|
6424 |
|
|
CARRYOUT(3) => NLW_blk00000003_blk000000e0_CARRYOUT_3_UNCONNECTED,
|
6425 |
|
|
CARRYOUT(2) => NLW_blk00000003_blk000000e0_CARRYOUT_2_UNCONNECTED,
|
6426 |
|
|
CARRYOUT(1) => NLW_blk00000003_blk000000e0_CARRYOUT_1_UNCONNECTED,
|
6427 |
|
|
CARRYOUT(0) => NLW_blk00000003_blk000000e0_CARRYOUT_0_UNCONNECTED
|
6428 |
|
|
);
|
6429 |
|
|
blk00000003_blk000000df : MUXCY
|
6430 |
|
|
port map (
|
6431 |
|
|
CI => blk00000003_sig00000067,
|
6432 |
|
|
DI => blk00000003_sig00000066,
|
6433 |
|
|
S => blk00000003_sig0000021c,
|
6434 |
|
|
O => blk00000003_sig0000021a
|
6435 |
|
|
);
|
6436 |
|
|
blk00000003_blk000000de : MUXCY
|
6437 |
|
|
port map (
|
6438 |
|
|
CI => blk00000003_sig0000021a,
|
6439 |
|
|
DI => blk00000003_sig00000066,
|
6440 |
|
|
S => blk00000003_sig0000021b,
|
6441 |
|
|
O => blk00000003_sig00000218
|
6442 |
|
|
);
|
6443 |
|
|
blk00000003_blk000000dd : MUXCY
|
6444 |
|
|
port map (
|
6445 |
|
|
CI => blk00000003_sig00000218,
|
6446 |
|
|
DI => blk00000003_sig00000066,
|
6447 |
|
|
S => blk00000003_sig00000219,
|
6448 |
|
|
O => blk00000003_sig00000216
|
6449 |
|
|
);
|
6450 |
|
|
blk00000003_blk000000dc : MUXCY
|
6451 |
|
|
port map (
|
6452 |
|
|
CI => blk00000003_sig00000216,
|
6453 |
|
|
DI => blk00000003_sig00000066,
|
6454 |
|
|
S => blk00000003_sig00000217,
|
6455 |
|
|
O => blk00000003_sig00000214
|
6456 |
|
|
);
|
6457 |
|
|
blk00000003_blk000000db : MUXCY
|
6458 |
|
|
port map (
|
6459 |
|
|
CI => blk00000003_sig00000214,
|
6460 |
|
|
DI => blk00000003_sig00000066,
|
6461 |
|
|
S => blk00000003_sig00000215,
|
6462 |
|
|
O => blk00000003_sig00000212
|
6463 |
|
|
);
|
6464 |
|
|
blk00000003_blk000000da : MUXCY
|
6465 |
|
|
port map (
|
6466 |
|
|
CI => blk00000003_sig00000212,
|
6467 |
|
|
DI => blk00000003_sig00000066,
|
6468 |
|
|
S => blk00000003_sig00000213,
|
6469 |
|
|
O => blk00000003_sig0000020f
|
6470 |
|
|
);
|
6471 |
|
|
blk00000003_blk000000d9 : MUXCY
|
6472 |
|
|
port map (
|
6473 |
|
|
CI => blk00000003_sig0000020f,
|
6474 |
|
|
DI => blk00000003_sig00000066,
|
6475 |
|
|
S => blk00000003_sig00000210,
|
6476 |
|
|
O => blk00000003_sig00000211
|
6477 |
|
|
);
|
6478 |
|
|
blk00000003_blk000000d8 : FD
|
6479 |
|
|
generic map(
|
6480 |
|
|
INIT => '0'
|
6481 |
|
|
)
|
6482 |
|
|
port map (
|
6483 |
|
|
C => sig00000042,
|
6484 |
|
|
D => blk00000003_sig000001f6,
|
6485 |
|
|
Q => blk00000003_sig0000020e
|
6486 |
|
|
);
|
6487 |
|
|
blk00000003_blk000000d7 : FD
|
6488 |
|
|
generic map(
|
6489 |
|
|
INIT => '0'
|
6490 |
|
|
)
|
6491 |
|
|
port map (
|
6492 |
|
|
C => sig00000042,
|
6493 |
|
|
D => blk00000003_sig000001f5,
|
6494 |
|
|
Q => blk00000003_sig0000020d
|
6495 |
|
|
);
|
6496 |
|
|
blk00000003_blk000000d6 : FD
|
6497 |
|
|
generic map(
|
6498 |
|
|
INIT => '0'
|
6499 |
|
|
)
|
6500 |
|
|
port map (
|
6501 |
|
|
C => sig00000042,
|
6502 |
|
|
D => blk00000003_sig000001f3,
|
6503 |
|
|
Q => blk00000003_sig0000020c
|
6504 |
|
|
);
|
6505 |
|
|
blk00000003_blk000000d5 : FD
|
6506 |
|
|
generic map(
|
6507 |
|
|
INIT => '0'
|
6508 |
|
|
)
|
6509 |
|
|
port map (
|
6510 |
|
|
C => sig00000042,
|
6511 |
|
|
D => blk00000003_sig000001f1,
|
6512 |
|
|
Q => blk00000003_sig0000020b
|
6513 |
|
|
);
|
6514 |
|
|
blk00000003_blk000000d4 : FD
|
6515 |
|
|
generic map(
|
6516 |
|
|
INIT => '0'
|
6517 |
|
|
)
|
6518 |
|
|
port map (
|
6519 |
|
|
C => sig00000042,
|
6520 |
|
|
D => blk00000003_sig000001ef,
|
6521 |
|
|
Q => blk00000003_sig0000020a
|
6522 |
|
|
);
|
6523 |
|
|
blk00000003_blk000000d3 : FD
|
6524 |
|
|
generic map(
|
6525 |
|
|
INIT => '0'
|
6526 |
|
|
)
|
6527 |
|
|
port map (
|
6528 |
|
|
C => sig00000042,
|
6529 |
|
|
D => blk00000003_sig000001ed,
|
6530 |
|
|
Q => blk00000003_sig00000209
|
6531 |
|
|
);
|
6532 |
|
|
blk00000003_blk000000d2 : FD
|
6533 |
|
|
generic map(
|
6534 |
|
|
INIT => '0'
|
6535 |
|
|
)
|
6536 |
|
|
port map (
|
6537 |
|
|
C => sig00000042,
|
6538 |
|
|
D => blk00000003_sig000001eb,
|
6539 |
|
|
Q => blk00000003_sig00000208
|
6540 |
|
|
);
|
6541 |
|
|
blk00000003_blk000000d1 : FD
|
6542 |
|
|
generic map(
|
6543 |
|
|
INIT => '0'
|
6544 |
|
|
)
|
6545 |
|
|
port map (
|
6546 |
|
|
C => sig00000042,
|
6547 |
|
|
D => blk00000003_sig000001e9,
|
6548 |
|
|
Q => blk00000003_sig00000207
|
6549 |
|
|
);
|
6550 |
|
|
blk00000003_blk000000d0 : FD
|
6551 |
|
|
generic map(
|
6552 |
|
|
INIT => '0'
|
6553 |
|
|
)
|
6554 |
|
|
port map (
|
6555 |
|
|
C => sig00000042,
|
6556 |
|
|
D => blk00000003_sig000001e7,
|
6557 |
|
|
Q => blk00000003_sig00000206
|
6558 |
|
|
);
|
6559 |
|
|
blk00000003_blk000000cf : FD
|
6560 |
|
|
generic map(
|
6561 |
|
|
INIT => '0'
|
6562 |
|
|
)
|
6563 |
|
|
port map (
|
6564 |
|
|
C => sig00000042,
|
6565 |
|
|
D => blk00000003_sig000001e5,
|
6566 |
|
|
Q => blk00000003_sig00000205
|
6567 |
|
|
);
|
6568 |
|
|
blk00000003_blk000000ce : FD
|
6569 |
|
|
generic map(
|
6570 |
|
|
INIT => '0'
|
6571 |
|
|
)
|
6572 |
|
|
port map (
|
6573 |
|
|
C => sig00000042,
|
6574 |
|
|
D => blk00000003_sig000001e3,
|
6575 |
|
|
Q => blk00000003_sig00000204
|
6576 |
|
|
);
|
6577 |
|
|
blk00000003_blk000000cd : FD
|
6578 |
|
|
generic map(
|
6579 |
|
|
INIT => '0'
|
6580 |
|
|
)
|
6581 |
|
|
port map (
|
6582 |
|
|
C => sig00000042,
|
6583 |
|
|
D => blk00000003_sig000001e1,
|
6584 |
|
|
Q => blk00000003_sig00000203
|
6585 |
|
|
);
|
6586 |
|
|
blk00000003_blk000000cc : FD
|
6587 |
|
|
generic map(
|
6588 |
|
|
INIT => '0'
|
6589 |
|
|
)
|
6590 |
|
|
port map (
|
6591 |
|
|
C => sig00000042,
|
6592 |
|
|
D => blk00000003_sig000001df,
|
6593 |
|
|
Q => blk00000003_sig00000202
|
6594 |
|
|
);
|
6595 |
|
|
blk00000003_blk000000cb : FD
|
6596 |
|
|
generic map(
|
6597 |
|
|
INIT => '0'
|
6598 |
|
|
)
|
6599 |
|
|
port map (
|
6600 |
|
|
C => sig00000042,
|
6601 |
|
|
D => blk00000003_sig000001dd,
|
6602 |
|
|
Q => blk00000003_sig00000201
|
6603 |
|
|
);
|
6604 |
|
|
blk00000003_blk000000ca : FD
|
6605 |
|
|
generic map(
|
6606 |
|
|
INIT => '0'
|
6607 |
|
|
)
|
6608 |
|
|
port map (
|
6609 |
|
|
C => sig00000042,
|
6610 |
|
|
D => blk00000003_sig000001db,
|
6611 |
|
|
Q => blk00000003_sig00000200
|
6612 |
|
|
);
|
6613 |
|
|
blk00000003_blk000000c9 : FD
|
6614 |
|
|
generic map(
|
6615 |
|
|
INIT => '0'
|
6616 |
|
|
)
|
6617 |
|
|
port map (
|
6618 |
|
|
C => sig00000042,
|
6619 |
|
|
D => blk00000003_sig000001d9,
|
6620 |
|
|
Q => blk00000003_sig000001ff
|
6621 |
|
|
);
|
6622 |
|
|
blk00000003_blk000000c8 : FD
|
6623 |
|
|
generic map(
|
6624 |
|
|
INIT => '0'
|
6625 |
|
|
)
|
6626 |
|
|
port map (
|
6627 |
|
|
C => sig00000042,
|
6628 |
|
|
D => blk00000003_sig000001d7,
|
6629 |
|
|
Q => blk00000003_sig000001fe
|
6630 |
|
|
);
|
6631 |
|
|
blk00000003_blk000000c7 : FD
|
6632 |
|
|
generic map(
|
6633 |
|
|
INIT => '0'
|
6634 |
|
|
)
|
6635 |
|
|
port map (
|
6636 |
|
|
C => sig00000042,
|
6637 |
|
|
D => blk00000003_sig000001d5,
|
6638 |
|
|
Q => blk00000003_sig000001fd
|
6639 |
|
|
);
|
6640 |
|
|
blk00000003_blk000000c6 : FD
|
6641 |
|
|
generic map(
|
6642 |
|
|
INIT => '0'
|
6643 |
|
|
)
|
6644 |
|
|
port map (
|
6645 |
|
|
C => sig00000042,
|
6646 |
|
|
D => blk00000003_sig000001d3,
|
6647 |
|
|
Q => blk00000003_sig000001fc
|
6648 |
|
|
);
|
6649 |
|
|
blk00000003_blk000000c5 : FD
|
6650 |
|
|
generic map(
|
6651 |
|
|
INIT => '0'
|
6652 |
|
|
)
|
6653 |
|
|
port map (
|
6654 |
|
|
C => sig00000042,
|
6655 |
|
|
D => blk00000003_sig000001d1,
|
6656 |
|
|
Q => blk00000003_sig000001fb
|
6657 |
|
|
);
|
6658 |
|
|
blk00000003_blk000000c4 : FD
|
6659 |
|
|
generic map(
|
6660 |
|
|
INIT => '0'
|
6661 |
|
|
)
|
6662 |
|
|
port map (
|
6663 |
|
|
C => sig00000042,
|
6664 |
|
|
D => blk00000003_sig000001cf,
|
6665 |
|
|
Q => blk00000003_sig000001fa
|
6666 |
|
|
);
|
6667 |
|
|
blk00000003_blk000000c3 : FD
|
6668 |
|
|
generic map(
|
6669 |
|
|
INIT => '0'
|
6670 |
|
|
)
|
6671 |
|
|
port map (
|
6672 |
|
|
C => sig00000042,
|
6673 |
|
|
D => blk00000003_sig000001cd,
|
6674 |
|
|
Q => blk00000003_sig000001f9
|
6675 |
|
|
);
|
6676 |
|
|
blk00000003_blk000000c2 : FD
|
6677 |
|
|
generic map(
|
6678 |
|
|
INIT => '0'
|
6679 |
|
|
)
|
6680 |
|
|
port map (
|
6681 |
|
|
C => sig00000042,
|
6682 |
|
|
D => blk00000003_sig000001cb,
|
6683 |
|
|
Q => blk00000003_sig000001f8
|
6684 |
|
|
);
|
6685 |
|
|
blk00000003_blk000000c1 : FD
|
6686 |
|
|
generic map(
|
6687 |
|
|
INIT => '0'
|
6688 |
|
|
)
|
6689 |
|
|
port map (
|
6690 |
|
|
C => sig00000042,
|
6691 |
|
|
D => blk00000003_sig000001c9,
|
6692 |
|
|
Q => blk00000003_sig000001f7
|
6693 |
|
|
);
|
6694 |
|
|
blk00000003_blk000000c0 : FD
|
6695 |
|
|
generic map(
|
6696 |
|
|
INIT => '0'
|
6697 |
|
|
)
|
6698 |
|
|
port map (
|
6699 |
|
|
C => sig00000042,
|
6700 |
|
|
D => blk00000003_sig00000067,
|
6701 |
|
|
Q => blk00000003_sig000001f6
|
6702 |
|
|
);
|
6703 |
|
|
blk00000003_blk000000bf : FD
|
6704 |
|
|
generic map(
|
6705 |
|
|
INIT => '0'
|
6706 |
|
|
)
|
6707 |
|
|
port map (
|
6708 |
|
|
C => sig00000042,
|
6709 |
|
|
D => blk00000003_sig000001f4,
|
6710 |
|
|
Q => blk00000003_sig000001f5
|
6711 |
|
|
);
|
6712 |
|
|
blk00000003_blk000000be : FD
|
6713 |
|
|
generic map(
|
6714 |
|
|
INIT => '0'
|
6715 |
|
|
)
|
6716 |
|
|
port map (
|
6717 |
|
|
C => sig00000042,
|
6718 |
|
|
D => blk00000003_sig000001f2,
|
6719 |
|
|
Q => blk00000003_sig000001f3
|
6720 |
|
|
);
|
6721 |
|
|
blk00000003_blk000000bd : FD
|
6722 |
|
|
generic map(
|
6723 |
|
|
INIT => '0'
|
6724 |
|
|
)
|
6725 |
|
|
port map (
|
6726 |
|
|
C => sig00000042,
|
6727 |
|
|
D => blk00000003_sig000001f0,
|
6728 |
|
|
Q => blk00000003_sig000001f1
|
6729 |
|
|
);
|
6730 |
|
|
blk00000003_blk000000bc : FD
|
6731 |
|
|
generic map(
|
6732 |
|
|
INIT => '0'
|
6733 |
|
|
)
|
6734 |
|
|
port map (
|
6735 |
|
|
C => sig00000042,
|
6736 |
|
|
D => blk00000003_sig000001ee,
|
6737 |
|
|
Q => blk00000003_sig000001ef
|
6738 |
|
|
);
|
6739 |
|
|
blk00000003_blk000000bb : FD
|
6740 |
|
|
generic map(
|
6741 |
|
|
INIT => '0'
|
6742 |
|
|
)
|
6743 |
|
|
port map (
|
6744 |
|
|
C => sig00000042,
|
6745 |
|
|
D => blk00000003_sig000001ec,
|
6746 |
|
|
Q => blk00000003_sig000001ed
|
6747 |
|
|
);
|
6748 |
|
|
blk00000003_blk000000ba : FD
|
6749 |
|
|
generic map(
|
6750 |
|
|
INIT => '0'
|
6751 |
|
|
)
|
6752 |
|
|
port map (
|
6753 |
|
|
C => sig00000042,
|
6754 |
|
|
D => blk00000003_sig000001ea,
|
6755 |
|
|
Q => blk00000003_sig000001eb
|
6756 |
|
|
);
|
6757 |
|
|
blk00000003_blk000000b9 : FD
|
6758 |
|
|
generic map(
|
6759 |
|
|
INIT => '0'
|
6760 |
|
|
)
|
6761 |
|
|
port map (
|
6762 |
|
|
C => sig00000042,
|
6763 |
|
|
D => blk00000003_sig000001e8,
|
6764 |
|
|
Q => blk00000003_sig000001e9
|
6765 |
|
|
);
|
6766 |
|
|
blk00000003_blk000000b8 : FD
|
6767 |
|
|
generic map(
|
6768 |
|
|
INIT => '0'
|
6769 |
|
|
)
|
6770 |
|
|
port map (
|
6771 |
|
|
C => sig00000042,
|
6772 |
|
|
D => blk00000003_sig000001e6,
|
6773 |
|
|
Q => blk00000003_sig000001e7
|
6774 |
|
|
);
|
6775 |
|
|
blk00000003_blk000000b7 : FD
|
6776 |
|
|
generic map(
|
6777 |
|
|
INIT => '0'
|
6778 |
|
|
)
|
6779 |
|
|
port map (
|
6780 |
|
|
C => sig00000042,
|
6781 |
|
|
D => blk00000003_sig000001e4,
|
6782 |
|
|
Q => blk00000003_sig000001e5
|
6783 |
|
|
);
|
6784 |
|
|
blk00000003_blk000000b6 : FD
|
6785 |
|
|
generic map(
|
6786 |
|
|
INIT => '0'
|
6787 |
|
|
)
|
6788 |
|
|
port map (
|
6789 |
|
|
C => sig00000042,
|
6790 |
|
|
D => blk00000003_sig000001e2,
|
6791 |
|
|
Q => blk00000003_sig000001e3
|
6792 |
|
|
);
|
6793 |
|
|
blk00000003_blk000000b5 : FD
|
6794 |
|
|
generic map(
|
6795 |
|
|
INIT => '0'
|
6796 |
|
|
)
|
6797 |
|
|
port map (
|
6798 |
|
|
C => sig00000042,
|
6799 |
|
|
D => blk00000003_sig000001e0,
|
6800 |
|
|
Q => blk00000003_sig000001e1
|
6801 |
|
|
);
|
6802 |
|
|
blk00000003_blk000000b4 : FD
|
6803 |
|
|
generic map(
|
6804 |
|
|
INIT => '0'
|
6805 |
|
|
)
|
6806 |
|
|
port map (
|
6807 |
|
|
C => sig00000042,
|
6808 |
|
|
D => blk00000003_sig000001de,
|
6809 |
|
|
Q => blk00000003_sig000001df
|
6810 |
|
|
);
|
6811 |
|
|
blk00000003_blk000000b3 : FD
|
6812 |
|
|
generic map(
|
6813 |
|
|
INIT => '0'
|
6814 |
|
|
)
|
6815 |
|
|
port map (
|
6816 |
|
|
C => sig00000042,
|
6817 |
|
|
D => blk00000003_sig000001dc,
|
6818 |
|
|
Q => blk00000003_sig000001dd
|
6819 |
|
|
);
|
6820 |
|
|
blk00000003_blk000000b2 : FD
|
6821 |
|
|
generic map(
|
6822 |
|
|
INIT => '0'
|
6823 |
|
|
)
|
6824 |
|
|
port map (
|
6825 |
|
|
C => sig00000042,
|
6826 |
|
|
D => blk00000003_sig000001da,
|
6827 |
|
|
Q => blk00000003_sig000001db
|
6828 |
|
|
);
|
6829 |
|
|
blk00000003_blk000000b1 : FD
|
6830 |
|
|
generic map(
|
6831 |
|
|
INIT => '0'
|
6832 |
|
|
)
|
6833 |
|
|
port map (
|
6834 |
|
|
C => sig00000042,
|
6835 |
|
|
D => blk00000003_sig000001d8,
|
6836 |
|
|
Q => blk00000003_sig000001d9
|
6837 |
|
|
);
|
6838 |
|
|
blk00000003_blk000000b0 : FD
|
6839 |
|
|
generic map(
|
6840 |
|
|
INIT => '0'
|
6841 |
|
|
)
|
6842 |
|
|
port map (
|
6843 |
|
|
C => sig00000042,
|
6844 |
|
|
D => blk00000003_sig000001d6,
|
6845 |
|
|
Q => blk00000003_sig000001d7
|
6846 |
|
|
);
|
6847 |
|
|
blk00000003_blk000000af : FD
|
6848 |
|
|
generic map(
|
6849 |
|
|
INIT => '0'
|
6850 |
|
|
)
|
6851 |
|
|
port map (
|
6852 |
|
|
C => sig00000042,
|
6853 |
|
|
D => blk00000003_sig000001d4,
|
6854 |
|
|
Q => blk00000003_sig000001d5
|
6855 |
|
|
);
|
6856 |
|
|
blk00000003_blk000000ae : FD
|
6857 |
|
|
generic map(
|
6858 |
|
|
INIT => '0'
|
6859 |
|
|
)
|
6860 |
|
|
port map (
|
6861 |
|
|
C => sig00000042,
|
6862 |
|
|
D => blk00000003_sig000001d2,
|
6863 |
|
|
Q => blk00000003_sig000001d3
|
6864 |
|
|
);
|
6865 |
|
|
blk00000003_blk000000ad : FD
|
6866 |
|
|
generic map(
|
6867 |
|
|
INIT => '0'
|
6868 |
|
|
)
|
6869 |
|
|
port map (
|
6870 |
|
|
C => sig00000042,
|
6871 |
|
|
D => blk00000003_sig000001d0,
|
6872 |
|
|
Q => blk00000003_sig000001d1
|
6873 |
|
|
);
|
6874 |
|
|
blk00000003_blk000000ac : FD
|
6875 |
|
|
generic map(
|
6876 |
|
|
INIT => '0'
|
6877 |
|
|
)
|
6878 |
|
|
port map (
|
6879 |
|
|
C => sig00000042,
|
6880 |
|
|
D => blk00000003_sig000001ce,
|
6881 |
|
|
Q => blk00000003_sig000001cf
|
6882 |
|
|
);
|
6883 |
|
|
blk00000003_blk000000ab : FD
|
6884 |
|
|
generic map(
|
6885 |
|
|
INIT => '0'
|
6886 |
|
|
)
|
6887 |
|
|
port map (
|
6888 |
|
|
C => sig00000042,
|
6889 |
|
|
D => blk00000003_sig000001cc,
|
6890 |
|
|
Q => blk00000003_sig000001cd
|
6891 |
|
|
);
|
6892 |
|
|
blk00000003_blk000000aa : FD
|
6893 |
|
|
generic map(
|
6894 |
|
|
INIT => '0'
|
6895 |
|
|
)
|
6896 |
|
|
port map (
|
6897 |
|
|
C => sig00000042,
|
6898 |
|
|
D => blk00000003_sig000001ca,
|
6899 |
|
|
Q => blk00000003_sig000001cb
|
6900 |
|
|
);
|
6901 |
|
|
blk00000003_blk000000a9 : FD
|
6902 |
|
|
generic map(
|
6903 |
|
|
INIT => '0'
|
6904 |
|
|
)
|
6905 |
|
|
port map (
|
6906 |
|
|
C => sig00000042,
|
6907 |
|
|
D => blk00000003_sig000001c8,
|
6908 |
|
|
Q => blk00000003_sig000001c9
|
6909 |
|
|
);
|
6910 |
|
|
blk00000003_blk000000a8 : FD
|
6911 |
|
|
generic map(
|
6912 |
|
|
INIT => '0'
|
6913 |
|
|
)
|
6914 |
|
|
port map (
|
6915 |
|
|
C => sig00000042,
|
6916 |
|
|
D => blk00000003_sig000001c6,
|
6917 |
|
|
Q => blk00000003_sig000001c7
|
6918 |
|
|
);
|
6919 |
|
|
blk00000003_blk000000a7 : FD
|
6920 |
|
|
generic map(
|
6921 |
|
|
INIT => '0'
|
6922 |
|
|
)
|
6923 |
|
|
port map (
|
6924 |
|
|
C => sig00000042,
|
6925 |
|
|
D => blk00000003_sig000001c4,
|
6926 |
|
|
Q => blk00000003_sig000001c5
|
6927 |
|
|
);
|
6928 |
|
|
blk00000003_blk000000a6 : FD
|
6929 |
|
|
generic map(
|
6930 |
|
|
INIT => '0'
|
6931 |
|
|
)
|
6932 |
|
|
port map (
|
6933 |
|
|
C => sig00000042,
|
6934 |
|
|
D => blk00000003_sig000001c2,
|
6935 |
|
|
Q => blk00000003_sig000001c3
|
6936 |
|
|
);
|
6937 |
|
|
blk00000003_blk000000a5 : FD
|
6938 |
|
|
generic map(
|
6939 |
|
|
INIT => '0'
|
6940 |
|
|
)
|
6941 |
|
|
port map (
|
6942 |
|
|
C => sig00000042,
|
6943 |
|
|
D => blk00000003_sig000001c0,
|
6944 |
|
|
Q => blk00000003_sig000001c1
|
6945 |
|
|
);
|
6946 |
|
|
blk00000003_blk000000a4 : FD
|
6947 |
|
|
generic map(
|
6948 |
|
|
INIT => '0'
|
6949 |
|
|
)
|
6950 |
|
|
port map (
|
6951 |
|
|
C => sig00000042,
|
6952 |
|
|
D => blk00000003_sig000001be,
|
6953 |
|
|
Q => blk00000003_sig000001bf
|
6954 |
|
|
);
|
6955 |
|
|
blk00000003_blk000000a3 : FD
|
6956 |
|
|
generic map(
|
6957 |
|
|
INIT => '0'
|
6958 |
|
|
)
|
6959 |
|
|
port map (
|
6960 |
|
|
C => sig00000042,
|
6961 |
|
|
D => blk00000003_sig000001bc,
|
6962 |
|
|
Q => blk00000003_sig000001bd
|
6963 |
|
|
);
|
6964 |
|
|
blk00000003_blk000000a2 : FD
|
6965 |
|
|
generic map(
|
6966 |
|
|
INIT => '0'
|
6967 |
|
|
)
|
6968 |
|
|
port map (
|
6969 |
|
|
C => sig00000042,
|
6970 |
|
|
D => blk00000003_sig000001ba,
|
6971 |
|
|
Q => blk00000003_sig000001bb
|
6972 |
|
|
);
|
6973 |
|
|
blk00000003_blk000000a1 : FD
|
6974 |
|
|
generic map(
|
6975 |
|
|
INIT => '0'
|
6976 |
|
|
)
|
6977 |
|
|
port map (
|
6978 |
|
|
C => sig00000042,
|
6979 |
|
|
D => blk00000003_sig000001b8,
|
6980 |
|
|
Q => blk00000003_sig000001b9
|
6981 |
|
|
);
|
6982 |
|
|
blk00000003_blk000000a0 : FD
|
6983 |
|
|
generic map(
|
6984 |
|
|
INIT => '0'
|
6985 |
|
|
)
|
6986 |
|
|
port map (
|
6987 |
|
|
C => sig00000042,
|
6988 |
|
|
D => blk00000003_sig000001b6,
|
6989 |
|
|
Q => blk00000003_sig000001b7
|
6990 |
|
|
);
|
6991 |
|
|
blk00000003_blk0000009f : FDE
|
6992 |
|
|
generic map(
|
6993 |
|
|
INIT => '0'
|
6994 |
|
|
)
|
6995 |
|
|
port map (
|
6996 |
|
|
C => sig00000042,
|
6997 |
|
|
CE => blk00000003_sig00000067,
|
6998 |
|
|
D => blk00000003_sig000001b5,
|
6999 |
|
|
Q => blk00000003_sig000001a8
|
7000 |
|
|
);
|
7001 |
|
|
blk00000003_blk0000009e : FDE
|
7002 |
|
|
generic map(
|
7003 |
|
|
INIT => '0'
|
7004 |
|
|
)
|
7005 |
|
|
port map (
|
7006 |
|
|
C => sig00000042,
|
7007 |
|
|
CE => blk00000003_sig00000067,
|
7008 |
|
|
D => blk00000003_sig000001b3,
|
7009 |
|
|
Q => blk00000003_sig000001b4
|
7010 |
|
|
);
|
7011 |
|
|
blk00000003_blk0000009d : FDE
|
7012 |
|
|
generic map(
|
7013 |
|
|
INIT => '0'
|
7014 |
|
|
)
|
7015 |
|
|
port map (
|
7016 |
|
|
C => sig00000042,
|
7017 |
|
|
CE => blk00000003_sig00000067,
|
7018 |
|
|
D => blk00000003_sig000001b1,
|
7019 |
|
|
Q => blk00000003_sig000001b2
|
7020 |
|
|
);
|
7021 |
|
|
blk00000003_blk0000009c : FDE
|
7022 |
|
|
generic map(
|
7023 |
|
|
INIT => '0'
|
7024 |
|
|
)
|
7025 |
|
|
port map (
|
7026 |
|
|
C => sig00000042,
|
7027 |
|
|
CE => blk00000003_sig00000067,
|
7028 |
|
|
D => blk00000003_sig000001af,
|
7029 |
|
|
Q => blk00000003_sig000001b0
|
7030 |
|
|
);
|
7031 |
|
|
blk00000003_blk0000009b : FDE
|
7032 |
|
|
generic map(
|
7033 |
|
|
INIT => '0'
|
7034 |
|
|
)
|
7035 |
|
|
port map (
|
7036 |
|
|
C => sig00000042,
|
7037 |
|
|
CE => blk00000003_sig00000067,
|
7038 |
|
|
D => blk00000003_sig000001ae,
|
7039 |
|
|
Q => blk00000003_sig000001af
|
7040 |
|
|
);
|
7041 |
|
|
blk00000003_blk0000009a : FD
|
7042 |
|
|
generic map(
|
7043 |
|
|
INIT => '0'
|
7044 |
|
|
)
|
7045 |
|
|
port map (
|
7046 |
|
|
C => sig00000042,
|
7047 |
|
|
D => blk00000003_sig000001ac,
|
7048 |
|
|
Q => blk00000003_sig000001ad
|
7049 |
|
|
);
|
7050 |
|
|
blk00000003_blk00000099 : FD
|
7051 |
|
|
generic map(
|
7052 |
|
|
INIT => '0'
|
7053 |
|
|
)
|
7054 |
|
|
port map (
|
7055 |
|
|
C => sig00000042,
|
7056 |
|
|
D => blk00000003_sig000001ab,
|
7057 |
|
|
Q => blk00000003_sig000001ac
|
7058 |
|
|
);
|
7059 |
|
|
blk00000003_blk00000098 : FD
|
7060 |
|
|
generic map(
|
7061 |
|
|
INIT => '0'
|
7062 |
|
|
)
|
7063 |
|
|
port map (
|
7064 |
|
|
C => sig00000042,
|
7065 |
|
|
D => blk00000003_sig000001aa,
|
7066 |
|
|
Q => blk00000003_sig000001a7
|
7067 |
|
|
);
|
7068 |
|
|
blk00000003_blk00000097 : FD
|
7069 |
|
|
generic map(
|
7070 |
|
|
INIT => '0'
|
7071 |
|
|
)
|
7072 |
|
|
port map (
|
7073 |
|
|
C => sig00000042,
|
7074 |
|
|
D => blk00000003_sig000001a9,
|
7075 |
|
|
Q => blk00000003_sig000001aa
|
7076 |
|
|
);
|
7077 |
|
|
blk00000003_blk00000096 : DSP48E
|
7078 |
|
|
generic map(
|
7079 |
|
|
ACASCREG => 2,
|
7080 |
|
|
ALUMODEREG => 1,
|
7081 |
|
|
AREG => 2,
|
7082 |
|
|
AUTORESET_PATTERN_DETECT => FALSE,
|
7083 |
|
|
AUTORESET_PATTERN_DETECT_OPTINV => "MATCH",
|
7084 |
|
|
A_INPUT => "DIRECT",
|
7085 |
|
|
BCASCREG => 1,
|
7086 |
|
|
BREG => 1,
|
7087 |
|
|
B_INPUT => "DIRECT",
|
7088 |
|
|
CARRYINREG => 1,
|
7089 |
|
|
CARRYINSELREG => 1,
|
7090 |
|
|
CREG => 1,
|
7091 |
|
|
PATTERN => X"000000000000",
|
7092 |
|
|
MREG => 1,
|
7093 |
|
|
MULTCARRYINREG => 0,
|
7094 |
|
|
OPMODEREG => 1,
|
7095 |
|
|
PREG => 1,
|
7096 |
|
|
SEL_MASK => "MASK",
|
7097 |
|
|
SEL_PATTERN => "PATTERN",
|
7098 |
|
|
SEL_ROUNDING_MASK => "SEL_MASK",
|
7099 |
|
|
SIM_MODE => "SAFE",
|
7100 |
|
|
USE_MULT => "MULT_S",
|
7101 |
|
|
USE_PATTERN_DETECT => "NO_PATDET",
|
7102 |
|
|
USE_SIMD => "ONE48",
|
7103 |
|
|
MASK => X"3FFFFFFFFFFF"
|
7104 |
|
|
)
|
7105 |
|
|
port map (
|
7106 |
|
|
CARRYIN => blk00000003_sig00000066,
|
7107 |
|
|
CEA1 => blk00000003_sig00000067,
|
7108 |
|
|
CEA2 => blk00000003_sig00000067,
|
7109 |
|
|
CEB1 => blk00000003_sig00000066,
|
7110 |
|
|
CEB2 => blk00000003_sig00000067,
|
7111 |
|
|
CEC => blk00000003_sig00000067,
|
7112 |
|
|
CECTRL => blk00000003_sig00000067,
|
7113 |
|
|
CEP => blk00000003_sig00000067,
|
7114 |
|
|
CEM => blk00000003_sig00000067,
|
7115 |
|
|
CECARRYIN => blk00000003_sig00000067,
|
7116 |
|
|
CEMULTCARRYIN => blk00000003_sig00000066,
|
7117 |
|
|
CLK => sig00000042,
|
7118 |
|
|
RSTA => blk00000003_sig00000066,
|
7119 |
|
|
RSTB => blk00000003_sig00000066,
|
7120 |
|
|
RSTC => blk00000003_sig00000066,
|
7121 |
|
|
RSTCTRL => blk00000003_sig00000066,
|
7122 |
|
|
RSTP => blk00000003_sig00000066,
|
7123 |
|
|
RSTM => blk00000003_sig00000066,
|
7124 |
|
|
RSTALLCARRYIN => blk00000003_sig00000066,
|
7125 |
|
|
CEALUMODE => blk00000003_sig00000067,
|
7126 |
|
|
RSTALUMODE => blk00000003_sig00000066,
|
7127 |
|
|
PATTERNBDETECT => NLW_blk00000003_blk00000096_PATTERNBDETECT_UNCONNECTED,
|
7128 |
|
|
PATTERNDETECT => NLW_blk00000003_blk00000096_PATTERNDETECT_UNCONNECTED,
|
7129 |
|
|
OVERFLOW => NLW_blk00000003_blk00000096_OVERFLOW_UNCONNECTED,
|
7130 |
|
|
UNDERFLOW => NLW_blk00000003_blk00000096_UNDERFLOW_UNCONNECTED,
|
7131 |
|
|
CARRYCASCIN => blk00000003_sig00000066,
|
7132 |
|
|
CARRYCASCOUT => NLW_blk00000003_blk00000096_CARRYCASCOUT_UNCONNECTED,
|
7133 |
|
|
MULTSIGNIN => blk00000003_sig00000066,
|
7134 |
|
|
MULTSIGNOUT => NLW_blk00000003_blk00000096_MULTSIGNOUT_UNCONNECTED,
|
7135 |
|
|
A(29) => blk00000003_sig00000066,
|
7136 |
|
|
A(28) => blk00000003_sig00000066,
|
7137 |
|
|
A(27) => blk00000003_sig00000066,
|
7138 |
|
|
A(26) => blk00000003_sig00000066,
|
7139 |
|
|
A(25) => blk00000003_sig00000066,
|
7140 |
|
|
A(24) => blk00000003_sig00000066,
|
7141 |
|
|
A(23) => blk00000003_sig00000172,
|
7142 |
|
|
A(22) => blk00000003_sig00000171,
|
7143 |
|
|
A(21) => blk00000003_sig0000017a,
|
7144 |
|
|
A(20) => blk00000003_sig00000179,
|
7145 |
|
|
A(19) => blk00000003_sig00000178,
|
7146 |
|
|
A(18) => blk00000003_sig00000177,
|
7147 |
|
|
A(17) => blk00000003_sig00000180,
|
7148 |
|
|
A(16) => blk00000003_sig0000017f,
|
7149 |
|
|
A(15) => blk00000003_sig0000017e,
|
7150 |
|
|
A(14) => blk00000003_sig0000017d,
|
7151 |
|
|
A(13) => blk00000003_sig00000186,
|
7152 |
|
|
A(12) => blk00000003_sig00000185,
|
7153 |
|
|
A(11) => blk00000003_sig00000184,
|
7154 |
|
|
A(10) => blk00000003_sig00000183,
|
7155 |
|
|
A(9) => blk00000003_sig00000194,
|
7156 |
|
|
A(8) => blk00000003_sig00000195,
|
7157 |
|
|
A(7) => blk00000003_sig00000196,
|
7158 |
|
|
A(6) => blk00000003_sig00000197,
|
7159 |
|
|
A(5) => blk00000003_sig00000198,
|
7160 |
|
|
A(4) => blk00000003_sig00000199,
|
7161 |
|
|
A(3) => blk00000003_sig0000019a,
|
7162 |
|
|
A(2) => blk00000003_sig0000019b,
|
7163 |
|
|
A(1) => blk00000003_sig0000019c,
|
7164 |
|
|
A(0) => blk00000003_sig0000019d,
|
7165 |
|
|
PCIN(47) => blk00000003_sig00000066,
|
7166 |
|
|
PCIN(46) => blk00000003_sig00000066,
|
7167 |
|
|
PCIN(45) => blk00000003_sig00000066,
|
7168 |
|
|
PCIN(44) => blk00000003_sig00000066,
|
7169 |
|
|
PCIN(43) => blk00000003_sig00000066,
|
7170 |
|
|
PCIN(42) => blk00000003_sig00000066,
|
7171 |
|
|
PCIN(41) => blk00000003_sig00000066,
|
7172 |
|
|
PCIN(40) => blk00000003_sig00000066,
|
7173 |
|
|
PCIN(39) => blk00000003_sig00000066,
|
7174 |
|
|
PCIN(38) => blk00000003_sig00000066,
|
7175 |
|
|
PCIN(37) => blk00000003_sig00000066,
|
7176 |
|
|
PCIN(36) => blk00000003_sig00000066,
|
7177 |
|
|
PCIN(35) => blk00000003_sig00000066,
|
7178 |
|
|
PCIN(34) => blk00000003_sig00000066,
|
7179 |
|
|
PCIN(33) => blk00000003_sig00000066,
|
7180 |
|
|
PCIN(32) => blk00000003_sig00000066,
|
7181 |
|
|
PCIN(31) => blk00000003_sig00000066,
|
7182 |
|
|
PCIN(30) => blk00000003_sig00000066,
|
7183 |
|
|
PCIN(29) => blk00000003_sig00000066,
|
7184 |
|
|
PCIN(28) => blk00000003_sig00000066,
|
7185 |
|
|
PCIN(27) => blk00000003_sig00000066,
|
7186 |
|
|
PCIN(26) => blk00000003_sig00000066,
|
7187 |
|
|
PCIN(25) => blk00000003_sig00000066,
|
7188 |
|
|
PCIN(24) => blk00000003_sig00000066,
|
7189 |
|
|
PCIN(23) => blk00000003_sig00000066,
|
7190 |
|
|
PCIN(22) => blk00000003_sig00000066,
|
7191 |
|
|
PCIN(21) => blk00000003_sig00000066,
|
7192 |
|
|
PCIN(20) => blk00000003_sig00000066,
|
7193 |
|
|
PCIN(19) => blk00000003_sig00000066,
|
7194 |
|
|
PCIN(18) => blk00000003_sig00000066,
|
7195 |
|
|
PCIN(17) => blk00000003_sig00000066,
|
7196 |
|
|
PCIN(16) => blk00000003_sig00000066,
|
7197 |
|
|
PCIN(15) => blk00000003_sig00000066,
|
7198 |
|
|
PCIN(14) => blk00000003_sig00000066,
|
7199 |
|
|
PCIN(13) => blk00000003_sig00000066,
|
7200 |
|
|
PCIN(12) => blk00000003_sig00000066,
|
7201 |
|
|
PCIN(11) => blk00000003_sig00000066,
|
7202 |
|
|
PCIN(10) => blk00000003_sig00000066,
|
7203 |
|
|
PCIN(9) => blk00000003_sig00000066,
|
7204 |
|
|
PCIN(8) => blk00000003_sig00000066,
|
7205 |
|
|
PCIN(7) => blk00000003_sig00000066,
|
7206 |
|
|
PCIN(6) => blk00000003_sig00000066,
|
7207 |
|
|
PCIN(5) => blk00000003_sig00000066,
|
7208 |
|
|
PCIN(4) => blk00000003_sig00000066,
|
7209 |
|
|
PCIN(3) => blk00000003_sig00000066,
|
7210 |
|
|
PCIN(2) => blk00000003_sig00000066,
|
7211 |
|
|
PCIN(1) => blk00000003_sig00000066,
|
7212 |
|
|
PCIN(0) => blk00000003_sig00000066,
|
7213 |
|
|
B(17) => blk00000003_sig00000066,
|
7214 |
|
|
B(16) => blk00000003_sig00000066,
|
7215 |
|
|
B(15) => blk00000003_sig00000140,
|
7216 |
|
|
B(14) => blk00000003_sig00000142,
|
7217 |
|
|
B(13) => blk00000003_sig00000144,
|
7218 |
|
|
B(12) => blk00000003_sig00000146,
|
7219 |
|
|
B(11) => blk00000003_sig00000148,
|
7220 |
|
|
B(10) => blk00000003_sig0000014a,
|
7221 |
|
|
B(9) => blk00000003_sig0000014c,
|
7222 |
|
|
B(8) => blk00000003_sig0000014e,
|
7223 |
|
|
B(7) => blk00000003_sig00000150,
|
7224 |
|
|
B(6) => blk00000003_sig00000152,
|
7225 |
|
|
B(5) => blk00000003_sig00000154,
|
7226 |
|
|
B(4) => blk00000003_sig00000156,
|
7227 |
|
|
B(3) => blk00000003_sig00000158,
|
7228 |
|
|
B(2) => blk00000003_sig0000015a,
|
7229 |
|
|
B(1) => blk00000003_sig0000015c,
|
7230 |
|
|
B(0) => blk00000003_sig0000015e,
|
7231 |
|
|
C(47) => blk00000003_sig00000066,
|
7232 |
|
|
C(46) => blk00000003_sig00000066,
|
7233 |
|
|
C(45) => blk00000003_sig00000066,
|
7234 |
|
|
C(44) => blk00000003_sig00000066,
|
7235 |
|
|
C(43) => blk00000003_sig00000066,
|
7236 |
|
|
C(42) => blk00000003_sig00000066,
|
7237 |
|
|
C(41) => blk00000003_sig00000066,
|
7238 |
|
|
C(40) => blk00000003_sig00000066,
|
7239 |
|
|
C(39) => blk00000003_sig00000066,
|
7240 |
|
|
C(38) => blk00000003_sig00000066,
|
7241 |
|
|
C(37) => blk00000003_sig00000066,
|
7242 |
|
|
C(36) => blk00000003_sig00000066,
|
7243 |
|
|
C(35) => blk00000003_sig00000066,
|
7244 |
|
|
C(34) => blk00000003_sig0000019e,
|
7245 |
|
|
C(33) => blk00000003_sig0000019f,
|
7246 |
|
|
C(32) => blk00000003_sig000001a0,
|
7247 |
|
|
C(31) => blk00000003_sig000001a1,
|
7248 |
|
|
C(30) => blk00000003_sig000001a2,
|
7249 |
|
|
C(29) => blk00000003_sig000001a3,
|
7250 |
|
|
C(28) => blk00000003_sig000001a4,
|
7251 |
|
|
C(27) => blk00000003_sig000001a5,
|
7252 |
|
|
C(26) => blk00000003_sig00000067,
|
7253 |
|
|
C(25) => blk00000003_sig000001a6,
|
7254 |
|
|
C(24) => blk00000003_sig000001a7,
|
7255 |
|
|
C(23) => blk00000003_sig00000066,
|
7256 |
|
|
C(22) => blk00000003_sig00000066,
|
7257 |
|
|
C(21) => blk00000003_sig00000066,
|
7258 |
|
|
C(20) => blk00000003_sig00000066,
|
7259 |
|
|
C(19) => blk00000003_sig00000066,
|
7260 |
|
|
C(18) => blk00000003_sig00000066,
|
7261 |
|
|
C(17) => blk00000003_sig00000066,
|
7262 |
|
|
C(16) => blk00000003_sig00000066,
|
7263 |
|
|
C(15) => blk00000003_sig00000066,
|
7264 |
|
|
C(14) => blk00000003_sig00000066,
|
7265 |
|
|
C(13) => blk00000003_sig00000066,
|
7266 |
|
|
C(12) => blk00000003_sig00000066,
|
7267 |
|
|
C(11) => blk00000003_sig00000066,
|
7268 |
|
|
C(10) => blk00000003_sig00000066,
|
7269 |
|
|
C(9) => blk00000003_sig00000066,
|
7270 |
|
|
C(8) => blk00000003_sig00000066,
|
7271 |
|
|
C(7) => blk00000003_sig00000066,
|
7272 |
|
|
C(6) => blk00000003_sig00000066,
|
7273 |
|
|
C(5) => blk00000003_sig00000066,
|
7274 |
|
|
C(4) => blk00000003_sig00000066,
|
7275 |
|
|
C(3) => blk00000003_sig00000066,
|
7276 |
|
|
C(2) => blk00000003_sig000001a8,
|
7277 |
|
|
C(1) => blk00000003_sig00000066,
|
7278 |
|
|
C(0) => blk00000003_sig00000066,
|
7279 |
|
|
CARRYINSEL(2) => blk00000003_sig00000066,
|
7280 |
|
|
CARRYINSEL(1) => blk00000003_sig00000066,
|
7281 |
|
|
CARRYINSEL(0) => blk00000003_sig00000066,
|
7282 |
|
|
OPMODE(6) => blk00000003_sig00000066,
|
7283 |
|
|
OPMODE(5) => blk00000003_sig00000067,
|
7284 |
|
|
OPMODE(4) => blk00000003_sig00000067,
|
7285 |
|
|
OPMODE(3) => blk00000003_sig00000066,
|
7286 |
|
|
OPMODE(2) => blk00000003_sig00000067,
|
7287 |
|
|
OPMODE(1) => blk00000003_sig00000066,
|
7288 |
|
|
OPMODE(0) => blk00000003_sig00000067,
|
7289 |
|
|
BCIN(17) => blk00000003_sig00000066,
|
7290 |
|
|
BCIN(16) => blk00000003_sig00000066,
|
7291 |
|
|
BCIN(15) => blk00000003_sig00000066,
|
7292 |
|
|
BCIN(14) => blk00000003_sig00000066,
|
7293 |
|
|
BCIN(13) => blk00000003_sig00000066,
|
7294 |
|
|
BCIN(12) => blk00000003_sig00000066,
|
7295 |
|
|
BCIN(11) => blk00000003_sig00000066,
|
7296 |
|
|
BCIN(10) => blk00000003_sig00000066,
|
7297 |
|
|
BCIN(9) => blk00000003_sig00000066,
|
7298 |
|
|
BCIN(8) => blk00000003_sig00000066,
|
7299 |
|
|
BCIN(7) => blk00000003_sig00000066,
|
7300 |
|
|
BCIN(6) => blk00000003_sig00000066,
|
7301 |
|
|
BCIN(5) => blk00000003_sig00000066,
|
7302 |
|
|
BCIN(4) => blk00000003_sig00000066,
|
7303 |
|
|
BCIN(3) => blk00000003_sig00000066,
|
7304 |
|
|
BCIN(2) => blk00000003_sig00000066,
|
7305 |
|
|
BCIN(1) => blk00000003_sig00000066,
|
7306 |
|
|
BCIN(0) => blk00000003_sig00000066,
|
7307 |
|
|
ALUMODE(3) => blk00000003_sig00000066,
|
7308 |
|
|
ALUMODE(2) => blk00000003_sig00000066,
|
7309 |
|
|
ALUMODE(1) => blk00000003_sig00000066,
|
7310 |
|
|
ALUMODE(0) => blk00000003_sig00000066,
|
7311 |
|
|
PCOUT(47) => NLW_blk00000003_blk00000096_PCOUT_47_UNCONNECTED,
|
7312 |
|
|
PCOUT(46) => NLW_blk00000003_blk00000096_PCOUT_46_UNCONNECTED,
|
7313 |
|
|
PCOUT(45) => NLW_blk00000003_blk00000096_PCOUT_45_UNCONNECTED,
|
7314 |
|
|
PCOUT(44) => NLW_blk00000003_blk00000096_PCOUT_44_UNCONNECTED,
|
7315 |
|
|
PCOUT(43) => NLW_blk00000003_blk00000096_PCOUT_43_UNCONNECTED,
|
7316 |
|
|
PCOUT(42) => NLW_blk00000003_blk00000096_PCOUT_42_UNCONNECTED,
|
7317 |
|
|
PCOUT(41) => NLW_blk00000003_blk00000096_PCOUT_41_UNCONNECTED,
|
7318 |
|
|
PCOUT(40) => NLW_blk00000003_blk00000096_PCOUT_40_UNCONNECTED,
|
7319 |
|
|
PCOUT(39) => NLW_blk00000003_blk00000096_PCOUT_39_UNCONNECTED,
|
7320 |
|
|
PCOUT(38) => NLW_blk00000003_blk00000096_PCOUT_38_UNCONNECTED,
|
7321 |
|
|
PCOUT(37) => NLW_blk00000003_blk00000096_PCOUT_37_UNCONNECTED,
|
7322 |
|
|
PCOUT(36) => NLW_blk00000003_blk00000096_PCOUT_36_UNCONNECTED,
|
7323 |
|
|
PCOUT(35) => NLW_blk00000003_blk00000096_PCOUT_35_UNCONNECTED,
|
7324 |
|
|
PCOUT(34) => NLW_blk00000003_blk00000096_PCOUT_34_UNCONNECTED,
|
7325 |
|
|
PCOUT(33) => NLW_blk00000003_blk00000096_PCOUT_33_UNCONNECTED,
|
7326 |
|
|
PCOUT(32) => NLW_blk00000003_blk00000096_PCOUT_32_UNCONNECTED,
|
7327 |
|
|
PCOUT(31) => NLW_blk00000003_blk00000096_PCOUT_31_UNCONNECTED,
|
7328 |
|
|
PCOUT(30) => NLW_blk00000003_blk00000096_PCOUT_30_UNCONNECTED,
|
7329 |
|
|
PCOUT(29) => NLW_blk00000003_blk00000096_PCOUT_29_UNCONNECTED,
|
7330 |
|
|
PCOUT(28) => NLW_blk00000003_blk00000096_PCOUT_28_UNCONNECTED,
|
7331 |
|
|
PCOUT(27) => NLW_blk00000003_blk00000096_PCOUT_27_UNCONNECTED,
|
7332 |
|
|
PCOUT(26) => NLW_blk00000003_blk00000096_PCOUT_26_UNCONNECTED,
|
7333 |
|
|
PCOUT(25) => NLW_blk00000003_blk00000096_PCOUT_25_UNCONNECTED,
|
7334 |
|
|
PCOUT(24) => NLW_blk00000003_blk00000096_PCOUT_24_UNCONNECTED,
|
7335 |
|
|
PCOUT(23) => NLW_blk00000003_blk00000096_PCOUT_23_UNCONNECTED,
|
7336 |
|
|
PCOUT(22) => NLW_blk00000003_blk00000096_PCOUT_22_UNCONNECTED,
|
7337 |
|
|
PCOUT(21) => NLW_blk00000003_blk00000096_PCOUT_21_UNCONNECTED,
|
7338 |
|
|
PCOUT(20) => NLW_blk00000003_blk00000096_PCOUT_20_UNCONNECTED,
|
7339 |
|
|
PCOUT(19) => NLW_blk00000003_blk00000096_PCOUT_19_UNCONNECTED,
|
7340 |
|
|
PCOUT(18) => NLW_blk00000003_blk00000096_PCOUT_18_UNCONNECTED,
|
7341 |
|
|
PCOUT(17) => NLW_blk00000003_blk00000096_PCOUT_17_UNCONNECTED,
|
7342 |
|
|
PCOUT(16) => NLW_blk00000003_blk00000096_PCOUT_16_UNCONNECTED,
|
7343 |
|
|
PCOUT(15) => NLW_blk00000003_blk00000096_PCOUT_15_UNCONNECTED,
|
7344 |
|
|
PCOUT(14) => NLW_blk00000003_blk00000096_PCOUT_14_UNCONNECTED,
|
7345 |
|
|
PCOUT(13) => NLW_blk00000003_blk00000096_PCOUT_13_UNCONNECTED,
|
7346 |
|
|
PCOUT(12) => NLW_blk00000003_blk00000096_PCOUT_12_UNCONNECTED,
|
7347 |
|
|
PCOUT(11) => NLW_blk00000003_blk00000096_PCOUT_11_UNCONNECTED,
|
7348 |
|
|
PCOUT(10) => NLW_blk00000003_blk00000096_PCOUT_10_UNCONNECTED,
|
7349 |
|
|
PCOUT(9) => NLW_blk00000003_blk00000096_PCOUT_9_UNCONNECTED,
|
7350 |
|
|
PCOUT(8) => NLW_blk00000003_blk00000096_PCOUT_8_UNCONNECTED,
|
7351 |
|
|
PCOUT(7) => NLW_blk00000003_blk00000096_PCOUT_7_UNCONNECTED,
|
7352 |
|
|
PCOUT(6) => NLW_blk00000003_blk00000096_PCOUT_6_UNCONNECTED,
|
7353 |
|
|
PCOUT(5) => NLW_blk00000003_blk00000096_PCOUT_5_UNCONNECTED,
|
7354 |
|
|
PCOUT(4) => NLW_blk00000003_blk00000096_PCOUT_4_UNCONNECTED,
|
7355 |
|
|
PCOUT(3) => NLW_blk00000003_blk00000096_PCOUT_3_UNCONNECTED,
|
7356 |
|
|
PCOUT(2) => NLW_blk00000003_blk00000096_PCOUT_2_UNCONNECTED,
|
7357 |
|
|
PCOUT(1) => NLW_blk00000003_blk00000096_PCOUT_1_UNCONNECTED,
|
7358 |
|
|
PCOUT(0) => NLW_blk00000003_blk00000096_PCOUT_0_UNCONNECTED,
|
7359 |
|
|
P(47) => NLW_blk00000003_blk00000096_P_47_UNCONNECTED,
|
7360 |
|
|
P(46) => NLW_blk00000003_blk00000096_P_46_UNCONNECTED,
|
7361 |
|
|
P(45) => NLW_blk00000003_blk00000096_P_45_UNCONNECTED,
|
7362 |
|
|
P(44) => NLW_blk00000003_blk00000096_P_44_UNCONNECTED,
|
7363 |
|
|
P(43) => NLW_blk00000003_blk00000096_P_43_UNCONNECTED,
|
7364 |
|
|
P(42) => NLW_blk00000003_blk00000096_P_42_UNCONNECTED,
|
7365 |
|
|
P(41) => NLW_blk00000003_blk00000096_P_41_UNCONNECTED,
|
7366 |
|
|
P(40) => NLW_blk00000003_blk00000096_P_40_UNCONNECTED,
|
7367 |
|
|
P(39) => NLW_blk00000003_blk00000096_P_39_UNCONNECTED,
|
7368 |
|
|
P(38) => NLW_blk00000003_blk00000096_P_38_UNCONNECTED,
|
7369 |
|
|
P(37) => NLW_blk00000003_blk00000096_P_37_UNCONNECTED,
|
7370 |
|
|
P(36) => NLW_blk00000003_blk00000096_P_36_UNCONNECTED,
|
7371 |
|
|
P(35) => NLW_blk00000003_blk00000096_P_35_UNCONNECTED,
|
7372 |
|
|
P(34) => blk00000003_sig00000125,
|
7373 |
|
|
P(33) => blk00000003_sig00000128,
|
7374 |
|
|
P(32) => blk00000003_sig00000129,
|
7375 |
|
|
P(31) => blk00000003_sig0000012a,
|
7376 |
|
|
P(30) => blk00000003_sig0000012b,
|
7377 |
|
|
P(29) => blk00000003_sig0000012c,
|
7378 |
|
|
P(28) => blk00000003_sig0000012d,
|
7379 |
|
|
P(27) => blk00000003_sig0000012e,
|
7380 |
|
|
P(26) => NLW_blk00000003_blk00000096_P_26_UNCONNECTED,
|
7381 |
|
|
P(25) => NLW_blk00000003_blk00000096_P_25_UNCONNECTED,
|
7382 |
|
|
P(24) => blk00000003_sig0000011a,
|
7383 |
|
|
P(23) => blk00000003_sig0000011d,
|
7384 |
|
|
P(22) => blk00000003_sig0000011f,
|
7385 |
|
|
P(21) => blk00000003_sig00000116,
|
7386 |
|
|
P(20) => blk00000003_sig00000117,
|
7387 |
|
|
P(19) => blk00000003_sig00000118,
|
7388 |
|
|
P(18) => blk00000003_sig00000119,
|
7389 |
|
|
P(17) => blk00000003_sig0000011e,
|
7390 |
|
|
P(16) => blk00000003_sig00000120,
|
7391 |
|
|
P(15) => blk00000003_sig00000122,
|
7392 |
|
|
P(14) => blk00000003_sig00000121,
|
7393 |
|
|
P(13) => blk00000003_sig00000123,
|
7394 |
|
|
P(12) => blk00000003_sig00000124,
|
7395 |
|
|
P(11) => blk00000003_sig0000010a,
|
7396 |
|
|
P(10) => blk00000003_sig0000010c,
|
7397 |
|
|
P(9) => blk00000003_sig0000010e,
|
7398 |
|
|
P(8) => blk00000003_sig0000010f,
|
7399 |
|
|
P(7) => blk00000003_sig00000110,
|
7400 |
|
|
P(6) => blk00000003_sig00000111,
|
7401 |
|
|
P(5) => blk00000003_sig00000114,
|
7402 |
|
|
P(4) => blk00000003_sig00000112,
|
7403 |
|
|
P(3) => blk00000003_sig00000113,
|
7404 |
|
|
P(2) => blk00000003_sig00000115,
|
7405 |
|
|
P(1) => NLW_blk00000003_blk00000096_P_1_UNCONNECTED,
|
7406 |
|
|
P(0) => NLW_blk00000003_blk00000096_P_0_UNCONNECTED,
|
7407 |
|
|
BCOUT(17) => NLW_blk00000003_blk00000096_BCOUT_17_UNCONNECTED,
|
7408 |
|
|
BCOUT(16) => NLW_blk00000003_blk00000096_BCOUT_16_UNCONNECTED,
|
7409 |
|
|
BCOUT(15) => NLW_blk00000003_blk00000096_BCOUT_15_UNCONNECTED,
|
7410 |
|
|
BCOUT(14) => NLW_blk00000003_blk00000096_BCOUT_14_UNCONNECTED,
|
7411 |
|
|
BCOUT(13) => NLW_blk00000003_blk00000096_BCOUT_13_UNCONNECTED,
|
7412 |
|
|
BCOUT(12) => NLW_blk00000003_blk00000096_BCOUT_12_UNCONNECTED,
|
7413 |
|
|
BCOUT(11) => NLW_blk00000003_blk00000096_BCOUT_11_UNCONNECTED,
|
7414 |
|
|
BCOUT(10) => NLW_blk00000003_blk00000096_BCOUT_10_UNCONNECTED,
|
7415 |
|
|
BCOUT(9) => NLW_blk00000003_blk00000096_BCOUT_9_UNCONNECTED,
|
7416 |
|
|
BCOUT(8) => NLW_blk00000003_blk00000096_BCOUT_8_UNCONNECTED,
|
7417 |
|
|
BCOUT(7) => NLW_blk00000003_blk00000096_BCOUT_7_UNCONNECTED,
|
7418 |
|
|
BCOUT(6) => NLW_blk00000003_blk00000096_BCOUT_6_UNCONNECTED,
|
7419 |
|
|
BCOUT(5) => NLW_blk00000003_blk00000096_BCOUT_5_UNCONNECTED,
|
7420 |
|
|
BCOUT(4) => NLW_blk00000003_blk00000096_BCOUT_4_UNCONNECTED,
|
7421 |
|
|
BCOUT(3) => NLW_blk00000003_blk00000096_BCOUT_3_UNCONNECTED,
|
7422 |
|
|
BCOUT(2) => NLW_blk00000003_blk00000096_BCOUT_2_UNCONNECTED,
|
7423 |
|
|
BCOUT(1) => NLW_blk00000003_blk00000096_BCOUT_1_UNCONNECTED,
|
7424 |
|
|
BCOUT(0) => NLW_blk00000003_blk00000096_BCOUT_0_UNCONNECTED,
|
7425 |
|
|
ACIN(29) => blk00000003_sig00000066,
|
7426 |
|
|
ACIN(28) => blk00000003_sig00000066,
|
7427 |
|
|
ACIN(27) => blk00000003_sig00000066,
|
7428 |
|
|
ACIN(26) => blk00000003_sig00000066,
|
7429 |
|
|
ACIN(25) => blk00000003_sig00000066,
|
7430 |
|
|
ACIN(24) => blk00000003_sig00000066,
|
7431 |
|
|
ACIN(23) => blk00000003_sig00000066,
|
7432 |
|
|
ACIN(22) => blk00000003_sig00000066,
|
7433 |
|
|
ACIN(21) => blk00000003_sig00000066,
|
7434 |
|
|
ACIN(20) => blk00000003_sig00000066,
|
7435 |
|
|
ACIN(19) => blk00000003_sig00000066,
|
7436 |
|
|
ACIN(18) => blk00000003_sig00000066,
|
7437 |
|
|
ACIN(17) => blk00000003_sig00000066,
|
7438 |
|
|
ACIN(16) => blk00000003_sig00000066,
|
7439 |
|
|
ACIN(15) => blk00000003_sig00000066,
|
7440 |
|
|
ACIN(14) => blk00000003_sig00000066,
|
7441 |
|
|
ACIN(13) => blk00000003_sig00000066,
|
7442 |
|
|
ACIN(12) => blk00000003_sig00000066,
|
7443 |
|
|
ACIN(11) => blk00000003_sig00000066,
|
7444 |
|
|
ACIN(10) => blk00000003_sig00000066,
|
7445 |
|
|
ACIN(9) => blk00000003_sig00000066,
|
7446 |
|
|
ACIN(8) => blk00000003_sig00000066,
|
7447 |
|
|
ACIN(7) => blk00000003_sig00000066,
|
7448 |
|
|
ACIN(6) => blk00000003_sig00000066,
|
7449 |
|
|
ACIN(5) => blk00000003_sig00000066,
|
7450 |
|
|
ACIN(4) => blk00000003_sig00000066,
|
7451 |
|
|
ACIN(3) => blk00000003_sig00000066,
|
7452 |
|
|
ACIN(2) => blk00000003_sig00000066,
|
7453 |
|
|
ACIN(1) => blk00000003_sig00000066,
|
7454 |
|
|
ACIN(0) => blk00000003_sig00000066,
|
7455 |
|
|
ACOUT(29) => NLW_blk00000003_blk00000096_ACOUT_29_UNCONNECTED,
|
7456 |
|
|
ACOUT(28) => NLW_blk00000003_blk00000096_ACOUT_28_UNCONNECTED,
|
7457 |
|
|
ACOUT(27) => NLW_blk00000003_blk00000096_ACOUT_27_UNCONNECTED,
|
7458 |
|
|
ACOUT(26) => NLW_blk00000003_blk00000096_ACOUT_26_UNCONNECTED,
|
7459 |
|
|
ACOUT(25) => NLW_blk00000003_blk00000096_ACOUT_25_UNCONNECTED,
|
7460 |
|
|
ACOUT(24) => NLW_blk00000003_blk00000096_ACOUT_24_UNCONNECTED,
|
7461 |
|
|
ACOUT(23) => NLW_blk00000003_blk00000096_ACOUT_23_UNCONNECTED,
|
7462 |
|
|
ACOUT(22) => NLW_blk00000003_blk00000096_ACOUT_22_UNCONNECTED,
|
7463 |
|
|
ACOUT(21) => NLW_blk00000003_blk00000096_ACOUT_21_UNCONNECTED,
|
7464 |
|
|
ACOUT(20) => NLW_blk00000003_blk00000096_ACOUT_20_UNCONNECTED,
|
7465 |
|
|
ACOUT(19) => NLW_blk00000003_blk00000096_ACOUT_19_UNCONNECTED,
|
7466 |
|
|
ACOUT(18) => NLW_blk00000003_blk00000096_ACOUT_18_UNCONNECTED,
|
7467 |
|
|
ACOUT(17) => NLW_blk00000003_blk00000096_ACOUT_17_UNCONNECTED,
|
7468 |
|
|
ACOUT(16) => NLW_blk00000003_blk00000096_ACOUT_16_UNCONNECTED,
|
7469 |
|
|
ACOUT(15) => NLW_blk00000003_blk00000096_ACOUT_15_UNCONNECTED,
|
7470 |
|
|
ACOUT(14) => NLW_blk00000003_blk00000096_ACOUT_14_UNCONNECTED,
|
7471 |
|
|
ACOUT(13) => NLW_blk00000003_blk00000096_ACOUT_13_UNCONNECTED,
|
7472 |
|
|
ACOUT(12) => NLW_blk00000003_blk00000096_ACOUT_12_UNCONNECTED,
|
7473 |
|
|
ACOUT(11) => NLW_blk00000003_blk00000096_ACOUT_11_UNCONNECTED,
|
7474 |
|
|
ACOUT(10) => NLW_blk00000003_blk00000096_ACOUT_10_UNCONNECTED,
|
7475 |
|
|
ACOUT(9) => NLW_blk00000003_blk00000096_ACOUT_9_UNCONNECTED,
|
7476 |
|
|
ACOUT(8) => NLW_blk00000003_blk00000096_ACOUT_8_UNCONNECTED,
|
7477 |
|
|
ACOUT(7) => NLW_blk00000003_blk00000096_ACOUT_7_UNCONNECTED,
|
7478 |
|
|
ACOUT(6) => NLW_blk00000003_blk00000096_ACOUT_6_UNCONNECTED,
|
7479 |
|
|
ACOUT(5) => NLW_blk00000003_blk00000096_ACOUT_5_UNCONNECTED,
|
7480 |
|
|
ACOUT(4) => NLW_blk00000003_blk00000096_ACOUT_4_UNCONNECTED,
|
7481 |
|
|
ACOUT(3) => NLW_blk00000003_blk00000096_ACOUT_3_UNCONNECTED,
|
7482 |
|
|
ACOUT(2) => NLW_blk00000003_blk00000096_ACOUT_2_UNCONNECTED,
|
7483 |
|
|
ACOUT(1) => NLW_blk00000003_blk00000096_ACOUT_1_UNCONNECTED,
|
7484 |
|
|
ACOUT(0) => NLW_blk00000003_blk00000096_ACOUT_0_UNCONNECTED,
|
7485 |
|
|
CARRYOUT(3) => NLW_blk00000003_blk00000096_CARRYOUT_3_UNCONNECTED,
|
7486 |
|
|
CARRYOUT(2) => NLW_blk00000003_blk00000096_CARRYOUT_2_UNCONNECTED,
|
7487 |
|
|
CARRYOUT(1) => NLW_blk00000003_blk00000096_CARRYOUT_1_UNCONNECTED,
|
7488 |
|
|
CARRYOUT(0) => NLW_blk00000003_blk00000096_CARRYOUT_0_UNCONNECTED
|
7489 |
|
|
);
|
7490 |
|
|
blk00000003_blk00000095 : FD
|
7491 |
|
|
generic map(
|
7492 |
|
|
INIT => '0'
|
7493 |
|
|
)
|
7494 |
|
|
port map (
|
7495 |
|
|
C => sig00000042,
|
7496 |
|
|
D => blk00000003_sig00000193,
|
7497 |
|
|
Q => blk00000003_sig0000017e
|
7498 |
|
|
);
|
7499 |
|
|
blk00000003_blk00000094 : FD
|
7500 |
|
|
generic map(
|
7501 |
|
|
INIT => '0'
|
7502 |
|
|
)
|
7503 |
|
|
port map (
|
7504 |
|
|
C => sig00000042,
|
7505 |
|
|
D => blk00000003_sig00000192,
|
7506 |
|
|
Q => blk00000003_sig0000017f
|
7507 |
|
|
);
|
7508 |
|
|
blk00000003_blk00000093 : FD
|
7509 |
|
|
generic map(
|
7510 |
|
|
INIT => '0'
|
7511 |
|
|
)
|
7512 |
|
|
port map (
|
7513 |
|
|
C => sig00000042,
|
7514 |
|
|
D => blk00000003_sig00000191,
|
7515 |
|
|
Q => blk00000003_sig00000180
|
7516 |
|
|
);
|
7517 |
|
|
blk00000003_blk00000092 : FD
|
7518 |
|
|
generic map(
|
7519 |
|
|
INIT => '0'
|
7520 |
|
|
)
|
7521 |
|
|
port map (
|
7522 |
|
|
C => sig00000042,
|
7523 |
|
|
D => blk00000003_sig00000190,
|
7524 |
|
|
Q => blk00000003_sig00000177
|
7525 |
|
|
);
|
7526 |
|
|
blk00000003_blk00000091 : FD
|
7527 |
|
|
generic map(
|
7528 |
|
|
INIT => '0'
|
7529 |
|
|
)
|
7530 |
|
|
port map (
|
7531 |
|
|
C => sig00000042,
|
7532 |
|
|
D => blk00000003_sig0000018f,
|
7533 |
|
|
Q => blk00000003_sig00000178
|
7534 |
|
|
);
|
7535 |
|
|
blk00000003_blk00000090 : FD
|
7536 |
|
|
generic map(
|
7537 |
|
|
INIT => '0'
|
7538 |
|
|
)
|
7539 |
|
|
port map (
|
7540 |
|
|
C => sig00000042,
|
7541 |
|
|
D => blk00000003_sig0000018e,
|
7542 |
|
|
Q => blk00000003_sig00000179
|
7543 |
|
|
);
|
7544 |
|
|
blk00000003_blk0000008f : FD
|
7545 |
|
|
generic map(
|
7546 |
|
|
INIT => '0'
|
7547 |
|
|
)
|
7548 |
|
|
port map (
|
7549 |
|
|
C => sig00000042,
|
7550 |
|
|
D => blk00000003_sig0000018d,
|
7551 |
|
|
Q => blk00000003_sig0000017a
|
7552 |
|
|
);
|
7553 |
|
|
blk00000003_blk0000008e : FD
|
7554 |
|
|
generic map(
|
7555 |
|
|
INIT => '0'
|
7556 |
|
|
)
|
7557 |
|
|
port map (
|
7558 |
|
|
C => sig00000042,
|
7559 |
|
|
D => blk00000003_sig0000018c,
|
7560 |
|
|
Q => blk00000003_sig00000171
|
7561 |
|
|
);
|
7562 |
|
|
blk00000003_blk0000008d : FD
|
7563 |
|
|
generic map(
|
7564 |
|
|
INIT => '0'
|
7565 |
|
|
)
|
7566 |
|
|
port map (
|
7567 |
|
|
C => sig00000042,
|
7568 |
|
|
D => blk00000003_sig0000018b,
|
7569 |
|
|
Q => blk00000003_sig00000172
|
7570 |
|
|
);
|
7571 |
|
|
blk00000003_blk0000008c : FD
|
7572 |
|
|
generic map(
|
7573 |
|
|
INIT => '0'
|
7574 |
|
|
)
|
7575 |
|
|
port map (
|
7576 |
|
|
C => sig00000042,
|
7577 |
|
|
D => blk00000003_sig0000018a,
|
7578 |
|
|
Q => blk00000003_sig00000173
|
7579 |
|
|
);
|
7580 |
|
|
blk00000003_blk0000008b : FD
|
7581 |
|
|
generic map(
|
7582 |
|
|
INIT => '0'
|
7583 |
|
|
)
|
7584 |
|
|
port map (
|
7585 |
|
|
C => sig00000042,
|
7586 |
|
|
D => blk00000003_sig00000189,
|
7587 |
|
|
Q => blk00000003_sig00000174
|
7588 |
|
|
);
|
7589 |
|
|
blk00000003_blk0000008a : LUT5
|
7590 |
|
|
generic map(
|
7591 |
|
|
INIT => X"000000FC"
|
7592 |
|
|
)
|
7593 |
|
|
port map (
|
7594 |
|
|
I0 => blk00000003_sig00000066,
|
7595 |
|
|
I1 => blk00000003_sig00000183,
|
7596 |
|
|
I2 => blk00000003_sig00000184,
|
7597 |
|
|
I3 => blk00000003_sig00000185,
|
7598 |
|
|
I4 => blk00000003_sig00000186,
|
7599 |
|
|
O => blk00000003_sig00000188
|
7600 |
|
|
);
|
7601 |
|
|
blk00000003_blk00000089 : LUT5
|
7602 |
|
|
generic map(
|
7603 |
|
|
INIT => X"0000FF0C"
|
7604 |
|
|
)
|
7605 |
|
|
port map (
|
7606 |
|
|
I0 => blk00000003_sig00000066,
|
7607 |
|
|
I1 => blk00000003_sig00000183,
|
7608 |
|
|
I2 => blk00000003_sig00000184,
|
7609 |
|
|
I3 => blk00000003_sig00000185,
|
7610 |
|
|
I4 => blk00000003_sig00000186,
|
7611 |
|
|
O => blk00000003_sig00000187
|
7612 |
|
|
);
|
7613 |
|
|
blk00000003_blk00000088 : LUT5
|
7614 |
|
|
generic map(
|
7615 |
|
|
INIT => X"000000FC"
|
7616 |
|
|
)
|
7617 |
|
|
port map (
|
7618 |
|
|
I0 => blk00000003_sig00000066,
|
7619 |
|
|
I1 => blk00000003_sig0000017d,
|
7620 |
|
|
I2 => blk00000003_sig0000017e,
|
7621 |
|
|
I3 => blk00000003_sig0000017f,
|
7622 |
|
|
I4 => blk00000003_sig00000180,
|
7623 |
|
|
O => blk00000003_sig00000182
|
7624 |
|
|
);
|
7625 |
|
|
blk00000003_blk00000087 : LUT5
|
7626 |
|
|
generic map(
|
7627 |
|
|
INIT => X"0000FF0C"
|
7628 |
|
|
)
|
7629 |
|
|
port map (
|
7630 |
|
|
I0 => blk00000003_sig00000066,
|
7631 |
|
|
I1 => blk00000003_sig0000017d,
|
7632 |
|
|
I2 => blk00000003_sig0000017e,
|
7633 |
|
|
I3 => blk00000003_sig0000017f,
|
7634 |
|
|
I4 => blk00000003_sig00000180,
|
7635 |
|
|
O => blk00000003_sig00000181
|
7636 |
|
|
);
|
7637 |
|
|
blk00000003_blk00000086 : LUT5
|
7638 |
|
|
generic map(
|
7639 |
|
|
INIT => X"000000FC"
|
7640 |
|
|
)
|
7641 |
|
|
port map (
|
7642 |
|
|
I0 => blk00000003_sig00000066,
|
7643 |
|
|
I1 => blk00000003_sig00000177,
|
7644 |
|
|
I2 => blk00000003_sig00000178,
|
7645 |
|
|
I3 => blk00000003_sig00000179,
|
7646 |
|
|
I4 => blk00000003_sig0000017a,
|
7647 |
|
|
O => blk00000003_sig0000017c
|
7648 |
|
|
);
|
7649 |
|
|
blk00000003_blk00000085 : LUT5
|
7650 |
|
|
generic map(
|
7651 |
|
|
INIT => X"0000FF0C"
|
7652 |
|
|
)
|
7653 |
|
|
port map (
|
7654 |
|
|
I0 => blk00000003_sig00000066,
|
7655 |
|
|
I1 => blk00000003_sig00000177,
|
7656 |
|
|
I2 => blk00000003_sig00000178,
|
7657 |
|
|
I3 => blk00000003_sig00000179,
|
7658 |
|
|
I4 => blk00000003_sig0000017a,
|
7659 |
|
|
O => blk00000003_sig0000017b
|
7660 |
|
|
);
|
7661 |
|
|
blk00000003_blk00000084 : LUT5
|
7662 |
|
|
generic map(
|
7663 |
|
|
INIT => X"000000FC"
|
7664 |
|
|
)
|
7665 |
|
|
port map (
|
7666 |
|
|
I0 => blk00000003_sig00000066,
|
7667 |
|
|
I1 => blk00000003_sig00000171,
|
7668 |
|
|
I2 => blk00000003_sig00000172,
|
7669 |
|
|
I3 => blk00000003_sig00000173,
|
7670 |
|
|
I4 => blk00000003_sig00000174,
|
7671 |
|
|
O => blk00000003_sig00000176
|
7672 |
|
|
);
|
7673 |
|
|
blk00000003_blk00000083 : LUT5
|
7674 |
|
|
generic map(
|
7675 |
|
|
INIT => X"0000FF0C"
|
7676 |
|
|
)
|
7677 |
|
|
port map (
|
7678 |
|
|
I0 => blk00000003_sig00000066,
|
7679 |
|
|
I1 => blk00000003_sig00000171,
|
7680 |
|
|
I2 => blk00000003_sig00000172,
|
7681 |
|
|
I3 => blk00000003_sig00000173,
|
7682 |
|
|
I4 => blk00000003_sig00000174,
|
7683 |
|
|
O => blk00000003_sig00000175
|
7684 |
|
|
);
|
7685 |
|
|
blk00000003_blk00000082 : MUXCY
|
7686 |
|
|
port map (
|
7687 |
|
|
CI => blk00000003_sig0000013b,
|
7688 |
|
|
DI => blk00000003_sig00000066,
|
7689 |
|
|
S => blk00000003_sig00000170,
|
7690 |
|
|
O => blk00000003_sig0000013d
|
7691 |
|
|
);
|
7692 |
|
|
blk00000003_blk00000081 : MUXCY
|
7693 |
|
|
port map (
|
7694 |
|
|
CI => blk00000003_sig00000139,
|
7695 |
|
|
DI => blk00000003_sig00000066,
|
7696 |
|
|
S => blk00000003_sig0000016f,
|
7697 |
|
|
O => blk00000003_sig0000013b
|
7698 |
|
|
);
|
7699 |
|
|
blk00000003_blk00000080 : MUXCY
|
7700 |
|
|
port map (
|
7701 |
|
|
CI => blk00000003_sig00000137,
|
7702 |
|
|
DI => blk00000003_sig00000066,
|
7703 |
|
|
S => blk00000003_sig0000016e,
|
7704 |
|
|
O => blk00000003_sig00000139
|
7705 |
|
|
);
|
7706 |
|
|
blk00000003_blk0000007f : MUXCY
|
7707 |
|
|
port map (
|
7708 |
|
|
CI => blk00000003_sig00000135,
|
7709 |
|
|
DI => blk00000003_sig00000066,
|
7710 |
|
|
S => blk00000003_sig0000016d,
|
7711 |
|
|
O => blk00000003_sig00000137
|
7712 |
|
|
);
|
7713 |
|
|
blk00000003_blk0000007e : MUXCY
|
7714 |
|
|
port map (
|
7715 |
|
|
CI => blk00000003_sig00000133,
|
7716 |
|
|
DI => blk00000003_sig00000066,
|
7717 |
|
|
S => blk00000003_sig0000016c,
|
7718 |
|
|
O => blk00000003_sig00000135
|
7719 |
|
|
);
|
7720 |
|
|
blk00000003_blk0000007d : MUXCY
|
7721 |
|
|
port map (
|
7722 |
|
|
CI => blk00000003_sig00000131,
|
7723 |
|
|
DI => blk00000003_sig00000066,
|
7724 |
|
|
S => blk00000003_sig0000016b,
|
7725 |
|
|
O => blk00000003_sig00000133
|
7726 |
|
|
);
|
7727 |
|
|
blk00000003_blk0000007c : MUXCY
|
7728 |
|
|
port map (
|
7729 |
|
|
CI => blk00000003_sig0000012f,
|
7730 |
|
|
DI => blk00000003_sig00000066,
|
7731 |
|
|
S => blk00000003_sig0000016a,
|
7732 |
|
|
O => blk00000003_sig00000131
|
7733 |
|
|
);
|
7734 |
|
|
blk00000003_blk0000007b : MUXCY
|
7735 |
|
|
port map (
|
7736 |
|
|
CI => blk00000003_sig00000067,
|
7737 |
|
|
DI => blk00000003_sig00000066,
|
7738 |
|
|
S => blk00000003_sig00000169,
|
7739 |
|
|
O => blk00000003_sig0000012f
|
7740 |
|
|
);
|
7741 |
|
|
blk00000003_blk0000007a : FD
|
7742 |
|
|
generic map(
|
7743 |
|
|
INIT => '0'
|
7744 |
|
|
)
|
7745 |
|
|
port map (
|
7746 |
|
|
C => sig00000042,
|
7747 |
|
|
D => blk00000003_sig00000167,
|
7748 |
|
|
Q => blk00000003_sig00000168
|
7749 |
|
|
);
|
7750 |
|
|
blk00000003_blk00000079 : FD
|
7751 |
|
|
generic map(
|
7752 |
|
|
INIT => '0'
|
7753 |
|
|
)
|
7754 |
|
|
port map (
|
7755 |
|
|
C => sig00000042,
|
7756 |
|
|
D => blk00000003_sig00000165,
|
7757 |
|
|
Q => blk00000003_sig00000166
|
7758 |
|
|
);
|
7759 |
|
|
blk00000003_blk00000078 : FD
|
7760 |
|
|
generic map(
|
7761 |
|
|
INIT => '0'
|
7762 |
|
|
)
|
7763 |
|
|
port map (
|
7764 |
|
|
C => sig00000042,
|
7765 |
|
|
D => blk00000003_sig00000163,
|
7766 |
|
|
Q => blk00000003_sig00000164
|
7767 |
|
|
);
|
7768 |
|
|
blk00000003_blk00000077 : FD
|
7769 |
|
|
generic map(
|
7770 |
|
|
INIT => '0'
|
7771 |
|
|
)
|
7772 |
|
|
port map (
|
7773 |
|
|
C => sig00000042,
|
7774 |
|
|
D => blk00000003_sig00000136,
|
7775 |
|
|
Q => blk00000003_sig00000162
|
7776 |
|
|
);
|
7777 |
|
|
blk00000003_blk00000076 : FD
|
7778 |
|
|
generic map(
|
7779 |
|
|
INIT => '0'
|
7780 |
|
|
)
|
7781 |
|
|
port map (
|
7782 |
|
|
C => sig00000042,
|
7783 |
|
|
D => blk00000003_sig00000160,
|
7784 |
|
|
Q => blk00000003_sig00000161
|
7785 |
|
|
);
|
7786 |
|
|
blk00000003_blk00000075 : FDE
|
7787 |
|
|
generic map(
|
7788 |
|
|
INIT => '0'
|
7789 |
|
|
)
|
7790 |
|
|
port map (
|
7791 |
|
|
C => sig00000042,
|
7792 |
|
|
CE => blk00000003_sig00000067,
|
7793 |
|
|
D => blk00000003_sig0000015f,
|
7794 |
|
|
Q => blk00000003_sig00000160
|
7795 |
|
|
);
|
7796 |
|
|
blk00000003_blk00000074 : FDE
|
7797 |
|
|
generic map(
|
7798 |
|
|
INIT => '0'
|
7799 |
|
|
)
|
7800 |
|
|
port map (
|
7801 |
|
|
C => sig00000042,
|
7802 |
|
|
CE => blk00000003_sig00000067,
|
7803 |
|
|
D => blk00000003_sig0000015d,
|
7804 |
|
|
Q => blk00000003_sig0000015e
|
7805 |
|
|
);
|
7806 |
|
|
blk00000003_blk00000073 : FDE
|
7807 |
|
|
generic map(
|
7808 |
|
|
INIT => '0'
|
7809 |
|
|
)
|
7810 |
|
|
port map (
|
7811 |
|
|
C => sig00000042,
|
7812 |
|
|
CE => blk00000003_sig00000067,
|
7813 |
|
|
D => blk00000003_sig0000015b,
|
7814 |
|
|
Q => blk00000003_sig0000015c
|
7815 |
|
|
);
|
7816 |
|
|
blk00000003_blk00000072 : FDE
|
7817 |
|
|
generic map(
|
7818 |
|
|
INIT => '0'
|
7819 |
|
|
)
|
7820 |
|
|
port map (
|
7821 |
|
|
C => sig00000042,
|
7822 |
|
|
CE => blk00000003_sig00000067,
|
7823 |
|
|
D => blk00000003_sig00000159,
|
7824 |
|
|
Q => blk00000003_sig0000015a
|
7825 |
|
|
);
|
7826 |
|
|
blk00000003_blk00000071 : FDE
|
7827 |
|
|
generic map(
|
7828 |
|
|
INIT => '0'
|
7829 |
|
|
)
|
7830 |
|
|
port map (
|
7831 |
|
|
C => sig00000042,
|
7832 |
|
|
CE => blk00000003_sig00000067,
|
7833 |
|
|
D => blk00000003_sig00000157,
|
7834 |
|
|
Q => blk00000003_sig00000158
|
7835 |
|
|
);
|
7836 |
|
|
blk00000003_blk00000070 : FDE
|
7837 |
|
|
generic map(
|
7838 |
|
|
INIT => '0'
|
7839 |
|
|
)
|
7840 |
|
|
port map (
|
7841 |
|
|
C => sig00000042,
|
7842 |
|
|
CE => blk00000003_sig00000067,
|
7843 |
|
|
D => blk00000003_sig00000155,
|
7844 |
|
|
Q => blk00000003_sig00000156
|
7845 |
|
|
);
|
7846 |
|
|
blk00000003_blk0000006f : FDE
|
7847 |
|
|
generic map(
|
7848 |
|
|
INIT => '0'
|
7849 |
|
|
)
|
7850 |
|
|
port map (
|
7851 |
|
|
C => sig00000042,
|
7852 |
|
|
CE => blk00000003_sig00000067,
|
7853 |
|
|
D => blk00000003_sig00000153,
|
7854 |
|
|
Q => blk00000003_sig00000154
|
7855 |
|
|
);
|
7856 |
|
|
blk00000003_blk0000006e : FDE
|
7857 |
|
|
generic map(
|
7858 |
|
|
INIT => '0'
|
7859 |
|
|
)
|
7860 |
|
|
port map (
|
7861 |
|
|
C => sig00000042,
|
7862 |
|
|
CE => blk00000003_sig00000067,
|
7863 |
|
|
D => blk00000003_sig00000151,
|
7864 |
|
|
Q => blk00000003_sig00000152
|
7865 |
|
|
);
|
7866 |
|
|
blk00000003_blk0000006d : FDE
|
7867 |
|
|
generic map(
|
7868 |
|
|
INIT => '0'
|
7869 |
|
|
)
|
7870 |
|
|
port map (
|
7871 |
|
|
C => sig00000042,
|
7872 |
|
|
CE => blk00000003_sig00000067,
|
7873 |
|
|
D => blk00000003_sig0000014f,
|
7874 |
|
|
Q => blk00000003_sig00000150
|
7875 |
|
|
);
|
7876 |
|
|
blk00000003_blk0000006c : FDE
|
7877 |
|
|
generic map(
|
7878 |
|
|
INIT => '0'
|
7879 |
|
|
)
|
7880 |
|
|
port map (
|
7881 |
|
|
C => sig00000042,
|
7882 |
|
|
CE => blk00000003_sig00000067,
|
7883 |
|
|
D => blk00000003_sig0000014d,
|
7884 |
|
|
Q => blk00000003_sig0000014e
|
7885 |
|
|
);
|
7886 |
|
|
blk00000003_blk0000006b : FDE
|
7887 |
|
|
generic map(
|
7888 |
|
|
INIT => '0'
|
7889 |
|
|
)
|
7890 |
|
|
port map (
|
7891 |
|
|
C => sig00000042,
|
7892 |
|
|
CE => blk00000003_sig00000067,
|
7893 |
|
|
D => blk00000003_sig0000014b,
|
7894 |
|
|
Q => blk00000003_sig0000014c
|
7895 |
|
|
);
|
7896 |
|
|
blk00000003_blk0000006a : FDE
|
7897 |
|
|
generic map(
|
7898 |
|
|
INIT => '0'
|
7899 |
|
|
)
|
7900 |
|
|
port map (
|
7901 |
|
|
C => sig00000042,
|
7902 |
|
|
CE => blk00000003_sig00000067,
|
7903 |
|
|
D => blk00000003_sig00000149,
|
7904 |
|
|
Q => blk00000003_sig0000014a
|
7905 |
|
|
);
|
7906 |
|
|
blk00000003_blk00000069 : FDE
|
7907 |
|
|
generic map(
|
7908 |
|
|
INIT => '0'
|
7909 |
|
|
)
|
7910 |
|
|
port map (
|
7911 |
|
|
C => sig00000042,
|
7912 |
|
|
CE => blk00000003_sig00000067,
|
7913 |
|
|
D => blk00000003_sig00000147,
|
7914 |
|
|
Q => blk00000003_sig00000148
|
7915 |
|
|
);
|
7916 |
|
|
blk00000003_blk00000068 : FDE
|
7917 |
|
|
generic map(
|
7918 |
|
|
INIT => '0'
|
7919 |
|
|
)
|
7920 |
|
|
port map (
|
7921 |
|
|
C => sig00000042,
|
7922 |
|
|
CE => blk00000003_sig00000067,
|
7923 |
|
|
D => blk00000003_sig00000145,
|
7924 |
|
|
Q => blk00000003_sig00000146
|
7925 |
|
|
);
|
7926 |
|
|
blk00000003_blk00000067 : FDE
|
7927 |
|
|
generic map(
|
7928 |
|
|
INIT => '0'
|
7929 |
|
|
)
|
7930 |
|
|
port map (
|
7931 |
|
|
C => sig00000042,
|
7932 |
|
|
CE => blk00000003_sig00000067,
|
7933 |
|
|
D => blk00000003_sig00000143,
|
7934 |
|
|
Q => blk00000003_sig00000144
|
7935 |
|
|
);
|
7936 |
|
|
blk00000003_blk00000066 : FDE
|
7937 |
|
|
generic map(
|
7938 |
|
|
INIT => '0'
|
7939 |
|
|
)
|
7940 |
|
|
port map (
|
7941 |
|
|
C => sig00000042,
|
7942 |
|
|
CE => blk00000003_sig00000067,
|
7943 |
|
|
D => blk00000003_sig00000141,
|
7944 |
|
|
Q => blk00000003_sig00000142
|
7945 |
|
|
);
|
7946 |
|
|
blk00000003_blk00000065 : FDE
|
7947 |
|
|
generic map(
|
7948 |
|
|
INIT => '0'
|
7949 |
|
|
)
|
7950 |
|
|
port map (
|
7951 |
|
|
C => sig00000042,
|
7952 |
|
|
CE => blk00000003_sig00000067,
|
7953 |
|
|
D => blk00000003_sig0000013f,
|
7954 |
|
|
Q => blk00000003_sig00000140
|
7955 |
|
|
);
|
7956 |
|
|
blk00000003_blk00000064 : FDE
|
7957 |
|
|
generic map(
|
7958 |
|
|
INIT => '0'
|
7959 |
|
|
)
|
7960 |
|
|
port map (
|
7961 |
|
|
C => sig00000042,
|
7962 |
|
|
CE => blk00000003_sig00000067,
|
7963 |
|
|
D => blk00000003_sig0000013d,
|
7964 |
|
|
Q => blk00000003_sig0000013e
|
7965 |
|
|
);
|
7966 |
|
|
blk00000003_blk00000063 : FDE
|
7967 |
|
|
generic map(
|
7968 |
|
|
INIT => '0'
|
7969 |
|
|
)
|
7970 |
|
|
port map (
|
7971 |
|
|
C => sig00000042,
|
7972 |
|
|
CE => blk00000003_sig00000067,
|
7973 |
|
|
D => blk00000003_sig0000013b,
|
7974 |
|
|
Q => blk00000003_sig0000013c
|
7975 |
|
|
);
|
7976 |
|
|
blk00000003_blk00000062 : FDE
|
7977 |
|
|
generic map(
|
7978 |
|
|
INIT => '0'
|
7979 |
|
|
)
|
7980 |
|
|
port map (
|
7981 |
|
|
C => sig00000042,
|
7982 |
|
|
CE => blk00000003_sig00000067,
|
7983 |
|
|
D => blk00000003_sig00000139,
|
7984 |
|
|
Q => blk00000003_sig0000013a
|
7985 |
|
|
);
|
7986 |
|
|
blk00000003_blk00000061 : FDE
|
7987 |
|
|
generic map(
|
7988 |
|
|
INIT => '0'
|
7989 |
|
|
)
|
7990 |
|
|
port map (
|
7991 |
|
|
C => sig00000042,
|
7992 |
|
|
CE => blk00000003_sig00000067,
|
7993 |
|
|
D => blk00000003_sig00000137,
|
7994 |
|
|
Q => blk00000003_sig00000138
|
7995 |
|
|
);
|
7996 |
|
|
blk00000003_blk00000060 : FDE
|
7997 |
|
|
generic map(
|
7998 |
|
|
INIT => '0'
|
7999 |
|
|
)
|
8000 |
|
|
port map (
|
8001 |
|
|
C => sig00000042,
|
8002 |
|
|
CE => blk00000003_sig00000067,
|
8003 |
|
|
D => blk00000003_sig00000135,
|
8004 |
|
|
Q => blk00000003_sig00000136
|
8005 |
|
|
);
|
8006 |
|
|
blk00000003_blk0000005f : FDE
|
8007 |
|
|
generic map(
|
8008 |
|
|
INIT => '0'
|
8009 |
|
|
)
|
8010 |
|
|
port map (
|
8011 |
|
|
C => sig00000042,
|
8012 |
|
|
CE => blk00000003_sig00000067,
|
8013 |
|
|
D => blk00000003_sig00000133,
|
8014 |
|
|
Q => blk00000003_sig00000134
|
8015 |
|
|
);
|
8016 |
|
|
blk00000003_blk0000005e : FDE
|
8017 |
|
|
generic map(
|
8018 |
|
|
INIT => '0'
|
8019 |
|
|
)
|
8020 |
|
|
port map (
|
8021 |
|
|
C => sig00000042,
|
8022 |
|
|
CE => blk00000003_sig00000067,
|
8023 |
|
|
D => blk00000003_sig00000131,
|
8024 |
|
|
Q => blk00000003_sig00000132
|
8025 |
|
|
);
|
8026 |
|
|
blk00000003_blk0000005d : FDE
|
8027 |
|
|
generic map(
|
8028 |
|
|
INIT => '0'
|
8029 |
|
|
)
|
8030 |
|
|
port map (
|
8031 |
|
|
C => sig00000042,
|
8032 |
|
|
CE => blk00000003_sig00000067,
|
8033 |
|
|
D => blk00000003_sig0000012f,
|
8034 |
|
|
Q => blk00000003_sig00000130
|
8035 |
|
|
);
|
8036 |
|
|
blk00000003_blk0000005c : FDRS
|
8037 |
|
|
port map (
|
8038 |
|
|
C => sig00000042,
|
8039 |
|
|
D => blk00000003_sig0000012e,
|
8040 |
|
|
R => blk00000003_sig00000126,
|
8041 |
|
|
S => blk00000003_sig00000127,
|
8042 |
|
|
Q => sig0000004c
|
8043 |
|
|
);
|
8044 |
|
|
blk00000003_blk0000005b : FDRS
|
8045 |
|
|
port map (
|
8046 |
|
|
C => sig00000042,
|
8047 |
|
|
D => blk00000003_sig0000012d,
|
8048 |
|
|
R => blk00000003_sig00000126,
|
8049 |
|
|
S => blk00000003_sig00000127,
|
8050 |
|
|
Q => sig0000004b
|
8051 |
|
|
);
|
8052 |
|
|
blk00000003_blk0000005a : FDRS
|
8053 |
|
|
port map (
|
8054 |
|
|
C => sig00000042,
|
8055 |
|
|
D => blk00000003_sig0000012c,
|
8056 |
|
|
R => blk00000003_sig00000126,
|
8057 |
|
|
S => blk00000003_sig00000127,
|
8058 |
|
|
Q => sig0000004a
|
8059 |
|
|
);
|
8060 |
|
|
blk00000003_blk00000059 : FDRS
|
8061 |
|
|
port map (
|
8062 |
|
|
C => sig00000042,
|
8063 |
|
|
D => blk00000003_sig0000012b,
|
8064 |
|
|
R => blk00000003_sig00000126,
|
8065 |
|
|
S => blk00000003_sig00000127,
|
8066 |
|
|
Q => sig00000049
|
8067 |
|
|
);
|
8068 |
|
|
blk00000003_blk00000058 : FDRS
|
8069 |
|
|
port map (
|
8070 |
|
|
C => sig00000042,
|
8071 |
|
|
D => blk00000003_sig0000012a,
|
8072 |
|
|
R => blk00000003_sig00000126,
|
8073 |
|
|
S => blk00000003_sig00000127,
|
8074 |
|
|
Q => sig00000048
|
8075 |
|
|
);
|
8076 |
|
|
blk00000003_blk00000057 : FDRS
|
8077 |
|
|
port map (
|
8078 |
|
|
C => sig00000042,
|
8079 |
|
|
D => blk00000003_sig00000129,
|
8080 |
|
|
R => blk00000003_sig00000126,
|
8081 |
|
|
S => blk00000003_sig00000127,
|
8082 |
|
|
Q => sig00000047
|
8083 |
|
|
);
|
8084 |
|
|
blk00000003_blk00000056 : FDRS
|
8085 |
|
|
port map (
|
8086 |
|
|
C => sig00000042,
|
8087 |
|
|
D => blk00000003_sig00000128,
|
8088 |
|
|
R => blk00000003_sig00000126,
|
8089 |
|
|
S => blk00000003_sig00000127,
|
8090 |
|
|
Q => sig00000046
|
8091 |
|
|
);
|
8092 |
|
|
blk00000003_blk00000055 : FDRS
|
8093 |
|
|
port map (
|
8094 |
|
|
C => sig00000042,
|
8095 |
|
|
D => blk00000003_sig00000125,
|
8096 |
|
|
R => blk00000003_sig00000126,
|
8097 |
|
|
S => blk00000003_sig00000127,
|
8098 |
|
|
Q => sig00000045
|
8099 |
|
|
);
|
8100 |
|
|
blk00000003_blk00000054 : FDRS
|
8101 |
|
|
port map (
|
8102 |
|
|
C => sig00000042,
|
8103 |
|
|
D => blk00000003_sig00000124,
|
8104 |
|
|
R => blk00000003_sig0000010b,
|
8105 |
|
|
S => blk00000003_sig00000066,
|
8106 |
|
|
Q => sig00000059
|
8107 |
|
|
);
|
8108 |
|
|
blk00000003_blk00000053 : FDRS
|
8109 |
|
|
port map (
|
8110 |
|
|
C => sig00000042,
|
8111 |
|
|
D => blk00000003_sig00000123,
|
8112 |
|
|
R => blk00000003_sig0000010b,
|
8113 |
|
|
S => blk00000003_sig00000066,
|
8114 |
|
|
Q => sig00000058
|
8115 |
|
|
);
|
8116 |
|
|
blk00000003_blk00000052 : FDRS
|
8117 |
|
|
port map (
|
8118 |
|
|
C => sig00000042,
|
8119 |
|
|
D => blk00000003_sig00000122,
|
8120 |
|
|
R => blk00000003_sig0000010b,
|
8121 |
|
|
S => blk00000003_sig00000066,
|
8122 |
|
|
Q => sig00000056
|
8123 |
|
|
);
|
8124 |
|
|
blk00000003_blk00000051 : FDRS
|
8125 |
|
|
port map (
|
8126 |
|
|
C => sig00000042,
|
8127 |
|
|
D => blk00000003_sig00000121,
|
8128 |
|
|
R => blk00000003_sig0000010b,
|
8129 |
|
|
S => blk00000003_sig00000066,
|
8130 |
|
|
Q => sig00000057
|
8131 |
|
|
);
|
8132 |
|
|
blk00000003_blk00000050 : FDRS
|
8133 |
|
|
port map (
|
8134 |
|
|
C => sig00000042,
|
8135 |
|
|
D => blk00000003_sig00000120,
|
8136 |
|
|
R => blk00000003_sig0000010b,
|
8137 |
|
|
S => blk00000003_sig00000066,
|
8138 |
|
|
Q => sig00000055
|
8139 |
|
|
);
|
8140 |
|
|
blk00000003_blk0000004f : FDRS
|
8141 |
|
|
port map (
|
8142 |
|
|
C => sig00000042,
|
8143 |
|
|
D => blk00000003_sig0000011f,
|
8144 |
|
|
R => blk00000003_sig0000010b,
|
8145 |
|
|
S => blk00000003_sig00000066,
|
8146 |
|
|
Q => sig0000004f
|
8147 |
|
|
);
|
8148 |
|
|
blk00000003_blk0000004e : FDRS
|
8149 |
|
|
port map (
|
8150 |
|
|
C => sig00000042,
|
8151 |
|
|
D => blk00000003_sig0000011e,
|
8152 |
|
|
R => blk00000003_sig0000010b,
|
8153 |
|
|
S => blk00000003_sig00000066,
|
8154 |
|
|
Q => sig00000054
|
8155 |
|
|
);
|
8156 |
|
|
blk00000003_blk0000004d : FDRS
|
8157 |
|
|
port map (
|
8158 |
|
|
C => sig00000042,
|
8159 |
|
|
D => blk00000003_sig0000011d,
|
8160 |
|
|
R => blk00000003_sig0000010b,
|
8161 |
|
|
S => blk00000003_sig00000066,
|
8162 |
|
|
Q => sig0000004e
|
8163 |
|
|
);
|
8164 |
|
|
blk00000003_blk0000004c : FDRS
|
8165 |
|
|
port map (
|
8166 |
|
|
C => sig00000042,
|
8167 |
|
|
D => blk00000003_sig0000011a,
|
8168 |
|
|
R => blk00000003_sig0000011b,
|
8169 |
|
|
S => blk00000003_sig0000011c,
|
8170 |
|
|
Q => sig0000004d
|
8171 |
|
|
);
|
8172 |
|
|
blk00000003_blk0000004b : FDRS
|
8173 |
|
|
port map (
|
8174 |
|
|
C => sig00000042,
|
8175 |
|
|
D => blk00000003_sig00000119,
|
8176 |
|
|
R => blk00000003_sig0000010b,
|
8177 |
|
|
S => blk00000003_sig00000066,
|
8178 |
|
|
Q => sig00000053
|
8179 |
|
|
);
|
8180 |
|
|
blk00000003_blk0000004a : FDRS
|
8181 |
|
|
port map (
|
8182 |
|
|
C => sig00000042,
|
8183 |
|
|
D => blk00000003_sig00000118,
|
8184 |
|
|
R => blk00000003_sig0000010b,
|
8185 |
|
|
S => blk00000003_sig00000066,
|
8186 |
|
|
Q => sig00000052
|
8187 |
|
|
);
|
8188 |
|
|
blk00000003_blk00000049 : FDRS
|
8189 |
|
|
port map (
|
8190 |
|
|
C => sig00000042,
|
8191 |
|
|
D => blk00000003_sig00000117,
|
8192 |
|
|
R => blk00000003_sig0000010b,
|
8193 |
|
|
S => blk00000003_sig00000066,
|
8194 |
|
|
Q => sig00000051
|
8195 |
|
|
);
|
8196 |
|
|
blk00000003_blk00000048 : FDRS
|
8197 |
|
|
port map (
|
8198 |
|
|
C => sig00000042,
|
8199 |
|
|
D => blk00000003_sig00000116,
|
8200 |
|
|
R => blk00000003_sig0000010b,
|
8201 |
|
|
S => blk00000003_sig00000066,
|
8202 |
|
|
Q => sig00000050
|
8203 |
|
|
);
|
8204 |
|
|
blk00000003_blk00000047 : FDRS
|
8205 |
|
|
port map (
|
8206 |
|
|
C => sig00000042,
|
8207 |
|
|
D => blk00000003_sig00000115,
|
8208 |
|
|
R => blk00000003_sig0000010b,
|
8209 |
|
|
S => blk00000003_sig00000066,
|
8210 |
|
|
Q => sig00000063
|
8211 |
|
|
);
|
8212 |
|
|
blk00000003_blk00000046 : FDRS
|
8213 |
|
|
port map (
|
8214 |
|
|
C => sig00000042,
|
8215 |
|
|
D => blk00000003_sig00000114,
|
8216 |
|
|
R => blk00000003_sig0000010b,
|
8217 |
|
|
S => blk00000003_sig00000066,
|
8218 |
|
|
Q => sig00000060
|
8219 |
|
|
);
|
8220 |
|
|
blk00000003_blk00000045 : FDRS
|
8221 |
|
|
port map (
|
8222 |
|
|
C => sig00000042,
|
8223 |
|
|
D => blk00000003_sig00000113,
|
8224 |
|
|
R => blk00000003_sig0000010b,
|
8225 |
|
|
S => blk00000003_sig00000066,
|
8226 |
|
|
Q => sig00000062
|
8227 |
|
|
);
|
8228 |
|
|
blk00000003_blk00000044 : FDRS
|
8229 |
|
|
port map (
|
8230 |
|
|
C => sig00000042,
|
8231 |
|
|
D => blk00000003_sig00000112,
|
8232 |
|
|
R => blk00000003_sig0000010b,
|
8233 |
|
|
S => blk00000003_sig00000066,
|
8234 |
|
|
Q => sig00000061
|
8235 |
|
|
);
|
8236 |
|
|
blk00000003_blk00000043 : FDRS
|
8237 |
|
|
port map (
|
8238 |
|
|
C => sig00000042,
|
8239 |
|
|
D => blk00000003_sig00000111,
|
8240 |
|
|
R => blk00000003_sig0000010b,
|
8241 |
|
|
S => blk00000003_sig00000066,
|
8242 |
|
|
Q => sig0000005f
|
8243 |
|
|
);
|
8244 |
|
|
blk00000003_blk00000042 : FDRS
|
8245 |
|
|
port map (
|
8246 |
|
|
C => sig00000042,
|
8247 |
|
|
D => blk00000003_sig00000110,
|
8248 |
|
|
R => blk00000003_sig0000010b,
|
8249 |
|
|
S => blk00000003_sig00000066,
|
8250 |
|
|
Q => sig0000005e
|
8251 |
|
|
);
|
8252 |
|
|
blk00000003_blk00000041 : FDRS
|
8253 |
|
|
port map (
|
8254 |
|
|
C => sig00000042,
|
8255 |
|
|
D => blk00000003_sig0000010f,
|
8256 |
|
|
R => blk00000003_sig0000010b,
|
8257 |
|
|
S => blk00000003_sig00000066,
|
8258 |
|
|
Q => sig0000005d
|
8259 |
|
|
);
|
8260 |
|
|
blk00000003_blk00000040 : FDRS
|
8261 |
|
|
port map (
|
8262 |
|
|
C => sig00000042,
|
8263 |
|
|
D => blk00000003_sig0000010e,
|
8264 |
|
|
R => blk00000003_sig0000010b,
|
8265 |
|
|
S => blk00000003_sig00000066,
|
8266 |
|
|
Q => sig0000005c
|
8267 |
|
|
);
|
8268 |
|
|
blk00000003_blk0000003f : FDRS
|
8269 |
|
|
port map (
|
8270 |
|
|
C => sig00000042,
|
8271 |
|
|
D => blk00000003_sig0000010d,
|
8272 |
|
|
R => blk00000003_sig00000066,
|
8273 |
|
|
S => blk00000003_sig00000066,
|
8274 |
|
|
Q => sig00000044
|
8275 |
|
|
);
|
8276 |
|
|
blk00000003_blk0000003e : FDRS
|
8277 |
|
|
port map (
|
8278 |
|
|
C => sig00000042,
|
8279 |
|
|
D => blk00000003_sig0000010c,
|
8280 |
|
|
R => blk00000003_sig0000010b,
|
8281 |
|
|
S => blk00000003_sig00000066,
|
8282 |
|
|
Q => sig0000005b
|
8283 |
|
|
);
|
8284 |
|
|
blk00000003_blk0000003d : FDRS
|
8285 |
|
|
port map (
|
8286 |
|
|
C => sig00000042,
|
8287 |
|
|
D => blk00000003_sig0000010a,
|
8288 |
|
|
R => blk00000003_sig0000010b,
|
8289 |
|
|
S => blk00000003_sig00000066,
|
8290 |
|
|
Q => sig0000005a
|
8291 |
|
|
);
|
8292 |
|
|
blk00000003_blk0000003c : FDE
|
8293 |
|
|
generic map(
|
8294 |
|
|
INIT => '0'
|
8295 |
|
|
)
|
8296 |
|
|
port map (
|
8297 |
|
|
C => sig00000042,
|
8298 |
|
|
CE => blk00000003_sig00000067,
|
8299 |
|
|
D => sig00000020,
|
8300 |
|
|
Q => blk00000003_sig00000109
|
8301 |
|
|
);
|
8302 |
|
|
blk00000003_blk0000003b : FDE
|
8303 |
|
|
generic map(
|
8304 |
|
|
INIT => '0'
|
8305 |
|
|
)
|
8306 |
|
|
port map (
|
8307 |
|
|
C => sig00000042,
|
8308 |
|
|
CE => blk00000003_sig00000067,
|
8309 |
|
|
D => sig0000001f,
|
8310 |
|
|
Q => blk00000003_sig00000108
|
8311 |
|
|
);
|
8312 |
|
|
blk00000003_blk0000003a : FDE
|
8313 |
|
|
generic map(
|
8314 |
|
|
INIT => '0'
|
8315 |
|
|
)
|
8316 |
|
|
port map (
|
8317 |
|
|
C => sig00000042,
|
8318 |
|
|
CE => blk00000003_sig00000067,
|
8319 |
|
|
D => sig0000001e,
|
8320 |
|
|
Q => blk00000003_sig00000107
|
8321 |
|
|
);
|
8322 |
|
|
blk00000003_blk00000039 : FDE
|
8323 |
|
|
generic map(
|
8324 |
|
|
INIT => '0'
|
8325 |
|
|
)
|
8326 |
|
|
port map (
|
8327 |
|
|
C => sig00000042,
|
8328 |
|
|
CE => blk00000003_sig00000067,
|
8329 |
|
|
D => sig0000001d,
|
8330 |
|
|
Q => blk00000003_sig00000106
|
8331 |
|
|
);
|
8332 |
|
|
blk00000003_blk00000038 : FDE
|
8333 |
|
|
generic map(
|
8334 |
|
|
INIT => '0'
|
8335 |
|
|
)
|
8336 |
|
|
port map (
|
8337 |
|
|
C => sig00000042,
|
8338 |
|
|
CE => blk00000003_sig00000067,
|
8339 |
|
|
D => sig0000001c,
|
8340 |
|
|
Q => blk00000003_sig00000105
|
8341 |
|
|
);
|
8342 |
|
|
blk00000003_blk00000037 : FDE
|
8343 |
|
|
generic map(
|
8344 |
|
|
INIT => '0'
|
8345 |
|
|
)
|
8346 |
|
|
port map (
|
8347 |
|
|
C => sig00000042,
|
8348 |
|
|
CE => blk00000003_sig00000067,
|
8349 |
|
|
D => sig0000001b,
|
8350 |
|
|
Q => blk00000003_sig00000104
|
8351 |
|
|
);
|
8352 |
|
|
blk00000003_blk00000036 : FDE
|
8353 |
|
|
generic map(
|
8354 |
|
|
INIT => '0'
|
8355 |
|
|
)
|
8356 |
|
|
port map (
|
8357 |
|
|
C => sig00000042,
|
8358 |
|
|
CE => blk00000003_sig00000067,
|
8359 |
|
|
D => sig0000001a,
|
8360 |
|
|
Q => blk00000003_sig00000103
|
8361 |
|
|
);
|
8362 |
|
|
blk00000003_blk00000035 : FDE
|
8363 |
|
|
generic map(
|
8364 |
|
|
INIT => '0'
|
8365 |
|
|
)
|
8366 |
|
|
port map (
|
8367 |
|
|
C => sig00000042,
|
8368 |
|
|
CE => blk00000003_sig00000067,
|
8369 |
|
|
D => sig00000019,
|
8370 |
|
|
Q => blk00000003_sig00000102
|
8371 |
|
|
);
|
8372 |
|
|
blk00000003_blk00000034 : FDE
|
8373 |
|
|
generic map(
|
8374 |
|
|
INIT => '0'
|
8375 |
|
|
)
|
8376 |
|
|
port map (
|
8377 |
|
|
C => sig00000042,
|
8378 |
|
|
CE => blk00000003_sig00000067,
|
8379 |
|
|
D => sig00000018,
|
8380 |
|
|
Q => blk00000003_sig00000101
|
8381 |
|
|
);
|
8382 |
|
|
blk00000003_blk00000033 : FDE
|
8383 |
|
|
generic map(
|
8384 |
|
|
INIT => '0'
|
8385 |
|
|
)
|
8386 |
|
|
port map (
|
8387 |
|
|
C => sig00000042,
|
8388 |
|
|
CE => blk00000003_sig00000067,
|
8389 |
|
|
D => sig00000017,
|
8390 |
|
|
Q => blk00000003_sig00000100
|
8391 |
|
|
);
|
8392 |
|
|
blk00000003_blk00000032 : FDE
|
8393 |
|
|
generic map(
|
8394 |
|
|
INIT => '0'
|
8395 |
|
|
)
|
8396 |
|
|
port map (
|
8397 |
|
|
C => sig00000042,
|
8398 |
|
|
CE => blk00000003_sig00000067,
|
8399 |
|
|
D => sig00000016,
|
8400 |
|
|
Q => blk00000003_sig000000ff
|
8401 |
|
|
);
|
8402 |
|
|
blk00000003_blk00000031 : FDE
|
8403 |
|
|
generic map(
|
8404 |
|
|
INIT => '0'
|
8405 |
|
|
)
|
8406 |
|
|
port map (
|
8407 |
|
|
C => sig00000042,
|
8408 |
|
|
CE => blk00000003_sig00000067,
|
8409 |
|
|
D => sig00000015,
|
8410 |
|
|
Q => blk00000003_sig000000fe
|
8411 |
|
|
);
|
8412 |
|
|
blk00000003_blk00000030 : FDE
|
8413 |
|
|
generic map(
|
8414 |
|
|
INIT => '0'
|
8415 |
|
|
)
|
8416 |
|
|
port map (
|
8417 |
|
|
C => sig00000042,
|
8418 |
|
|
CE => blk00000003_sig00000067,
|
8419 |
|
|
D => sig00000014,
|
8420 |
|
|
Q => blk00000003_sig000000fd
|
8421 |
|
|
);
|
8422 |
|
|
blk00000003_blk0000002f : FDE
|
8423 |
|
|
generic map(
|
8424 |
|
|
INIT => '0'
|
8425 |
|
|
)
|
8426 |
|
|
port map (
|
8427 |
|
|
C => sig00000042,
|
8428 |
|
|
CE => blk00000003_sig00000067,
|
8429 |
|
|
D => sig00000013,
|
8430 |
|
|
Q => blk00000003_sig000000fc
|
8431 |
|
|
);
|
8432 |
|
|
blk00000003_blk0000002e : FDE
|
8433 |
|
|
generic map(
|
8434 |
|
|
INIT => '0'
|
8435 |
|
|
)
|
8436 |
|
|
port map (
|
8437 |
|
|
C => sig00000042,
|
8438 |
|
|
CE => blk00000003_sig00000067,
|
8439 |
|
|
D => sig00000012,
|
8440 |
|
|
Q => blk00000003_sig000000fb
|
8441 |
|
|
);
|
8442 |
|
|
blk00000003_blk0000002d : FDE
|
8443 |
|
|
generic map(
|
8444 |
|
|
INIT => '0'
|
8445 |
|
|
)
|
8446 |
|
|
port map (
|
8447 |
|
|
C => sig00000042,
|
8448 |
|
|
CE => blk00000003_sig00000067,
|
8449 |
|
|
D => sig00000011,
|
8450 |
|
|
Q => blk00000003_sig000000fa
|
8451 |
|
|
);
|
8452 |
|
|
blk00000003_blk0000002c : FDE
|
8453 |
|
|
generic map(
|
8454 |
|
|
INIT => '0'
|
8455 |
|
|
)
|
8456 |
|
|
port map (
|
8457 |
|
|
C => sig00000042,
|
8458 |
|
|
CE => blk00000003_sig00000067,
|
8459 |
|
|
D => sig00000010,
|
8460 |
|
|
Q => blk00000003_sig000000f9
|
8461 |
|
|
);
|
8462 |
|
|
blk00000003_blk0000002b : FDE
|
8463 |
|
|
generic map(
|
8464 |
|
|
INIT => '0'
|
8465 |
|
|
)
|
8466 |
|
|
port map (
|
8467 |
|
|
C => sig00000042,
|
8468 |
|
|
CE => blk00000003_sig00000067,
|
8469 |
|
|
D => sig0000000f,
|
8470 |
|
|
Q => blk00000003_sig000000f8
|
8471 |
|
|
);
|
8472 |
|
|
blk00000003_blk0000002a : FDE
|
8473 |
|
|
generic map(
|
8474 |
|
|
INIT => '0'
|
8475 |
|
|
)
|
8476 |
|
|
port map (
|
8477 |
|
|
C => sig00000042,
|
8478 |
|
|
CE => blk00000003_sig00000067,
|
8479 |
|
|
D => sig0000000e,
|
8480 |
|
|
Q => blk00000003_sig000000f7
|
8481 |
|
|
);
|
8482 |
|
|
blk00000003_blk00000029 : FDE
|
8483 |
|
|
generic map(
|
8484 |
|
|
INIT => '0'
|
8485 |
|
|
)
|
8486 |
|
|
port map (
|
8487 |
|
|
C => sig00000042,
|
8488 |
|
|
CE => blk00000003_sig00000067,
|
8489 |
|
|
D => sig0000000d,
|
8490 |
|
|
Q => blk00000003_sig000000f6
|
8491 |
|
|
);
|
8492 |
|
|
blk00000003_blk00000028 : FDE
|
8493 |
|
|
generic map(
|
8494 |
|
|
INIT => '0'
|
8495 |
|
|
)
|
8496 |
|
|
port map (
|
8497 |
|
|
C => sig00000042,
|
8498 |
|
|
CE => blk00000003_sig00000067,
|
8499 |
|
|
D => sig0000000c,
|
8500 |
|
|
Q => blk00000003_sig000000f5
|
8501 |
|
|
);
|
8502 |
|
|
blk00000003_blk00000027 : FDE
|
8503 |
|
|
generic map(
|
8504 |
|
|
INIT => '0'
|
8505 |
|
|
)
|
8506 |
|
|
port map (
|
8507 |
|
|
C => sig00000042,
|
8508 |
|
|
CE => blk00000003_sig00000067,
|
8509 |
|
|
D => sig0000000b,
|
8510 |
|
|
Q => blk00000003_sig000000f4
|
8511 |
|
|
);
|
8512 |
|
|
blk00000003_blk00000026 : FDE
|
8513 |
|
|
generic map(
|
8514 |
|
|
INIT => '0'
|
8515 |
|
|
)
|
8516 |
|
|
port map (
|
8517 |
|
|
C => sig00000042,
|
8518 |
|
|
CE => blk00000003_sig00000067,
|
8519 |
|
|
D => sig0000000a,
|
8520 |
|
|
Q => blk00000003_sig000000f3
|
8521 |
|
|
);
|
8522 |
|
|
blk00000003_blk00000025 : FDE
|
8523 |
|
|
generic map(
|
8524 |
|
|
INIT => '0'
|
8525 |
|
|
)
|
8526 |
|
|
port map (
|
8527 |
|
|
C => sig00000042,
|
8528 |
|
|
CE => blk00000003_sig00000067,
|
8529 |
|
|
D => sig00000040,
|
8530 |
|
|
Q => blk00000003_sig000000f2
|
8531 |
|
|
);
|
8532 |
|
|
blk00000003_blk00000024 : FDE
|
8533 |
|
|
generic map(
|
8534 |
|
|
INIT => '0'
|
8535 |
|
|
)
|
8536 |
|
|
port map (
|
8537 |
|
|
C => sig00000042,
|
8538 |
|
|
CE => blk00000003_sig00000067,
|
8539 |
|
|
D => sig0000003f,
|
8540 |
|
|
Q => blk00000003_sig000000f1
|
8541 |
|
|
);
|
8542 |
|
|
blk00000003_blk00000023 : FDE
|
8543 |
|
|
generic map(
|
8544 |
|
|
INIT => '0'
|
8545 |
|
|
)
|
8546 |
|
|
port map (
|
8547 |
|
|
C => sig00000042,
|
8548 |
|
|
CE => blk00000003_sig00000067,
|
8549 |
|
|
D => sig0000003e,
|
8550 |
|
|
Q => blk00000003_sig000000f0
|
8551 |
|
|
);
|
8552 |
|
|
blk00000003_blk00000022 : FDE
|
8553 |
|
|
generic map(
|
8554 |
|
|
INIT => '0'
|
8555 |
|
|
)
|
8556 |
|
|
port map (
|
8557 |
|
|
C => sig00000042,
|
8558 |
|
|
CE => blk00000003_sig00000067,
|
8559 |
|
|
D => sig0000003d,
|
8560 |
|
|
Q => blk00000003_sig000000ef
|
8561 |
|
|
);
|
8562 |
|
|
blk00000003_blk00000021 : FDE
|
8563 |
|
|
generic map(
|
8564 |
|
|
INIT => '0'
|
8565 |
|
|
)
|
8566 |
|
|
port map (
|
8567 |
|
|
C => sig00000042,
|
8568 |
|
|
CE => blk00000003_sig00000067,
|
8569 |
|
|
D => sig0000003c,
|
8570 |
|
|
Q => blk00000003_sig000000ee
|
8571 |
|
|
);
|
8572 |
|
|
blk00000003_blk00000020 : FDE
|
8573 |
|
|
generic map(
|
8574 |
|
|
INIT => '0'
|
8575 |
|
|
)
|
8576 |
|
|
port map (
|
8577 |
|
|
C => sig00000042,
|
8578 |
|
|
CE => blk00000003_sig00000067,
|
8579 |
|
|
D => sig0000003b,
|
8580 |
|
|
Q => blk00000003_sig000000ed
|
8581 |
|
|
);
|
8582 |
|
|
blk00000003_blk0000001f : FDE
|
8583 |
|
|
generic map(
|
8584 |
|
|
INIT => '0'
|
8585 |
|
|
)
|
8586 |
|
|
port map (
|
8587 |
|
|
C => sig00000042,
|
8588 |
|
|
CE => blk00000003_sig00000067,
|
8589 |
|
|
D => sig0000003a,
|
8590 |
|
|
Q => blk00000003_sig000000ec
|
8591 |
|
|
);
|
8592 |
|
|
blk00000003_blk0000001e : FDE
|
8593 |
|
|
generic map(
|
8594 |
|
|
INIT => '0'
|
8595 |
|
|
)
|
8596 |
|
|
port map (
|
8597 |
|
|
C => sig00000042,
|
8598 |
|
|
CE => blk00000003_sig00000067,
|
8599 |
|
|
D => sig00000039,
|
8600 |
|
|
Q => blk00000003_sig000000eb
|
8601 |
|
|
);
|
8602 |
|
|
blk00000003_blk0000001d : FDE
|
8603 |
|
|
generic map(
|
8604 |
|
|
INIT => '0'
|
8605 |
|
|
)
|
8606 |
|
|
port map (
|
8607 |
|
|
C => sig00000042,
|
8608 |
|
|
CE => blk00000003_sig00000067,
|
8609 |
|
|
D => sig00000038,
|
8610 |
|
|
Q => blk00000003_sig000000ea
|
8611 |
|
|
);
|
8612 |
|
|
blk00000003_blk0000001c : FDE
|
8613 |
|
|
generic map(
|
8614 |
|
|
INIT => '0'
|
8615 |
|
|
)
|
8616 |
|
|
port map (
|
8617 |
|
|
C => sig00000042,
|
8618 |
|
|
CE => blk00000003_sig00000067,
|
8619 |
|
|
D => sig00000037,
|
8620 |
|
|
Q => blk00000003_sig000000e9
|
8621 |
|
|
);
|
8622 |
|
|
blk00000003_blk0000001b : FDE
|
8623 |
|
|
generic map(
|
8624 |
|
|
INIT => '0'
|
8625 |
|
|
)
|
8626 |
|
|
port map (
|
8627 |
|
|
C => sig00000042,
|
8628 |
|
|
CE => blk00000003_sig00000067,
|
8629 |
|
|
D => sig00000036,
|
8630 |
|
|
Q => blk00000003_sig000000e8
|
8631 |
|
|
);
|
8632 |
|
|
blk00000003_blk0000001a : FDE
|
8633 |
|
|
generic map(
|
8634 |
|
|
INIT => '0'
|
8635 |
|
|
)
|
8636 |
|
|
port map (
|
8637 |
|
|
C => sig00000042,
|
8638 |
|
|
CE => blk00000003_sig00000067,
|
8639 |
|
|
D => sig00000035,
|
8640 |
|
|
Q => blk00000003_sig000000e7
|
8641 |
|
|
);
|
8642 |
|
|
blk00000003_blk00000019 : FDE
|
8643 |
|
|
generic map(
|
8644 |
|
|
INIT => '0'
|
8645 |
|
|
)
|
8646 |
|
|
port map (
|
8647 |
|
|
C => sig00000042,
|
8648 |
|
|
CE => blk00000003_sig00000067,
|
8649 |
|
|
D => sig00000034,
|
8650 |
|
|
Q => blk00000003_sig000000e6
|
8651 |
|
|
);
|
8652 |
|
|
blk00000003_blk00000018 : FDE
|
8653 |
|
|
generic map(
|
8654 |
|
|
INIT => '0'
|
8655 |
|
|
)
|
8656 |
|
|
port map (
|
8657 |
|
|
C => sig00000042,
|
8658 |
|
|
CE => blk00000003_sig00000067,
|
8659 |
|
|
D => sig00000033,
|
8660 |
|
|
Q => blk00000003_sig000000e5
|
8661 |
|
|
);
|
8662 |
|
|
blk00000003_blk00000017 : FDE
|
8663 |
|
|
generic map(
|
8664 |
|
|
INIT => '0'
|
8665 |
|
|
)
|
8666 |
|
|
port map (
|
8667 |
|
|
C => sig00000042,
|
8668 |
|
|
CE => blk00000003_sig00000067,
|
8669 |
|
|
D => sig00000032,
|
8670 |
|
|
Q => blk00000003_sig000000e4
|
8671 |
|
|
);
|
8672 |
|
|
blk00000003_blk00000016 : FDE
|
8673 |
|
|
generic map(
|
8674 |
|
|
INIT => '0'
|
8675 |
|
|
)
|
8676 |
|
|
port map (
|
8677 |
|
|
C => sig00000042,
|
8678 |
|
|
CE => blk00000003_sig00000067,
|
8679 |
|
|
D => sig00000031,
|
8680 |
|
|
Q => blk00000003_sig000000e3
|
8681 |
|
|
);
|
8682 |
|
|
blk00000003_blk00000015 : FDE
|
8683 |
|
|
generic map(
|
8684 |
|
|
INIT => '0'
|
8685 |
|
|
)
|
8686 |
|
|
port map (
|
8687 |
|
|
C => sig00000042,
|
8688 |
|
|
CE => blk00000003_sig00000067,
|
8689 |
|
|
D => sig00000030,
|
8690 |
|
|
Q => blk00000003_sig000000e2
|
8691 |
|
|
);
|
8692 |
|
|
blk00000003_blk00000014 : FDE
|
8693 |
|
|
generic map(
|
8694 |
|
|
INIT => '0'
|
8695 |
|
|
)
|
8696 |
|
|
port map (
|
8697 |
|
|
C => sig00000042,
|
8698 |
|
|
CE => blk00000003_sig00000067,
|
8699 |
|
|
D => sig0000002f,
|
8700 |
|
|
Q => blk00000003_sig000000e1
|
8701 |
|
|
);
|
8702 |
|
|
blk00000003_blk00000013 : FDE
|
8703 |
|
|
generic map(
|
8704 |
|
|
INIT => '0'
|
8705 |
|
|
)
|
8706 |
|
|
port map (
|
8707 |
|
|
C => sig00000042,
|
8708 |
|
|
CE => blk00000003_sig00000067,
|
8709 |
|
|
D => sig0000002e,
|
8710 |
|
|
Q => blk00000003_sig000000e0
|
8711 |
|
|
);
|
8712 |
|
|
blk00000003_blk00000012 : FDE
|
8713 |
|
|
generic map(
|
8714 |
|
|
INIT => '0'
|
8715 |
|
|
)
|
8716 |
|
|
port map (
|
8717 |
|
|
C => sig00000042,
|
8718 |
|
|
CE => blk00000003_sig00000067,
|
8719 |
|
|
D => sig0000002d,
|
8720 |
|
|
Q => blk00000003_sig000000df
|
8721 |
|
|
);
|
8722 |
|
|
blk00000003_blk00000011 : FDE
|
8723 |
|
|
generic map(
|
8724 |
|
|
INIT => '0'
|
8725 |
|
|
)
|
8726 |
|
|
port map (
|
8727 |
|
|
C => sig00000042,
|
8728 |
|
|
CE => blk00000003_sig00000067,
|
8729 |
|
|
D => sig0000002c,
|
8730 |
|
|
Q => blk00000003_sig000000de
|
8731 |
|
|
);
|
8732 |
|
|
blk00000003_blk00000010 : FDE
|
8733 |
|
|
generic map(
|
8734 |
|
|
INIT => '0'
|
8735 |
|
|
)
|
8736 |
|
|
port map (
|
8737 |
|
|
C => sig00000042,
|
8738 |
|
|
CE => blk00000003_sig00000067,
|
8739 |
|
|
D => sig0000002b,
|
8740 |
|
|
Q => blk00000003_sig000000dd
|
8741 |
|
|
);
|
8742 |
|
|
blk00000003_blk0000000f : FDE
|
8743 |
|
|
generic map(
|
8744 |
|
|
INIT => '0'
|
8745 |
|
|
)
|
8746 |
|
|
port map (
|
8747 |
|
|
C => sig00000042,
|
8748 |
|
|
CE => blk00000003_sig00000067,
|
8749 |
|
|
D => sig0000002a,
|
8750 |
|
|
Q => blk00000003_sig000000dc
|
8751 |
|
|
);
|
8752 |
|
|
blk00000003_blk0000000e : FD
|
8753 |
|
|
generic map(
|
8754 |
|
|
INIT => '0'
|
8755 |
|
|
)
|
8756 |
|
|
port map (
|
8757 |
|
|
C => sig00000042,
|
8758 |
|
|
D => blk00000003_sig000000da,
|
8759 |
|
|
Q => blk00000003_sig000000db
|
8760 |
|
|
);
|
8761 |
|
|
blk00000003_blk0000000d : FDSE
|
8762 |
|
|
generic map(
|
8763 |
|
|
INIT => '0'
|
8764 |
|
|
)
|
8765 |
|
|
port map (
|
8766 |
|
|
C => sig00000042,
|
8767 |
|
|
CE => blk00000003_sig000000d8,
|
8768 |
|
|
D => blk00000003_sig00000066,
|
8769 |
|
|
S => sig00000043,
|
8770 |
|
|
Q => blk00000003_sig000000d9
|
8771 |
|
|
);
|
8772 |
|
|
blk00000003_blk0000000c : FDR
|
8773 |
|
|
generic map(
|
8774 |
|
|
INIT => '1'
|
8775 |
|
|
)
|
8776 |
|
|
port map (
|
8777 |
|
|
C => sig00000042,
|
8778 |
|
|
D => blk00000003_sig00000067,
|
8779 |
|
|
R => sig00000043,
|
8780 |
|
|
Q => blk00000003_sig000000d7
|
8781 |
|
|
);
|
8782 |
|
|
blk00000003_blk0000000b : FDR
|
8783 |
|
|
port map (
|
8784 |
|
|
C => sig00000042,
|
8785 |
|
|
D => blk00000003_sig000000d6,
|
8786 |
|
|
R => sig00000043,
|
8787 |
|
|
Q => sig00000064
|
8788 |
|
|
);
|
8789 |
|
|
blk00000003_blk0000000a : FDRE
|
8790 |
|
|
generic map(
|
8791 |
|
|
INIT => '0'
|
8792 |
|
|
)
|
8793 |
|
|
port map (
|
8794 |
|
|
C => sig00000042,
|
8795 |
|
|
CE => blk00000003_sig000000cb,
|
8796 |
|
|
D => blk00000003_sig000000d4,
|
8797 |
|
|
R => sig00000043,
|
8798 |
|
|
Q => blk00000003_sig000000d5
|
8799 |
|
|
);
|
8800 |
|
|
blk00000003_blk00000009 : FDRE
|
8801 |
|
|
generic map(
|
8802 |
|
|
INIT => '0'
|
8803 |
|
|
)
|
8804 |
|
|
port map (
|
8805 |
|
|
C => sig00000042,
|
8806 |
|
|
CE => blk00000003_sig000000cb,
|
8807 |
|
|
D => blk00000003_sig000000d2,
|
8808 |
|
|
R => sig00000043,
|
8809 |
|
|
Q => blk00000003_sig000000d3
|
8810 |
|
|
);
|
8811 |
|
|
blk00000003_blk00000008 : FDRE
|
8812 |
|
|
generic map(
|
8813 |
|
|
INIT => '0'
|
8814 |
|
|
)
|
8815 |
|
|
port map (
|
8816 |
|
|
C => sig00000042,
|
8817 |
|
|
CE => blk00000003_sig000000cb,
|
8818 |
|
|
D => blk00000003_sig000000d0,
|
8819 |
|
|
R => sig00000043,
|
8820 |
|
|
Q => blk00000003_sig000000d1
|
8821 |
|
|
);
|
8822 |
|
|
blk00000003_blk00000007 : FDRE
|
8823 |
|
|
generic map(
|
8824 |
|
|
INIT => '0'
|
8825 |
|
|
)
|
8826 |
|
|
port map (
|
8827 |
|
|
C => sig00000042,
|
8828 |
|
|
CE => blk00000003_sig000000cb,
|
8829 |
|
|
D => blk00000003_sig000000ce,
|
8830 |
|
|
R => sig00000043,
|
8831 |
|
|
Q => blk00000003_sig000000cf
|
8832 |
|
|
);
|
8833 |
|
|
blk00000003_blk00000006 : FDSE
|
8834 |
|
|
generic map(
|
8835 |
|
|
INIT => '1'
|
8836 |
|
|
)
|
8837 |
|
|
port map (
|
8838 |
|
|
C => sig00000042,
|
8839 |
|
|
CE => blk00000003_sig000000cb,
|
8840 |
|
|
D => blk00000003_sig000000cc,
|
8841 |
|
|
S => sig00000043,
|
8842 |
|
|
Q => blk00000003_sig000000cd
|
8843 |
|
|
);
|
8844 |
|
|
blk00000003_blk00000005 : VCC
|
8845 |
|
|
port map (
|
8846 |
|
|
P => blk00000003_sig00000067
|
8847 |
|
|
);
|
8848 |
|
|
blk00000003_blk00000004 : GND
|
8849 |
|
|
port map (
|
8850 |
|
|
G => blk00000003_sig00000066
|
8851 |
|
|
);
|
8852 |
|
|
|
8853 |
|
|
end STRUCTURE;
|
8854 |
|
|
|
8855 |
|
|
-- synthesis translate_on
|