Subversion Repositories fpga

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<p><font color="#BF0000" size="5" face="Helvetica, Arial"><b>Project

Name: Embedded FPGA Core</b></font> </p>

<p><font size="2">(See change Log at bottom of page for

changes/updates)</font> <br>

</p>

<p><font size="4"><u>Architecture Description</u></font> </p>

<p>Field-Programmable

Gate Arrays (FPGAs) are flexible and reusable high-density

circuits that can be (re)configured by the designer, enabling the

VLSI design/validation/ simulation cycle to be performed more

quickly and cheaply.</p>

<p>The flexibility

provided by FPGAs cause a substantial performance penalty due to

non-specialized circuit design and signal delay through the

programmable routing resources, compared do ASIC designs but

FPGAs are still 1000 times faster than circuit simulators.</p>

<p>This core

provides plural of high-speed reprogrammable logic. This FPGA has

regular structure and consists of three configurable elements:

Look-Up-Tables (LUTs), each with 8 inputs and 2 outputs, full 4b

adders and Input-Output Cells (IOCs). It logic size is

aproximately equal to 1500 Virtex LUTs. The development system

offers fully automated logic placement and routing (more about

P&R software can be found in FPGA P&R Software document).

Every non-adder function is stored in static memory array, called

LUT, during programing phase. Also connections are established to

match desired schematics. Programing data should be supplied by

any external data source, e.g. main memory, disk, processor

built.</p>

<p><i>NOTE: This

version does not support multiple FPGA connection, but FPGA

design can be easily adopted, connecting status registers in

Input Output Logic module. There is also no tristate support.</i></p>

<p>Full specification <a

href="http://www.opencores.org/cores/fpga/Fpga.pdf">Fpga.pdf (84k)</a>

.</p>

<p>More information

about the WISHBONE SoC and a full specification can be found <a

href="http://www.opencores.org/wishbone/">here</a>. </p>

<p><font size="4"><u></u></font> </p>

<p><font size="4"><u>Software

Description</u></font></p>

<p>Placement and

routing software is a tool, which automaticaly (or with some user

help) distributes given elements, so that they match certain

criteria. For FPGA (Field Programmable Gate Array) this criteria

usully is limited number of FPGA resources (connections, number

of programmable elements, speed of (or part of) circuit, etc).

More about resources and their functionality can be found in FPGA

Architecture document.</p>

<p>Command line utility is in development, which performs mapping,

placement and routing for specified

architecture. Currently it supports two input file types:</p>

<ul>

    <li>Verilog, GTECH library, technology independent</li>

    <li>EDIF, technology independent</li>

</ul>

<p>Since P&R is

NP-complete problem, no optimal practical solution for large

placement can be found, so we are forced to search for

sub-optimal solution.</p>

<p>KRPAN P&R Software Beta v0.1 is now available for download, but

it still needs a lot of work<br>

<a href="http://www.opencores.org/cores/fpga/KRPAN.jar">KRPAN.jar (118k)</a>

(Requires <a href="http://java.sun.com/products/jdk/1.2/index.html">Java Runtime Environment v1.2</a>).</p>

<p><code>.jar</code> files can be run using JRE on command line:<br>

<code>java -jar KRPAN.jar</code></p>

<p>Jar (code correctness) can be verified using Sun's <code>jarsigner</code> command line utility.

OpenCores (self published) certificate is available <a href="http://www.opencores.org/cores/fpga/opencores.cer">here</a><br>

<b>KRPAN P&R software is published under <a href="http://www.gnu.org">GNU</a> <a href="http://www.gnu.org/philosophy/categories.html">GPL</a> license, available <a href="http://www.opencores.org/cores/fpga/gpl.txt">here</a>.</b></p>

<p>Download KRPAN P&R API Documentation (<code>javadoc</code>)

<a href="http://www.opencores.org/cores/fpga/docs.jar">docs.jar (398k)</a>

.</p>

<p>Complete KRPAN P&R Java sources

<a href="http://www.opencores.org/cores/fpga/sources.jar">sources.jar (133k)</a>

.</p>

<p>Java programming

language was choosed, to allow full portabillity on several

platforms and faster development.<br>

Also we conjecture that Java will become more supported and used

and have more computing potential. Java console applications

require 70% to 250% the speed of maximally optimized C programs

to calculate same results (only Windows platform was tested, but

compilers provided by Sun share same code). It is estimated, for

this application, that Java would run 100% slower than matching C

program.</p>

<p>KRPAN screenshot after routing phase:<br>

<IMG SRC="sshot1.gif"></p>

<p>Preliminary SW documentation is available <a href="http://www.opencores.org/cores/fpga/fpga_sw.pdf">here</a> (PDF, 81k)</p>

<p><font size="4"><u>Status</u></font></p>

<ul>

    <li>P&R software coding started 15th february</li>

    <li>full source code available when first stable

        version will be reached - aproximately at end of March</li>

    <li><font color="#FF0000">HELP NEEDED</font> - more

        Verilog/Edif examples are needed to test, if you wish to

        help please contact us first before sending actual files.</li>

                <li><font color="#FF0000">SUGGESTIONS NEEDED.</font> You can help with

        architecture design - many things are still open.</li>

    <li>message will be posted to <code>cores@opencores.org</code> when any

        significant progress is made. <code>cores@opencores.org</code> is at the same time

        official mailing list for FPGA project.</li>

</ul>

<p> </p>

<p><font size="4"><u>Authors / Maintainers</u></font></p>

<p>Marko Mlinar - SW part, architecture<br>

<a href="mailto:markom@opencores.org_NOSPAM">markom@opencores.org</a>

<br>

Damjan Lampret - HW design<br>

<a href="mailto:lampret@opencores.org_NOSPAM">lampret@opencores.org</a>

</p>

<p>Feel free to send us comments, suggestions or bug reports.</p>

<p><font size="4"><u></u></font> </p>

<p><a NAME="LOG"><font size="4"><u>Change Log</u></font></a> </p>

<ul>

    <li>13/3/2001 MM Initial web page </li>

    <li>30/3/2001 MM Added KRPAN v0.1 </li>

    <li>5 /4/2001 MM Modifications to architecture, spec updated </li>

    <li>20/4/2001 MM first SW spec available, added screen shot </li>

</ul>

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