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# The 4vfx60ff672-10 part is chosen for this example design.
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# This value should be modified to match your device.
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CONFIG PART = 4vfx12ff668-10;
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NET "*tx_gmii_mii_clk_in_0_i" TNM_NET = "clk_phy_tx_clk0";
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TIMESPEC "TS_phy_tx_clk0" = PERIOD "clk_phy_tx_clk0" 7400 ps HIGH 50 %;
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NET "*tx_client_clk_in_0_i" TNM_NET = "clk_client_tx_clk0";
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TIMESPEC "TS_client_tx_clk0" = PERIOD "clk_client_tx_clk0" 7200 ps HIGH 50 %;
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NET "*rx_client_clk_in_0_i" TNM_NET = "clk_client_rx_clk0";
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TIMESPEC "TS_client_rx_clk0" = PERIOD "clk_client_rx_clk0" 7200 ps HIGH 50 %;
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NET "*mii_rx_clk_0_i" TNM_NET = "clk_phy_rx_clk0";
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TIMESPEC "TS_phy_rx_clk0" = PERIOD "clk_phy_rx_clk0" 7200 ps HIGH 50 %;
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NET "*host_clk_i" TNM_NET = "host_clock";
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TIMEGRP "clk_host" = "host_clock";
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TIMESPEC "TS_clk_host" = PERIOD "clk_host" 10000 ps HIGH 50 %;
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# Locate EMAC instance for timing closure
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INST "*v4_emac" LOC = "EMAC_X0Y0";
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#################### EMAC 0 MII Constraints ########################
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INST "*mii0?RXD_TO_MAC*" IOB = true;
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INST "*mii0?RX_DV_TO_MAC" IOB = true;
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INST "*mii0?RX_ER_TO_MAC" IOB = true;
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INST "mii_txd_0" IOSTANDARD = LVTTL;
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INST "mii_tx_en_0" IOSTANDARD = LVTTL;
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INST "mii_tx_er_0" IOSTANDARD = LVTTL;
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INST "mii_rxd_0" IOSTANDARD = LVTTL;
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INST "mii_rx_dv_0" IOSTANDARD = LVTTL;
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INST "mii_rx_er_0" IOSTANDARD = LVTTL;
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INST "mii_tx_clk_0" IOSTANDARD = LVTTL;
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INST "mii_rx_clk_0" IOSTANDARD = LVTTL;
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INST "mii_col_0" IOSTANDARD = LVTTL;
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INST "mii_crs_0" IOSTANDARD = LVTTL;
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INST "reset" IOSTANDARD = LVTTL;
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INST "phy_reset_0" IOSTANDARD = LVTTL;
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INST "hostclk" IOSTANDARD = LVTTL;
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INST "mii_txd_0" TNM = "sig_mii_tx_0";
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INST "mii_tx_en_0" TNM = "sig_mii_tx_0";
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INST "mii_tx_er_0" TNM = "sig_mii_tx_0";
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INST "mii_rxd_0" TNM = "sig_mii_rx_0";
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INST "mii_rx_dv_0" TNM = "sig_mii_rx_0";
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INST "mii_rx_er_0" TNM = "sig_mii_rx_0";
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# using recommended budget from the clause 22
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TIMEGRP "sig_mii_rx_0" OFFSET = IN 10 ns VALID 20 ns BEFORE "mii_rx_clk_0";
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TIMEGRP "sig_mii_tx_0" OFFSET = OUT 15 ns AFTER "mii_tx_clk_0";
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# Remove the following constraints if example design FIFOs are not used
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# These constraints cover any clock domain crossing for metastability.
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# Tx client FIFO:
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INST "*client_side_FIFO_emac0?tx_fifo_i?wr_col_window_pipe_0" TNM = "tx_metastable";
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INST "*client_side_FIFO_emac0?tx_fifo_i?wr_retran_frame_tog" TNM = "tx_metastable";
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INST "*client_side_FIFO_emac0?tx_fifo_i?wr_col_window_pipe_1" TNM = "tx_stable";
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INST "*client_side_FIFO_emac0?tx_fifo_i?wr_retran_frame_sync" TNM = "tx_stable";
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INST "*tx_fifo_i?wr_tran_frame_tog" TNM = "tx_metastable";
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INST "*tx_fifo_i?frame_in_fifo_sync" TNM = "tx_metastable";
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INST "*tx_fifo_i?wr_txfer_tog" TNM = "tx_metastable";
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INST "*tx_fifo_i?wr_rd_addr*" TNM = "tx_metastable";
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INST "*tx_fifo_i?wr_tran_frame_sync" TNM = "tx_stable";
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INST "*tx_fifo_i?frame_in_fifo" TNM = "tx_stable";
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INST "*tx_fifo_i?wr_txfer_tog_sync" TNM = "tx_stable";
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INST "*tx_fifo_i?wr_addr_diff*" TNM = "tx_stable";
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TIMESPEC "TS_tx_meta_protect" = FROM "tx_metastable" TO "tx_stable" 5 ns;
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# Rx client FIFO:
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INST "*rx_fifo_i?rd_store_frame_tog" TNM = "rx_metastable";
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INST "*rx_fifo_i?wr_rd_addr_gray_sync*" TNM = "rx_metastable";
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INST "*rx_fifo_i?rd_store_frame_sync" TNM = "rx_stable";
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INST "*rx_fifo_i?wr_rd_addr_gray*" TNM = "rx_stable";
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TIMESPEC "TS_rx_meta_protect" = FROM "rx_metastable" TO "rx_stable" 5 ns;
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# Location Constraints
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# Receiver signals
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INST "MII_RX_CLK_0" LOC = "B15";
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#INST "MII_RXD_0<7>" LOC = "A3";
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#INST "MII_RXD_0<6>" LOC = "B3";
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#INST "MII_RXD_0<5>" LOC = "A4";
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#INST "MII_RXD_0<4>" LOC = "B4";
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INST "MII_RXD_0<3>" LOC = "C4";
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INST "MII_RXD_0<2>" LOC = "D4";
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INST "MII_RXD_0<1>" LOC = "E1";
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INST "MII_RXD_0<0>" LOC = "F1";
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INST "MII_RX_DV_0" LOC = "A9";
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INST "MII_RX_ER_0" LOC = "B9";
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# Transmitter signals
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#INST "MII_TXD_0<7>" LOC = "G3";
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#INST "MII_TXD_0<6>" LOC = "H6";
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#INST "MII_TXD_0<5>" LOC = "H5";
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#INST "MII_TXD_0<4>" LOC = "G2";
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INST "MII_TXD_0<3>" LOC = "G1";
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INST "MII_TXD_0<2>" LOC = "H3";
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INST "MII_TXD_0<1>" LOC = "H2";
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INST "MII_TXD_0<0>" LOC = "H1";
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INST "MII_TX_EN_0" LOC = "F4";
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INST "MII_TX_ER_0" LOC = "F3";
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INST "MII_TX_CLK_0" LOC = "C15";
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# Other Phy signals
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INST "MII_COL_0" LOC = "E3";
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INST "MII_CRS_0" LOC = "D5";
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INST "PHY_RESET_0" LOC = "D10";
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#INST "SPEED_VECTOR_IN_0<0>" LOC = "";
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#INST "SPEED_VECTOR_IN_0<1>" LOC = "";
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# Other
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INST "HOSTCLK" LOC = "AE14";
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INST "RESET" LOC = "D6";
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