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//-----------------------------------------------------------------------------
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// Title : 10/100/1G Ethernet FIFO for 8-bit client I/F
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// Project : Virtex-4 Embedded Tri-Mode Ethernet MAC Wrapper
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// File : eth_fifo_8.v
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// Version : 4.8
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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2004-2010 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Description: This is the top level wrapper for the 10/100/1G Ethernet FIFO.
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// The top level wrapper consists of individual fifos on the
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// transmitter path and on the receiver path.
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//
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// Each path consists of an 8 bit local link to 8 bit client
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// interface FIFO.
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//-----------------------------------------------------------------------------
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`timescale 1ps / 1ps
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module eth_fifo_8
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(
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// Transmit FIFO MAC TX Interface
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tx_clk, // MAC transmit clock
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tx_reset, // Synchronous reset (tx_clk)
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tx_enable, // Clock enable for tx_clk
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tx_data, // Data to MAC transmitter
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tx_data_valid, // Valid signal to MAC transmitter
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tx_ack, // Ack signal from MAC transmitter
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tx_underrun, // Underrun signal to MAC transmitter
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tx_collision, // Collsion signal from MAC transmitter
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tx_retransmit, // Retransmit signal from MAC transmitter
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// Transmit FIFO Local-link Interface
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tx_ll_clock, // Local link write clock
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tx_ll_reset, // synchronous reset (tx_ll_clock)
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tx_ll_data_in, // Data to Tx FIFO
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tx_ll_sof_in_n, // sof indicator to FIFO
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tx_ll_eof_in_n, // eof indicator to FIFO
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tx_ll_src_rdy_in_n, // src ready indicator to FIFO
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tx_ll_dst_rdy_out_n, // dst ready indicator from FIFO
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tx_fifo_status, // FIFO memory status
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tx_overflow, // FIFO overflow indicator from FIFO
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// Receive FIFO MAC RX Interface
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rx_clk, // MAC receive clock
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rx_reset, // Synchronous reset (rx_clk)
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rx_enable, // Clock enable for rx_clk
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rx_data, // Data from MAC receiver
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rx_data_valid, // Valid signal from MAC receiver
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rx_good_frame, // Good frame indicator from MAC receiver
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rx_bad_frame, // Bad frame indicator from MAC receiver
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rx_overflow, // FIFO overflow indicator from FIFO
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// Receive FIFO Local-link Interface
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rx_ll_clock, // Local link read clock
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rx_ll_reset, // synchronous reset (rx_ll_clock)
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rx_ll_data_out, // Data from Rx FIFO
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rx_ll_sof_out_n, // sof indicator from FIFO
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rx_ll_eof_out_n, // eof indicator from FIFO
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rx_ll_src_rdy_out_n, // src ready indicator from FIFO
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rx_ll_dst_rdy_in_n, // dst ready indicator to FIFO
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rx_fifo_status // FIFO memory status
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);
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//---------------------------------------------------------------------------
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// Define Interface Signals
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//---------------------------------------------------------------------------
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parameter FULL_DUPLEX_ONLY = 0;
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// Transmit FIFO MAC TX Interface
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input tx_clk;
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input tx_reset;
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input tx_enable;
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output [7:0] tx_data;
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output tx_data_valid;
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input tx_ack;
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output tx_underrun;
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input tx_collision;
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input tx_retransmit;
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// Transmit FIFO Local-link Interface
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input tx_ll_clock;
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input tx_ll_reset;
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input [7:0] tx_ll_data_in;
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input tx_ll_sof_in_n;
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input tx_ll_eof_in_n;
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input tx_ll_src_rdy_in_n;
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output tx_ll_dst_rdy_out_n;
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output [3:0] tx_fifo_status;
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output tx_overflow;
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// Receive FIFO MAC RX Interface
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input rx_clk;
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input rx_reset;
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input rx_enable;
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input [7:0] rx_data;
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input rx_data_valid;
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input rx_good_frame;
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input rx_bad_frame;
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output rx_overflow;
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// Receive FIFO Local-link Interface
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input rx_ll_clock;
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input rx_ll_reset;
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output [7:0] rx_ll_data_out;
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output rx_ll_sof_out_n;
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output rx_ll_eof_out_n;
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output rx_ll_src_rdy_out_n;
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input rx_ll_dst_rdy_in_n;
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output [3:0] rx_fifo_status;
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assign tx_underrun = 1'b0;
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// Transmitter FIFO
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defparam tx_fifo_i.FULL_DUPLEX_ONLY = FULL_DUPLEX_ONLY;
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tx_client_fifo_8 tx_fifo_i (
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.rd_clk (tx_clk),
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.rd_sreset (tx_reset),
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.rd_enable (tx_enable),
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.tx_data (tx_data),
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.tx_data_valid (tx_data_valid),
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.tx_ack (tx_ack),
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.tx_collision (tx_collision),
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.tx_retransmit (tx_retransmit),
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.overflow (tx_overflow),
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.wr_clk (tx_ll_clock),
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.wr_sreset (tx_ll_reset),
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.wr_data (tx_ll_data_in),
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.wr_sof_n (tx_ll_sof_in_n),
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.wr_eof_n (tx_ll_eof_in_n),
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.wr_src_rdy_n (tx_ll_src_rdy_in_n),
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.wr_dst_rdy_n (tx_ll_dst_rdy_out_n),
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.wr_fifo_status (tx_fifo_status)
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);
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// Receiver FIFO
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rx_client_fifo_8 rx_fifo_i (
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.wr_clk (rx_clk),
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.wr_enable (rx_enable),
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.wr_sreset (rx_reset),
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.rx_data (rx_data),
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.rx_data_valid (rx_data_valid),
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.rx_good_frame (rx_good_frame),
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.rx_bad_frame (rx_bad_frame),
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.overflow (rx_overflow),
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.rd_clk (rx_ll_clock),
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.rd_sreset (rx_ll_reset),
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.rd_data_out (rx_ll_data_out),
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.rd_sof_n (rx_ll_sof_out_n),
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.rd_eof_n (rx_ll_eof_out_n),
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.rd_src_rdy_n (rx_ll_src_rdy_out_n),
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.rd_dst_rdy_n (rx_ll_dst_rdy_in_n),
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.rx_fifo_status (rx_fifo_status)
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);
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endmodule
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