1 |
2 |
peteralieb |
//----------------------------------------------------------------------
|
2 |
|
|
// Title : Media Independent Interface (MII) Physical Interface
|
3 |
|
|
// Project : Virtex-4 Embedded Tri-Mode Ethernet MAC Wrapper
|
4 |
|
|
// File : mii_if.v
|
5 |
|
|
// Version : 4.8
|
6 |
|
|
//-----------------------------------------------------------------------------
|
7 |
|
|
//
|
8 |
|
|
// (c) Copyright 2004-2010 Xilinx, Inc. All rights reserved.
|
9 |
|
|
//
|
10 |
|
|
// This file contains confidential and proprietary information
|
11 |
|
|
// of Xilinx, Inc. and is protected under U.S. and
|
12 |
|
|
// international copyright and other intellectual property
|
13 |
|
|
// laws.
|
14 |
|
|
//
|
15 |
|
|
// DISCLAIMER
|
16 |
|
|
// This disclaimer is not a license and does not grant any
|
17 |
|
|
// rights to the materials distributed herewith. Except as
|
18 |
|
|
// otherwise provided in a valid license issued to you by
|
19 |
|
|
// Xilinx, and to the maximum extent permitted by applicable
|
20 |
|
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
21 |
|
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
22 |
|
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
23 |
|
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
24 |
|
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
25 |
|
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
26 |
|
|
// including negligence, or under any other theory of
|
27 |
|
|
// liability) for any loss or damage of any kind or nature
|
28 |
|
|
// related to, arising under or in connection with these
|
29 |
|
|
// materials, including for any direct, or any indirect,
|
30 |
|
|
// special, incidental, or consequential loss or damage
|
31 |
|
|
// (including loss of data, profits, goodwill, or any type of
|
32 |
|
|
// loss or damage suffered as a result of any action brought
|
33 |
|
|
// by a third party) even if such damage or loss was
|
34 |
|
|
// reasonably foreseeable or Xilinx had been advised of the
|
35 |
|
|
// possibility of the same.
|
36 |
|
|
//
|
37 |
|
|
// CRITICAL APPLICATIONS
|
38 |
|
|
// Xilinx products are not designed or intended to be fail-
|
39 |
|
|
// safe, or for use in any application requiring fail-safe
|
40 |
|
|
// performance, such as life-support or safety devices or
|
41 |
|
|
// systems, Class III medical devices, nuclear facilities,
|
42 |
|
|
// applications related to the deployment of airbags, or any
|
43 |
|
|
// other applications that could lead to death, personal
|
44 |
|
|
// injury, or severe property or environmental damage
|
45 |
|
|
// (individually and collectively, "Critical
|
46 |
|
|
// Applications"). Customer assumes the sole risk and
|
47 |
|
|
// liability of any use of Xilinx products in Critical
|
48 |
|
|
// Applications, subject only to applicable laws and
|
49 |
|
|
// regulations governing limitations on product liability.
|
50 |
|
|
//
|
51 |
|
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
52 |
|
|
// PART OF THIS FILE AT ALL TIMES.
|
53 |
|
|
//
|
54 |
|
|
//----------------------------------------------------------------------
|
55 |
|
|
// Description: This module creates a Media Independent Interface (MII)
|
56 |
|
|
// by instantiating Input/Output buffers and Input/Output
|
57 |
|
|
// flip-flops as required.
|
58 |
|
|
//
|
59 |
|
|
// This interface is used to connect the Ethernet MAC to
|
60 |
|
|
// an external 10Mb/s and 100Mb/s Ethernet PHY.
|
61 |
|
|
//----------------------------------------------------------------------
|
62 |
|
|
//
|
63 |
|
|
|
64 |
|
|
`timescale 1 ps / 1 ps
|
65 |
|
|
|
66 |
|
|
module mii_if (
|
67 |
|
|
RESET,
|
68 |
|
|
// MII Interface
|
69 |
|
|
MII_TXD,
|
70 |
|
|
MII_TX_EN,
|
71 |
|
|
MII_TX_ER,
|
72 |
|
|
MII_RXD,
|
73 |
|
|
MII_RX_DV,
|
74 |
|
|
MII_RX_ER,
|
75 |
|
|
MII_COL,
|
76 |
|
|
MII_CRS,
|
77 |
|
|
// MAC Interface
|
78 |
|
|
TXD_FROM_MAC,
|
79 |
|
|
TX_EN_FROM_MAC,
|
80 |
|
|
TX_ER_FROM_MAC,
|
81 |
|
|
TX_CLK,
|
82 |
|
|
RXD_TO_MAC,
|
83 |
|
|
RX_DV_TO_MAC,
|
84 |
|
|
RX_ER_TO_MAC,
|
85 |
|
|
RX_CLK,
|
86 |
|
|
MII_COL_TO_MAC,
|
87 |
|
|
MII_CRS_TO_MAC);
|
88 |
|
|
|
89 |
|
|
input RESET;
|
90 |
|
|
output [3:0] MII_TXD;
|
91 |
|
|
output MII_TX_EN;
|
92 |
|
|
output MII_TX_ER;
|
93 |
|
|
input [3:0] MII_RXD;
|
94 |
|
|
input MII_RX_DV;
|
95 |
|
|
input MII_RX_ER;
|
96 |
|
|
input MII_COL;
|
97 |
|
|
input MII_CRS;
|
98 |
|
|
input [3:0] TXD_FROM_MAC;
|
99 |
|
|
input TX_EN_FROM_MAC;
|
100 |
|
|
input TX_ER_FROM_MAC;
|
101 |
|
|
input TX_CLK;
|
102 |
|
|
output [3:0] RXD_TO_MAC;
|
103 |
|
|
output RX_DV_TO_MAC;
|
104 |
|
|
output RX_ER_TO_MAC;
|
105 |
|
|
input RX_CLK;
|
106 |
|
|
output MII_COL_TO_MAC;
|
107 |
|
|
output MII_CRS_TO_MAC;
|
108 |
|
|
|
109 |
|
|
reg mii_tx_en_r;
|
110 |
|
|
reg mii_tx_er_r;
|
111 |
|
|
reg [3:0] mii_txd_r;
|
112 |
|
|
|
113 |
|
|
wire mii_rx_dv_i;
|
114 |
|
|
wire mii_rx_er_i;
|
115 |
|
|
wire [3:0] mii_rxd_i;
|
116 |
|
|
|
117 |
|
|
wire mii_col_i;
|
118 |
|
|
wire mii_crs_i;
|
119 |
|
|
wire mii_tx_clk_i;
|
120 |
|
|
reg reg_mii_col;
|
121 |
|
|
reg reg_reg_mii_col;
|
122 |
|
|
|
123 |
|
|
reg [3:0] RXD_TO_MAC;
|
124 |
|
|
reg RX_DV_TO_MAC;
|
125 |
|
|
reg RX_ER_TO_MAC;
|
126 |
|
|
|
127 |
|
|
//------------------------------------------------------------------------
|
128 |
|
|
// MII Transmitter Logic : Drive TX signals through IOBs onto MII
|
129 |
|
|
// interface
|
130 |
|
|
//------------------------------------------------------------------------
|
131 |
|
|
// Infer IOB Output flip-flops.
|
132 |
|
|
always @(posedge TX_CLK, posedge RESET)
|
133 |
|
|
begin
|
134 |
|
|
if (RESET == 1'b1)
|
135 |
|
|
begin
|
136 |
|
|
mii_tx_en_r <= 1'b0;
|
137 |
|
|
mii_tx_er_r <= 1'b0;
|
138 |
|
|
mii_txd_r <= 8'h00;
|
139 |
|
|
end
|
140 |
|
|
else
|
141 |
|
|
begin
|
142 |
|
|
mii_tx_en_r <= TX_EN_FROM_MAC;
|
143 |
|
|
mii_tx_er_r <= TX_ER_FROM_MAC;
|
144 |
|
|
mii_txd_r <= TXD_FROM_MAC;
|
145 |
|
|
end
|
146 |
|
|
end
|
147 |
|
|
|
148 |
|
|
// Drive MII TX signals through Output Buffers and onto PADS
|
149 |
|
|
OBUF mii_tx_en_obuf (.I(mii_tx_en_r), .O(MII_TX_EN));
|
150 |
|
|
OBUF mii_tx_er_obuf (.I(mii_tx_er_r), .O(MII_TX_ER));
|
151 |
|
|
|
152 |
|
|
OBUF mii_txd0_obuf (.I(mii_txd_r[0]), .O(MII_TXD[0]));
|
153 |
|
|
OBUF mii_txd1_obuf (.I(mii_txd_r[1]), .O(MII_TXD[1]));
|
154 |
|
|
OBUF mii_txd2_obuf (.I(mii_txd_r[2]), .O(MII_TXD[2]));
|
155 |
|
|
OBUF mii_txd3_obuf (.I(mii_txd_r[3]), .O(MII_TXD[3]));
|
156 |
|
|
|
157 |
|
|
//------------------------------------------------------------------------
|
158 |
|
|
// MII Receiver Logic : Receive RX signals through IOBs from MII
|
159 |
|
|
// interface
|
160 |
|
|
//------------------------------------------------------------------------
|
161 |
|
|
// Drive input MII Rx signals from PADS through Input Buffers and then
|
162 |
|
|
// use IDELAYs to provide Zero-Hold Time Delay
|
163 |
|
|
IBUF mii_rx_dv_ibuf (.I(MII_RX_DV), .O(mii_rx_dv_i));
|
164 |
|
|
|
165 |
|
|
IBUF mii_rx_er_ibuf (.I(MII_RX_ER), .O(mii_rx_er_i));
|
166 |
|
|
|
167 |
|
|
IBUF mii_rxd0_ibuf (.I(MII_RXD[0]), .O(mii_rxd_i[0]));
|
168 |
|
|
|
169 |
|
|
IBUF mii_rxd1_ibuf (.I(MII_RXD[1]), .O(mii_rxd_i[1]));
|
170 |
|
|
|
171 |
|
|
IBUF mii_rxd2_ibuf (.I(MII_RXD[2]), .O(mii_rxd_i[2]));
|
172 |
|
|
|
173 |
|
|
IBUF mii_rxd3_ibuf (.I(MII_RXD[3]), .O(mii_rxd_i[3]));
|
174 |
|
|
|
175 |
|
|
// Infer IOB Input flip-flops
|
176 |
|
|
always @ (posedge RX_CLK, posedge RESET)
|
177 |
|
|
begin
|
178 |
|
|
if (RESET == 1'b1)
|
179 |
|
|
begin
|
180 |
|
|
RX_DV_TO_MAC <= 1'b0;
|
181 |
|
|
RX_ER_TO_MAC <= 1'b0;
|
182 |
|
|
RXD_TO_MAC <= 4'h0;
|
183 |
|
|
end
|
184 |
|
|
else
|
185 |
|
|
begin
|
186 |
|
|
RX_DV_TO_MAC <= mii_rx_dv_i;
|
187 |
|
|
RX_ER_TO_MAC <= mii_rx_er_i;
|
188 |
|
|
RXD_TO_MAC <= mii_rxd_i;
|
189 |
|
|
end
|
190 |
|
|
end
|
191 |
|
|
|
192 |
|
|
// Half Duplex signals
|
193 |
|
|
IBUF mii_col_obuf (.I(MII_COL), .O(mii_col_i));
|
194 |
|
|
IBUF mii_crs_obuf (.I(MII_CRS), .O(mii_crs_i));
|
195 |
|
|
|
196 |
|
|
always @(posedge RESET, posedge TX_CLK)
|
197 |
|
|
begin
|
198 |
|
|
if (RESET == 1'b1)
|
199 |
|
|
begin
|
200 |
|
|
reg_mii_col <= 1'b0;
|
201 |
|
|
reg_reg_mii_col <= 1'b0;
|
202 |
|
|
end
|
203 |
|
|
else
|
204 |
|
|
begin
|
205 |
|
|
reg_mii_col <= mii_col_i;
|
206 |
|
|
reg_reg_mii_col <= reg_mii_col;
|
207 |
|
|
end
|
208 |
|
|
end
|
209 |
|
|
|
210 |
|
|
assign MII_COL_TO_MAC = mii_col_i | reg_mii_col | reg_reg_mii_col;
|
211 |
|
|
assign MII_CRS_TO_MAC = mii_crs_i;
|
212 |
|
|
|
213 |
|
|
endmodule
|